JPH11149376A - Boot loader circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a more flexible software development environment by realizing the same function with a circuit mounting an Initial Program Loader ROM in circuit constitution of a smaller scale. SOLUTION: A BOOT loader circuit is provided with a BOOT detection part 4 for detecting whether a system becomes a BOOT mode or not, an address decoder 5 for generating a selection signal for each device, switch parts 6 and 7 for selecting ROM and the external input interface and a CPU stop control part 8 for instructing the stop of CPU various conditions.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a boot loader circuit, and more particularly to a boot loader circuit in a control device having an external communication interface means, which can write data into a ROM without holding a program for the external communication interface means.

[0002]

2. Description of the Related Art For a very small electronic device such as a cellular phone, a configuration for reducing the size and weight is required.
A method has been devised. The above electronic devices usually include a CPU.
And a writable RO after mounting on a flash ROM etc.
M and a control device having an external input interface. The control device further includes an IPL-ROM separately from the ROM. The IPL-ROM is an initial program loader ROM, which stores a program necessary for operating the CPU when no program is stored in the ROM or when the program is updated to a new version. ROM. If a program to be stored in the IPL-ROM is stored in a ROM for holding other programs, the program written in the ROM cannot be executed during the ROM writing operation. It is necessary to store the data once and execute the rewriting program on the RAM. The IPL-ROM is used to solve the problem. FIG. 4 is a block diagram showing a typical example of a circuit configuration using a conventional IPL-ROM. In the figure, reference numeral 1 denotes a BOOT detection or changeover switch unit, which is an IPL-R
This is a mechanism for selecting whether to start with the OM or with the ROM, and performs a manual changeover switch, a changeover by an automatic operation using a control signal, and the like, and outputs the result to a signal b.
To the address decoder 2. Address decoder 2
Decodes an address based on a control signal group a of the CPU and the signal b and outputs an IPL-ROM selection signal c, a selection signal d of a rewritable ROM after mounting, and other selection signals e. ROM.

[0003]

However, since the control device requires an IPL-ROM, the number of parts increases. Further, in the case of a one-chip CPU with a built-in ROM, there is a drawback that a built-in ROM which can be accessed at high speed is occupied because of a function which is hardly used usually. SUMMARY OF THE INVENTION The present invention has been made in order to eliminate the drawbacks of the conventional BOOT loader circuit as described above. It is intended to provide a circuit.

[0004]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a CPU and a writable ROM after mounting.
In a control device having a working RAM of a CPU and an external communication interface means, when a ROM in which a program is not stored is mounted, or when it is necessary to overwrite an old program for updating a program, In addition, the present invention is characterized in that a command is directly given to the CPU through the external communication interface means without depending on the contents of the ROM, and the CPU is operated so that the control device can write into the ROM without having a program.
Also, the control device uses the WAIT time function when the CPU accesses the slow-responding memory after detecting that the CPU reads the instruction from the ROM, and instructs the data obtained through the external communication interface means to execute the instruction. It is characterized by being executed as Further, the control device is C
When the PU reads an instruction from the ROM, the operation clock of the CPU is stopped, and when an input is provided to the external communication interface means, the clock is re-operated to cause the CPU to read the ROM.
In this case, data obtained by the external communication interface is executed as an instruction instead of the data.

[0005]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on embodiments shown in the drawings. FIG. 1 shows a BO according to the invention.
FIG. 2 is a diagram illustrating a schematic configuration example of an OT loader circuit. The circuit shown in FIG. 1 includes a BOOT detection unit 4 having a function of detecting that the device is in the BOOT mode, a CPU stop control unit 8 that receives the result, and stops the operation of the CPU, and a selection signal for each device. And an address decoder 5 for generating
A switch 6 and a switch 7 for setting selection conditions of the OOT mode are provided. The operation in this configuration will be described.
First, in a device equipped with the BOOT loader circuit,
Whether the device transitions to the BOOT mode state is determined by the BOO
The T detector 4 detects whether or not to enter the BOOT mode, and determines by holding the BOOT mode shift request of the control signal a by the reset signal c. The selection signal b is B
It is used to return from the BOOT mode to the normal mode as a request to release the OOT mode. The control signal f indicates a signal due to the bus connection of the CPU, includes a CPU read signal of the control signal e, and generates a selection signal for each device by the address decoder 5. The selection signal g indicates an internal selection signal of the ROM, and the read of the ROM can be detected by the selection signal g and the control signal e. h is a ROM external selection signal;
When the BOOT mode signal of the control signal i is in the normal mode by the switching unit 6, it is not selected in the BOOT mode as in the case of the selection signal g. j indicates an internal selection signal of the external input interface. When the control signal i is in the normal mode by the switching unit 7, the external selection signal k of the external input interface is the selection signal g in the BOOT mode in the same manner as the selection signal j. And is selected instead of the ROM. When the control signal i is in the BOOT mode, the selection signal g selects ROM, the control signal e is being read, and the input completion signal of the external input interface of the control signal d is not completed when the control signal i is in the BOOT mode. Only the control signal 1 instructs CPU stop. At this time, as soon as the control signal d becomes a completion signal, the CPU resumes its operation and reads and executes the data of the external input interface. The selection signal k is R
The AM selection signal and selection signal l are other selection signals,
Make what you need in the control unit. After setting the BOOT mode by the control signal a and inputting data from the external input interface in the same order as the CPU reads from the ROM, the CPU can operate as expected.
For example, if the CPU first transfers data from the ROM (actually an external input interface) to the RAM and then jumps to the RAM and sends a program for executing the RAM program (ROM writing program, etc.), the CPU executes the program within the capacity of the RAM. Possible programs can be executed. Also, if there is not enough RAM capacity, the execution speed is low, but R
It is also possible to write OM.

FIG. 2 shows an example of an operation flowchart of the BOOT loader circuit according to the present invention. Before the reset of the control device is released and the CPU is started, it is determined whether a normal mode or a BOOT mode is set by a switch or a predetermined control signal. The normal mode is a mode in which the CPU normally reads the ROM and operates. BOO
The T mode is a mode in which the operation described below is performed only when the CPU attempts to read the ROM, and other operations of the CPU are the same as those in the normal mode. In the boot mode, when the CPU detects that the CPU has attempted to read the ROM, the CPU executes the ROM
The CPU is stopped before reading of data is completed, and waits until data is input to the external communication interface. Further, after outputting the input data to the data bus of the CPU instead of the data of the ROM, the operation of the CPU is restarted. Therefore, by causing the CPU to execute the data of the external communication interface as a command, the CPU is executed without the IPL-ROM.
It is intended to operate the PU. Then, by applying this, it becomes possible to write data into the ROM.

The external communication interface is roughly classified into a parallel interface and a serial interface. The operation after this interface is the same, and the following example will be described using the serial interface. FIG. 3 is a schematic configuration diagram showing an embodiment when an external communication interface of a control device incorporating the present invention is connected to a personal computer through an RS232C serial interface and a program is written in ROM. The figure shows a personal computer 9 for sending a program for operating the CPU of the control device.
And a control device 10 using the present invention, and a circuit group 11 necessary for the other devices is a collection of portions unrelated to the description of the present invention. The personal computer 9 and the control device 10 are connected by a serial interface m of the RS232C standard, the level converter 12 converts the voltage level of the RS232C into the voltage level of the control device, and the serial reception interface 13 converts the input data a into parallel data. In the BOOT mode, the parallel data is output to the data bus of the CPU bus for the control signal f. The BOOT loader circuit 14 is according to the present invention, and the symbols representing signal lines correspond to those in FIG. In this example, the serial input data a is transmitted to the system reset circuit 1
5 is held at the timing of the reset signal c, and when the input data is 0, the BOOT mode is set, and when the input data is 1, the normal mode is set. k is a serial interface selection signal, d is a serial interface reception flag, l is a CPU 16 stop signal, n is a RAM 17 selection signal, h
Is a selection signal of the ROM 18, and p is a selection signal of the control device. In this example, the BOOT mode release signal b is generated by the CPU read signal e and the RAM selection signal k.
BOOT when PU16 tries to read RAM17
Although the mode is released, the release signal b may be generated under other conditions.

The stop signal m of the CPU 16 is
An example in which the AIT signal is used is described in claim 2, and the stoppable CP
An example in which the U clock is used is shown in claim 3. In order to write in the ROM 18, in a state where the signal a is set to 0 by means of transmission of a break character from the personal computer 9 or the like, the power of the control device 10 is turned on or the system reset circuit 15 resets the control device 10.
Is in the BOOT mode as described above. So, CPU
16 sends a program for writing the IPL program to the RAM 17 through the control signal m from the personal computer 9 in the same order as the data is read from the ROM 18;
An instruction to jump to the execution address of the program written in 17 is sent. Further, the CPU 16 reads the program on the RAM 17 and attempts to execute the program. At this point, the RAM read occurs, the BOOT mode is released, and the program on the RAM 17 starts running. After that RAM1
7 can be used to write the program in the ROM 18.

[0009]

Since the present invention is configured as described above, it has a remarkable effect in reducing the circuit scale and diversifying the software development means.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram showing an example of a BOOT loader circuit according to the present invention.

FIG. 2 is a configuration diagram showing an example of an operation flowchart according to the present invention;

FIG. 3 is a schematic configuration diagram showing one embodiment when a BOOT loader circuit according to the present invention is applied to a serial interface;

FIG. 4 is a configuration diagram showing a circuit example incorporating a conventional IPL-ROM;

[Explanation of symbols]

1 ··· BOOT detection or changeover switch unit 2 ···
・ Address decoder, 3 ... IPL-ROM, 4
... BOOT detection unit, 5 ... address decoder,
6 switching unit, 7 switching unit, 8 CP
U-stop control unit, 9 ... PC, 10 ...
Control device, 11 ... other circuits required for the device,
12: level conversion unit, 13: serial reception interface, 14: BOOT loader circuit,
15: System reset circuit, 16: CP
U, 17 ... RAM, 18 ... ROM

Claims (3)

[Claims] A CPU, a writable nonvolatile memory (hereinafter referred to as a ROM) after mounting, and a work RA of the CPU.
M and a control device having external communication interface means, when a ROM in which a program is not stored is mounted or when it is necessary to overwrite an old program for updating a program, it does not depend on the contents of the ROM. CPU directly through external communication interface means
A boot loader circuit configured to be operated by giving an instruction to the controller so that the controller can write the data into the ROM without having a program. 2. Using the wait time when the CPU accesses a memory with a slow response after the CPU detects that the instruction is read from the ROM, the data obtained through the external communication interface means is executed as the instruction. 2. The BOOT loader circuit according to claim 1, wherein: 3. When the CPU reads an instruction from the ROM, the CPU
The operation clock of U is stopped, and the clock is restarted when there is an input to the external communication interface means.
2. The BOOT loader circuit according to claim 1, wherein the PUOT causes the PU to execute, as an instruction, data obtained by the external communication interface instead of the ROM data.