JP3745031B2 - CPU accelerator - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a CPU accelerator, and more particularly to a CPU accelerator including a CPU having a write-back cache function.
[0002]
[Prior art]
The CPU accelerator is mounted on a computer (hereinafter referred to as a PC) having an old CPU, and the processing is compensated for by a newer CPU to increase the speed. The modernization of the CPU adds various new functions. For example, the CPU of the next generation or later may have a write-back cache function that was not available in a certain generation.
[0003]
The function of the write-back cache needs to prevent inconsistency between the contents of the cache memory in the CPU and the original external memory. For this reason, a hardware circuit that monitors the access to the external memory by the external device in hardware and forms a signal to be flashed by the CPU when the external device tries to access the external memory is required.
However, it is not premised that the old PC has such a write-back cache function. Therefore, there is no reason to have such a hardware circuit. Even if a conventional CPU accelerator has a CPU having a write-back cache function, the write-back mode for pulling down the write-back cache function is pulled down to write-through mode. It can be operated only with.
[0004]
Even if there is no hardware circuit described above for using the write-back cache function, software can monitor access to the external memory and flush the contents of the internal cache memory when an access request occurs. Is possible. Here, when the CPU is started in the write-through mode, it is not possible to shift from the write-through mode to the write-back mode, and when the CPU is started in the write-back mode, it is possible to shift between the two modes. There is. Therefore, the CPU must be started in the write-back mode and the procedure for loading the software must be taken. However, in such a procedure, cache inconsistency occurs after the CPU is started in the write-back mode until the software is loaded and started.
[0005]
In the end, the write-back cache function is not used because it does not have the necessary hardware circuitry and cannot load software.
[0006]
[Problems to be solved by the invention]
The conventional CPU accelerator described above has a problem that the write back cache function cannot be used while using a CPU having the write back cache function.
The present invention has been made in view of the above-described problems. A CPU accelerator capable of realizing a write-back cache function even when the PC main body does not have a necessary hardware circuit for the write-back cache function. For the purpose of provision.
[0007]
[Means for Solving the Problems]
In order to achieve the above object, the invention according to claim 1 is incapable of shifting from the write-through mode to the write-back mode after starting up when started up in the write-through mode, and when started up in write-back mode. A CPU accelerator having a CPU with a write-back cache function that can be switched between the write-back mode and the write-through mode after raising, and that rises in the write-back mode when a write-back signal is given at reset. The CPU is started up in the back mode and has a write back start control means for shifting to the write through mode immediately after the start.
[0008]
According to the present invention having such a configuration, the write back startup control means starts up in the write back mode when the CPU starts up, and shifts to the write through mode immediately after startup. Therefore, since the memory is actually in the write-through mode, there is no memory mismatch even if various initial setting processes are executed. On the other hand, since the memory is originally in the write-back mode, the write-through mode is used for writing. It is possible to shift to the back mode, and it is sufficient to shift to the write back mode after the environment necessary for software is prepared.
[0009]
The method of starting up in the write-back mode when starting up the CPU, or shifting to the write-through mode immediately after that can be appropriately changed according to the specifications of the CPU, as long as the above-described start-up process can be executed substantially.
For example, the write back mode corresponds to whether or not the write back terminal is enabled. By giving a write back signal at the time of reset, the write back terminal is enabled thereafter. Even if it is a specification that can be done, it can be said that it actually stands up in the write-back mode. As another example, in the invention according to claim 2, in the CPU accelerator according to claim 1, the write-back start-up control means turns on the write-back signal when the reset signal to the CPU is turned on. And a write back signal control circuit that turns off the write back signal when the reset signal is turned off.
[0010]
As a specification of the CPU, when a write back signal is given at the time of reset, the CPU may start up in a write back mode. In this case, when the reset signal for the CPU is turned on, the write back signal control circuit turns on the write back signal, and when the reset signal is turned off, the write back signal is turned off. At the same time, immediately after the reset signal is turned off and the rise is completed, the write back signal is turned off and the mode shifts to the write-through mode.
[0011]
Therefore, substantially the same processing as in claim 1 can be executed. Of course, signal characteristics such as on / off polarity and timing in the reset signal and the write-back signal can be appropriately changed according to the specifications of the CPU, and the detailed configuration of the write-back signal control circuit is not particularly limited. .
As an example of this, the invention according to claim 3 is the CPU accelerator according to claim 2, wherein the write-back signal control circuit is capable of outputting a port signal for the write-back mode when a predetermined control signal is inputted. A back port and a logical sum circuit that takes the logical sum of the reset signal and the port signal and outputs the logical sum signal to the write back terminal in the CPU are provided.
[0012]
According to the present invention having such a configuration, a write-back port is provided, and a port signal for the write-back mode can be normally output by inputting a predetermined control signal from the CPU. Sometimes the same port signal is not output. This port signal is input to the logical sum circuit, and the logical sum signal is input to the write back terminal of the CPU. By controlling the sending of the control signal to the port by the CPU, the write back mode and the write through mode are controlled. Can be migrated between. On the other hand, since the reset signal is also input to the above OR circuit, if the reset signal is turned on to reset the CPU, the ON signal is also input to the write back terminal through the OR circuit at the same time. Will stand up at.
[0013]
Further, according to a fourth aspect of the present invention, in the CPU accelerator according to any one of the first to third aspects, the access to the external memory is monitored, and the internal cache memory of the CPU is inconsistent with the external memory. The cache management software for performing write back is executed so as not to occur, and the cache management software is used to shift from the write-through mode to the write-back mode.
As described above, it is possible to shift from the write-through mode to the write-back mode, and when the cache management software is loaded to prevent the inconsistency of the memory, the software shifts to the write-back mode. Then, the access to the external memory by an external device or the like is monitored, and a write-back is performed as appropriate so that the internal cache memory and the external memory do not become inconsistent. Of course, when the external memory is accessed from the CPU, inconsistency does not occur, so it is not always necessary to write back. As a specific method of writing back, the contents of the internal cache memory may be flushed when there is no direct writing back command.
[0014]
Note that the write-back is performed by monitoring access to the external memory by an external device or the like, but there are various monitoring methods. For example, a DMA controller that manages memory access may be directly monitored, or a BIOS call that substantially causes memory access may be monitored. Depending on the degree, inconsistency may be accepted, and performance such as processing speed may be prioritized. Furthermore, after the transition from the write-through mode to the write-back mode, the transition may be made appropriately between the write-through mode and the write-back mode as necessary.
[0015]
【The invention's effect】
As described above, the present invention can provide a CPU accelerator that can execute a write-back cache function of a CPU even in a PC that does not include a hardware circuit for a write-back cache.
According to the invention of claim 2, it can be realized with a simple circuit by controlling the write-back signal in synchronization with the reset signal.
Further, according to the invention of claim 3, since the port used in the PC is used, for example, if the circuit has a margin in the port, it is realized with an extremely easy configuration by adding an OR circuit. it can.
[0016]
Furthermore, according to the fourth aspect of the invention, the cache management software is surely loaded and then the mode shifts to the write-back mode, so that the reliability of the system can be improved.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing a schematic configuration of a PC to which a CPU accelerator according to an embodiment of the present invention is applied. FIG. 2 is a block diagram showing a main configuration of the CPU accelerator.
[0018]
In FIG. 1, a computer (PC) 10 includes a data bus 20 to which a CPU accelerator 30, a main memory (hereinafter referred to as an external memory) 40, an external device interface 50, and the like are connected. The CPU accelerator 30 includes a CPU 31 having an internal level 1 cache (hereinafter referred to as an internal cache memory), and the CPU 31 is connected to the external memory 40 via the data bus 20.
[0019]
The CPU 31 has a write-back cache function and has a write-back (W / B) terminal 32 for switching modes. In order to make the write back mode valid, it is necessary to give an ON signal to the write back terminal 32 at the time of start-up and to start up in the write back mode, whereby the write back terminal 32 becomes effective thereafter. Therefore, even after the start-up, if the on signal is given to the write back terminal 32, the write back mode is set, and if the off signal is given, the write through mode is set. However, when starting up in the write-through mode, the write-through mode is always set regardless of whether the signal to the write-back terminal 32 is on or off.
[0020]
Since this relates to the CPU specifications, the present invention can be applied when it is necessary to externally provide a write back permission signal. For example, when the write back is controlled by a register in the CPU. Is not necessary. On the other hand, the present invention can be widely applied as long as it determines whether to give a write back permission signal externally.
The CPU accelerator 30 is equipped with a decoder 33 together with the CPU 31, and the output of the decoder 33 is connected to the write terminal of the port 34. Here, the CPU 31 can send a predetermined code signal to the decoder 33 depending on whether the write back mode or the write through mode is set, and the code signal C1 for the write back mode is sent to the decoder 33. When output, the decoder 33 writes a specified value indicating the write back mode at the address assigned for write back control at the port 34. On the other hand, if the code signal C2 for setting the write-through mode is output to the decoder 33, a specified value indicating the write-through mode is written to the same address. In this sense, the output of the same address in the port 34 corresponds to the write back port 34a. The port 34 itself does not have to be provided exclusively for the write back, and can be used as a normal port having other functions.
[0021]
On the other hand, reset terminals 31a and 34b are formed in the CPU 31 and the port 34, respectively, and a reset signal is supplied in conjunction with a power switch or the like. When a reset signal is supplied to the reset terminal 34b of the port 34, the port output becomes a preset initial value, and in the case of the write back port 34a, it is in an off state indicating the write through mode.
The output of the write-back port 34a is input to the OR circuit 36 together with the output of the delay circuit 35 that receives the reset signal. The output of the OR circuit 36 is connected to the write-back terminal 32 in the CPU 31. Yes. The logical sum circuit 36 calculates a logical sum. If either one of the output of the delay circuit 35 and the output of the write-back port 34a is in the ON state by the connection described above, the CPU 31 converts the ON signal into a logical sum. Is supplied to the write back terminal 32.
[0022]
Therefore, when the reset signal for the CPU 31 is turned on, the write-back signal output from the OR circuit 36 after the delay time by the delay circuit 35 is also turned on. When the reset signal for the CPU 31 is turned off, the OR circuit 36 is output after the same delay time. The write back signal output from is also turned off. In the present embodiment, the write back signal needs to be on at the fall of the reset signal according to the specifications of the CPU 31, so the delay circuit 35 is interposed at the input of the OR circuit 36. However, if the reset is enabled by the rising edge of the reset signal, the reset signal may be supplied to the write-back terminal 32 as it is. In this case, when the signal condition of the write-back terminal 32 is checked for the first time after the reset is enabled, the ON signal can be supplied. Therefore, the reset signal is substantially used as it is as the write-back signal. Can do. In this sense, the signal line of the reset signal, the delay circuit, and the like constitute a write back signal control circuit. Of course, the configuration of the write back signal control circuit is not limited to this, and can be changed as appropriate.
[0023]
The write-back signal control circuit constitutes a write-back start-up control means, but it is necessary to change the circuit configuration if the start condition of the write-back mode changes. An entire circuit that starts the CPU in the write-back mode and shifts to the write-through mode immediately after the start-up is called a write-back start-up control means.
Next, the operation of the present embodiment having the above hardware configuration will be described together with the software processing.
[0024]
As shown in FIG. 3, when the reset signal is turned from OFF to ON, the write-back signal output from the OR circuit 36 is also turned on after the delay time of the delay circuit 35, and the CPU 31 is reset when the reset signal falls. To be launched. On the other hand, since the write back signal is on for the delay time of the delay circuit 35 at the time of this rise, the CPU 31 starts up in the write back mode. Then, after the delay time elapses, the write back signal is also turned off as the reset signal is turned off, and the CPU 31 shifts to the write through mode.
[0025]
If the write back signal is formed in this way, the CPU 31 rises in the write back mode, and shifts to the write through mode immediately after the rise when the reset signal is turned off and the write back signal is also turned off. Therefore, the processing starts in the write-through mode with the possibility of shifting to the write-back mode. The above signal situation and mode change state are shown in FIG.
When the CPU 31 starts up, as shown in FIG. 4, first, initialization such as memory check is executed (step S100), and then a DOS program is loaded from a hard disk or the like and started (step S110). During this time, as described above, since it operates in the write-through mode, cache inconsistency does not occur. Following the loading of the DOS program, the flash management software is loaded and activated in this embodiment (step S120).
[0026]
This flash management software mainly monitors the access to the external memory 40 by an external device or the like, and changes the contents of the internal cache memory so that inconsistency between the internal cache memory of the CPU 31 and the external memory 40 does not occur. More specifically, the process shown in FIG. 5 is executed.
In the case of the present embodiment, in order to monitor access to the external memory 40, a call for BIOS disk access is used. Considering that the cause of memory inconsistency is access to the external memory 40 by an external device, it may be appropriate to monitor the operation status of the DMA controller, but access to the DMA controller occurs very frequently. If the contents of the cache memory are flushed at each access, the processing speed is not substantially improved. For this reason, in the present embodiment, the situation in which processing may be abnormal due to cache inconsistency is narrowed down and flushed when there is a BIOS call for disk access.
[0027]
Note that when the sound circuit accesses the external memory 40 via DMA, there is a possibility that a cache inconsistency may occur, but it is known that the degree of influence on the processing is very small. The priority in this case can be changed depending on the system, and in this embodiment, the processing speed performance is prioritized. However, in the case of a music system, even if it is accessed from the sound circuit, it is flushed. do it. On the other hand, the CPU has a function of monitoring the access to a predetermined I / O. Therefore, the CPU may be appropriately changed according to the system, such as flushing by accessing the predetermined I / O. Further, in this embodiment, the inconsistency is eliminated by the flash, but if there is a command for direct write back, it may be executed.
[0028]
In order to realize the functions as described above, in this embodiment, the BIOS call vector table is rewritten to hook the BIOS call. Originally, if the BIOS call of INT1Bh is a disk access, as shown in FIG. 6, the start address (address 1) of the disk access routine in the BIOS call routine is recorded at the address corresponding to INT1Bh in the BIOS call vector table. Has been. This is rewritten to the start address (address 2) of the flash routine shown in the figure, and the flash routine is started before jumping to the disk access routine.
[0029]
This flow will be described with reference to the flowchart shown in FIG. First, the flash routine is loaded (step S200), and then the INT1Bh start address in the BIOS call vector table is rewritten to the flash routine start address (address 2) (step S210). In order to shift to the mode, the code signal C1 for turning on the write-back port 34a in the port 34 is output to the decoder 33 (step S220). By this port writing, the output of the write-back port 34a is turned on, and the output of the OR circuit 36 that receives the output is turned on. Since the output of the OR circuit 36 is input as a write back signal to the write back terminal 32 in the CPU 31, the write back signal is turned on, and the CPU 31 shifts to the write back mode (FIG. 3). This flash management software has this kind of content, and completes immediately after loading and starting up.
[0030]
After the flash management software is loaded and activated as described above, the write-back mode is entered. When the application is loaded and activated, it is executed in the write-back mode (step S130).
On the other hand, if the operation during the execution of the application is represented by a flowchart, it is as shown in FIG. After shifting to the write back mode as described above (step S300), it is monitored whether there is a request for disk access from the application (step S310). When a disk access request is made, the cache memory is flushed (step S320), a disk access routine is called (step S330), and data is referred to the external memory 40 via the external device interface 50. Etc. are performed. That is, the contents of the cache memory are first flushed by the flush routine, and the disk access is executed after the cache inconsistency with the external memory 40 is eliminated. Therefore, the write-back cache function can be operated normally.
[0031]
Note that the flash management software only needs to be able to substantially provide the above-described operation, and does not necessarily correspond to the above-described flowcharts. For example, the flash management software described above has a resident function as shown in FIG. 7, but in fact, it is terminated after securing a predetermined bioshook path even if it is activated. It is also possible to monitor access to the external memory in the state. On the other hand, for the sake of safety, in this embodiment, flushing is performed again after the end of the disk access call, but it is not always necessary to flush after execution. Of course, in parallel with monitoring for such a cache inconsistency, it may be periodically flushed by another program.
[0032]
As described above, in the CPU accelerator 30 according to the present embodiment, the reset signal is delayed by the delay circuit 35 and output to the write-back terminal. Therefore, when the CPU 31 is reset when the reset signal is turned on from off. When the write back signal is turned on and the system starts up in the write back mode, the reset signal is turned off, and immediately after the reset, the mode shifts to the write-through mode. In addition, after the cache management software shifts to the write-back mode, the processing speed can be increased by using the write-back cache function.
[Brief description of the drawings]
FIG. 1 is a schematic block diagram of a computer to which a CPU accelerator according to an embodiment of the present invention is applied.
FIG. 2 is a schematic block diagram of the CPU accelerator.
FIG. 3 is a timing chart showing a relationship between a reset signal, a write back signal, and a mode.
FIG. 4 is a flowchart showing activation processing of the CPU accelerator.
FIG. 5 is a flowchart showing loading and activation of flash management software.
FIG. 6 is an explanatory diagram for hooking a BIOS call for disk access;
FIG. 7 is a flowchart showing the operation of the flash management software.
[Explanation of symbols]
30 ... CPU accelerator 31 ... CPU
31a ... Reset terminal 32 ... Write-back terminal 33 ... Decoder 34 ... Port 34a ... Write-back port 34b ... Reset terminal 35 ... Delay circuit 36 ... OR circuit 40 ... External memory 50 ... Contents of internal device internal cache memory Flush

Claims (4)

When starting up in write-through mode, it is not possible to switch from write-through mode to write-back mode after startup. When starting up in write-back mode, after startup, between the two modes of write-back mode and write-through mode. A CPU accelerator having a CPU with a write-back cache function that can be transferred to each other and that starts in write-back mode when a write-back signal is given at reset,
A CPU accelerator comprising a write back start control means for starting up the CPU in a write back mode and shifting to the write through mode immediately after the start.   2. The CPU accelerator according to claim 1, wherein the write-back start-up control means turns on the write-back signal when a reset signal for the CPU is turned on and turns the write-back signal off when the reset signal is turned off. A CPU accelerator having a write-back signal control circuit for performing the operation. In the CPU accelerator according to claim 2,
The write back signal control circuit takes a logical sum of a write back port capable of outputting a port signal for the write back mode when a predetermined control signal from the CPU is input, and a reset signal and the port signal. A CPU accelerator comprising: a logical sum circuit that outputs a sum signal to a write-back terminal of the CPU. In the CPU accelerator according to any one of claims 1 to 3,
Monitors access to external memory and executes cache management software to write back so that inconsistency between the internal cache memory of the CPU and the external memory does not occur. A CPU accelerator that is shifted from a write back mode to a write back mode.

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