CN114035853B - MCU guide system and chip with SPI interface - Google Patents
MCU guide system and chip with SPI interface Download PDFInfo
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- CN114035853B CN114035853B CN202111359951.4A CN202111359951A CN114035853B CN 114035853 B CN114035853 B CN 114035853B CN 202111359951 A CN202111359951 A CN 202111359951A CN 114035853 B CN114035853 B CN 114035853B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
- G06F9/4411—Configuring for operating with peripheral devices; Loading of device drivers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
- G06F8/65—Updates
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention relates to an MCU guiding system and a chip with SPI interface, wherein the MCU guiding system comprises a state machine circuit and two alternative buffer areas; the state machine circuit is connected with a flash memory with an SPI interface through an SPI bus and is used for reading a guiding instruction section from the flash memory; when two guiding instruction sections read by the state machine circuit successively are continuous, the two guiding instruction sections read successively are sent to one of the alternative buffer areas, and then the two guiding instruction sections received successively in the same alternative buffer area are sequentially sent to the MCU; otherwise, one guide instruction segment read in advance is sent to one of the alternative buffer areas, then one guide instruction segment read in later is sent to the other alternative buffer area, in the working state, the one alternative buffer area sends the received one guide instruction segment to the MCU, and then the other alternative buffer area sends the received one guide instruction segment to the MCU.
Description
Technical Field
The invention relates to the technical field of MCU (micro control Unit) guide start, in particular to an MCU guide system with an SPI interface and a chip.
Background
In order to meet the requirements of high performance and low cost of communication equipment, the Norflash (NOR gate nonvolatile memory flash) is used as a current nonvolatile flash memory, and is more suitable for being used as a storage medium of a starting program compared with the other nonvolatile flash memory Nandflash (NAND gate nonvolatile memory flash) due to the characteristic that the Norflash (NOR gate nonvolatile memory flash) can be executed in a chip.
Norflash mainly adopts an SPI serial interface (SPI is serial peripheral interface, serial peripheral interface); the number of signal wires of the SPI interface of Norflash is small, and the peripheral design is simple, so that the Norflash SPI interface is very suitable for being used as a data storage device in intelligent mobile terminal products such as mobile phones, flat plates, small wheeled robots (such as pet robots, tumbler robots and indoor cleaning robots), but for intelligent mobile terminal products needing to upgrade functions according to the period, a microcontroller unit (Micro Control Unit, MCU) in the existing intelligent mobile terminal products cannot support the use of Norflash as a carrier of a bootstrap program, namely, the bootstrap program data inside the Norflash cannot be used for guiding the microcontroller unit to start the task of executing the function upgrade.
Disclosure of Invention
Aiming at the problems, the invention aims to provide an MCU guiding system and a chip with SPI interface, which realize that a default guiding command is built in a flash memory to support an MCU, thereby meeting the requirements of guiding the MCU to start, guiding and configuring the MCU and guiding the MCU to upgrade. The specific technical scheme is as follows:
the MCU guide system is provided with an SPI interface and comprises a state machine circuit and two alternative cache areas; the state machine circuit is connected with a flash memory with an SPI interface through an SPI bus and is used for reading a guide instruction section from the flash memory, wherein the state machine circuit has the following working state jumps: when two guiding instruction sections read by a state machine circuit successively are continuous, triggering the state machine circuit to enter a continuous access state, wherein the state machine circuit is used for sending the two guiding instruction sections read successively into one of the alternative cache areas in the continuous access state, and then sequentially sending the two guiding instruction sections received successively in the one of the alternative cache areas to the MCU so as to guide the MCU to start; when two guiding instruction sections read by the state machine circuit in sequence are not continuous, triggering the state machine circuit to enter a branch access state, wherein the state machine circuit is used for sending one guiding instruction section read before into one of the alternative cache areas in the branch access state, and sending one guiding instruction section read after into the other alternative cache area; the state machine circuit is further used for triggering one of the alternative buffer areas to send the received one guide instruction segment to the MCU at first and triggering the other alternative buffer area to send the received one guide instruction segment to the MCU under the branch access state so as to avoid searching two discontinuous guide instruction segments one address unit by one address unit in the same alternative buffer area.
Further, the two alternative cache areas are a first alternative cache area and a second alternative cache area respectively; if the first guiding instruction section and the second guiding instruction section which are read successively are not continuous, and the second guiding instruction section and the third guiding instruction section which are read successively are not continuous, the state machine is used for sending the first guiding instruction section into a first alternate cache area, sending the second guiding instruction section into a second alternate cache area and sending the third guiding instruction section into the first alternate cache area under the branch access state; the state machine circuit is further used for triggering the first alternate buffer area to send the first guiding instruction section to the MCU, triggering the second alternate buffer area to send the second guiding instruction section to the MCU, and triggering the first alternate buffer area to send the third guiding instruction section to the MCU under the branch access state, so that the situation that two discontinuous guiding instruction sections are searched in the same alternate buffer area one by one address unit in the same time sequence period is avoided.
Further, the two alternative cache areas are a first alternative cache area and a second alternative cache area respectively; if the first guide instruction section and the second guide instruction section read by the state machine circuit in sequence are not continuous, the state machine circuit jumps to the branch access state, and the state machine circuit sends the first guide instruction section to a first alternate buffer area and sends the second guide instruction section to a second alternate buffer area in the branch access state; then, if the second guiding instruction section and the third guiding instruction section read by the state machine circuit in sequence are continuous, the state machine circuit jumps from the branch access state to the continuous access state, and the state machine circuit sends the third guiding instruction section to a second alternate buffer area in the continuous access state; the state machine circuit is further used for triggering the first alternate buffer area to send the first guide instruction segment to the MCU, and triggering the second alternate buffer area to sequentially send the two guide instruction segments received successively to the MCU, so that the situation that the two discontinuous guide instruction segments are searched for one address unit by one address unit in the same alternate buffer area in the same time sequence period is avoided.
Further, when the guiding instruction sections read twice continuously by the state machine circuit are continuous, the state machine circuit enters the continuous access state, and then controls the guiding instruction sections read twice continuously to be stored in the same alternate buffer area until the guiding instruction sections read twice continuously by the state machine circuit are not continuous, the state machine circuit jumps to the branch access state, and controls the guiding instruction sections read once last to be stored in the other alternate buffer area.
Further, in the process of sending one guide instruction segment in one alternative cache region to the MCU, sending the other guide instruction segment into the alternative cache region or the other alternative cache region synchronously; the two alternative cache areas are respectively positioned in different storage spaces in the MCU guide system; the processing process comprises the steps of sending the two successively read guide instruction segments to corresponding alternative cache areas and sending the two successively read guide instruction segments to an MCU from the corresponding alternative cache areas.
Further, an SPI interface is arranged in the state machine circuit; each functional pin of the SPI interface of the flash memory is respectively connected with the corresponding functional pin of the SPI interface of the state machine circuit through an SPI bus; the SPI interface of the flash memory is configured into a 4-wire read mode, so that the SPI interface of the state machine circuit is also adaptively adjusted into the 4-wire read mode; the write protection pin and the holding pin of the SPI interface of the state machine circuit are configured as data input ends so as to form 4 data lines with parallel data receiving and transmitting functions in one SPI interface, and one guide instruction section is read in one clock period; the state machine circuit is used for carrying out parallel-serial conversion on binary numbers corresponding to the guide instruction segments received in parallel by the 4 data input ends in the 4-line reading mode of the SPI interface, and then transmitting the binary numbers to a corresponding alternate buffer area; wherein, the alternate buffer is to use serial interface to send and receive data.
Further, the two guiding instruction sections read by the state machine circuit successively are continuous, which means that addresses corresponding to the two guiding instruction sections read by the state machine circuit successively are continuous; the two guiding instruction sections read by the state machine circuit successively are not continuous, which means that the addresses corresponding to the two guiding instruction sections read by the state machine circuit successively are not continuous, and further, the fact that one guiding instruction section read later is jumped relative to one guiding instruction section read earlier is determined; the boot instruction section is boot program data which is stored in the flash memory in advance, and the boot program data configures an upgrade request port of the MCU to enter a boot mode.
Further, in the two alternate buffer areas, when any one of the alternate buffer areas has no remaining buffer space, continuing to read the boot instruction segment from the flash memory is stopped, and the flash memory is configured in a write-protected state.
Further, the speed at which the state machine circuit reads the boot instruction segment through the SPI bus is greater than the speed at which the MCU extracts the boot instruction segment from the alternating cache region.
Further, after the MCU is guided to start, the upgrade program in the MCU is further used for taking over the SPI interface of the state machine circuit, so that the MCU performs read-write operation on the flash memory through the SPI interface and the SPI bus connected with the SPI interface, and data conversion between different bus transmission is reduced.
A chip is internally provided with the MCU guide system with the SPI interface.
Compared with the prior art, the method has the beneficial effects that two alternative cache areas are designed, and a working state scheduling mechanism existing in a state machine circuit is combined to deal with the continuous condition between two successively read guide instruction sections, so that most of MCUs can support the start by SPI Norflash guide, thereby realizing the upgrade of the MCU, specifically realizing the use of the two alternative cache areas to respectively cache the two successively read discontinuous guide instruction sections, and the use of one alternative cache area to respectively cache the two successively read guide instruction sections, thereby reducing the probability of abnormal program operation caused by frequent code jump; furthermore, the upgrade period of small wheeled robots (such as pet robots and tumbler robots) using the part of MCU which does not support SPI Norflash guidance is shortened.
Drawings
Fig. 1 is a schematic connection diagram of an MCU boot system with an SPI interface, a flash memory (SPI flash) with an SPI interface, and an MCU according to an embodiment of the present invention.
Detailed Description
The following describes the embodiments of the present invention further with reference to the drawings. Each unit module in the following embodiments is a logic circuit, and one logic circuit may be one physical unit, or may be a state machine formed by combining a plurality of logic devices according to a certain read-write time sequence and signal logic change, or may be a part of one physical unit, or may be implemented by combining a plurality of physical units. In addition, in order to highlight the innovative part of the present invention, elements that are not so close to solving the technical problem presented by the present invention are not introduced in the present embodiment, but it does not indicate that other elements are not present in the present embodiment.
In the prior art, the MCU cannot directly access the peripheral flash memory (flash memory), especially when developing or upgrading functions for some small portable intelligent devices controlled by the MCU, the compatibility of the data communication interface is limited, and it is not possible to better use the nor flash memory with serial peripheral interface (SPI interface) and the nand flash memory with serial peripheral interface (SPI interface) as a storage medium for storing the boot program data, and the necessary software driver is also lacking in the MCU of these small intelligent devices to support the transfer of the related boot program data.
The embodiment of the invention discloses an MCU guiding system with SPI interface, referring to fig. 1, the MCU guiding system comprises a state machine circuit and two alternative buffer areas; the two alternative buffer areas are respectively a first alternative buffer area and a second alternative buffer area in fig. 1, and are preferably two buffer spaces with mutually independent pin resources, and the read-write operations involved in the two buffer spaces are not interfered with each other. The state machine circuit is connected with a flash memory with an SPI interface through an SPI bus and is used for reading a guide instruction section from the flash memory; the flash memory with the SPI interface is the flash memory with the SPI interface, and the SPI interface of the flash memory comprises 4 pins supporting data input and output, a clock pin SCK and a chip selection pin/CS, and the SPI interface is used for providing 4 paths of data signals, 1 path of clock signals and 1 path of chip selection signals for the state machine circuit through the SPI bus, so that the state machine circuit reads code data with a program guiding function from the flash memory to guide and start the MCU or a related processor. It should be noted that, the 4 pins supporting data input and output shown in fig. 1 include IO0, IO1, IO2, and IO3, and provide 4 data signal lines, and the more the number of data signal lines in the same clock cycle, the higher the transmission rate of the SPI interface.
In this embodiment, the MCU and the state machine circuit may be designed with parallel interfaces, and the MCU obtains a boot startup program from a peripheral memory, and the MCU is specially configured with a valid port execution boot startup mode for an upgrade request; the state machine circuit can be a digital integrated circuit which uses a hardware programming language to construct a logic function by itself according to the scheduling requirement of working states, and generates a time sequence function under each working state, so that the compatibility of various MCUs to a standard SPI protocol can be overcome.
The guiding instruction section can be guiding program data occupying 4 bits or bit width of multiple of 4 bits, and is used for guiding the MCU to start so as to be convenient for initializing relevant running environments (including MCU, SPI interface and flash memory) configuration parameters (including determining starting address and judging verification information), upgrading functions of the MCU, erasing data of the flash memory and upgrading a storage block in the flash memory, so that the MCU guiding system, the MCU and the flash memory form an integral system, program starting guiding under the SPI interface and subsequent program function upgrading are supported, and intelligent mobile terminal products such as mobile phones, flat-panel, small-sized wheeled robots (such as pet robots, tumbler robots and indoor cleaning robots) are further served, and the requirement of using Norflash as a carrier of guiding programs is met.
In this embodiment, the state machine has the following operating state jumps:
when two guiding instruction sections read by the state machine circuit successively are continuous, the state machine circuit is triggered to enter a continuous access state. The state machine circuit is operable to enter the sequential access state from an initial state or other operating state, including an idle state. When the state machine circuit detects that the two guiding instruction sections read successively are continuous, a detection result signal in the state machine circuit triggers the state machine circuit to enter a continuous access state.
In this embodiment, the data input end of the state machine circuit receives the guiding command section through the SPI bus according to the timing sequence specified by the SPI interface, so that every other clock cycle, the state machine circuit reads one guiding command section from the flash memory, wherein the bit width of the data read at a time is greater than 1, and the SPI bus is generally transmitted in bytes. And the flash memory transmits a guide instruction segment to the state machine circuit, and the state machine circuit sets the chip selection pin/SS 1 of the flash memory and/or the chip selection pin/CS of the flash memory to be low level to play a triggering role.
It should be noted that, before the boot instruction segment is read, the state machine circuit receives a request instruction triggered by an external power-on reset signal transmitted from the MCU, and the request instruction is parsed by the state machine circuit into address signals, so that the state machine circuit reads the boot instruction segments corresponding to the address signals from the flash memory, and the address signals are used as address information corresponding to the instruction segments to be received when the MCU is started, specifically, the address information corresponding to the address of the boot instruction segment in the flash memory, and sequentially reads the boot instruction segments from the flash memory according to the address information, so that two consecutive and non-consecutive situations exist in two boot instruction segments read sequentially, and the two boot instruction segments read sequentially are also indicated to be two adjacent boot instruction segments. The boot instruction section may be boot program data stored in the flash memory in advance before the MCU is started each time, where the boot program data configures an upgrade request port of the MCU to enter a boot mode.
Specifically, when the effective addresses corresponding to the guiding instruction sections read by the state machine circuit twice continuously are continuous, the state machine circuit indicates that two guiding instruction sections read by the state machine circuit sequentially are continuous, the storage sequence of the two guiding instruction sections in the flash memory is continuous, the state machine circuit can continuously access the guiding instruction sections in the flash memory from a starting address and store the guiding instruction sections in a buffer area of a stack structure according to the sequence of the guiding instruction sections, then the state machine circuit is used for sending the two guiding instruction sections read sequentially into one of the alternative buffer areas in a continuous access state, namely, the state machine circuit sequentially transmits the two guiding instruction sections read continuously to the same alternative buffer area, the alternative buffer area receives the two guiding instruction sections in the form of the stack structure, the access continuity between the guiding instruction sections is ensured, the two guiding instruction sections received in the alternative buffer area can be sequentially started to be sent to the MCU after receiving a guiding request instruction sent by the MCU, the guiding MCU is updated, the speed of the MCU can be reduced, and the data of the MCU is read from the starting address of the MCU is reduced, and the data of the MCU is read from the MCU is not influenced, the speed is reduced, and the speed of the MCU is changed, and the data of the MCU is read from the MCU is not read, and the MCU is different, the type of the type is read, and the data is read from the MCU is read from the continuous speed is read. Notably, the state machine circuit reads only one boot instruction segment per clock cycle.
In some embodiments, after the MCU boot system, the MCU and the flash memory are powered on, the state machine circuit starts to read the boot instruction segment from a preset start address in the flash memory, where it may be implemented that the MCU boot system is used as a printed circuit board, a serial port key is assembled in the printed circuit board, and after the serial port key is pressed, the state machine circuit generates a level change to send the level change to the MCU and the flash memory respectively, especially, a boot start indication signal generated at an upgrade request port of the MCU is used for some mobile terminal devices, so that status information of boot device self start and subsequent function upgrade can be obviously reflected.
When the state machine circuit detects that the two guiding instruction sections read successively are not continuous, a detection result signal in the state machine circuit triggers the state machine circuit to enter the branch access state; at this time, the two guiding instruction sections read by the state machine circuit successively are not continuous, the storage sequence of the effective addresses corresponding to the two guiding instruction sections in the memory space is also not continuous, the effective addresses corresponding to the two guiding instruction sections have an interval of one address section in the flash memory, then the state machine circuit is used for sending one guiding instruction section read before into one of the alternative buffer areas in a branch access state, and then sending one guiding instruction section read after into the other alternative buffer area, so that when the guiding instruction section read by the state machine circuit is discontinuous for every two consecutive guiding instruction sections, the two guiding instruction sections are respectively sent to two different alternative buffer areas, then the state machine circuit is used for sending one guiding instruction section received to the MCU in a branch access state, and then triggering the other alternative buffer area to send the received guiding instruction section to the MCU in a branch access state, therefore, the two guiding instruction sections read by the state machine circuit are not read by the two alternative buffer areas, and the two guiding instruction sections are not read successively, and the two guiding instruction sections are not read successively in the alternative buffer areas are read successively; meanwhile, the state machine circuit can enable the MCU to read one guide instruction section from the respective initial address in two alternative cache regions in sequence, so that two guide instruction sections with discontinuous address information are read alternately between the two alternative cache regions, compatibility of the MCU to guide instruction codes of the flash memory is enhanced, namely, the MCU is enabled to adapt to the guide instruction with jump (namely, the two discontinuous guide instruction sections transmitted by the flash memory), and therefore stability of program guide starting of the MCU guide system to different types of MCUs under the same SPI interface is improved.
Compared with the prior art, the method has the beneficial technical effects that two alternative cache areas can be designed in the starting stage of the MCU, and the continuous condition between two successively read guide instruction areas can be dealt with by combining the working state scheduling mechanism existing in the state machine circuit, so that most of the MCU can support the starting and subsequent upgrading by SPI Norflash, two discontinuous guide instruction areas successively read by using the two alternative cache areas are cached respectively, and two continuous guide instruction areas successively read by using one alternative cache area are cached respectively, and the probability of abnormal program operation caused by frequent code jump is reduced; furthermore, the upgrade period of small wheeled robots (such as pet robots and tumbler robots) using the part of MCU which does not support SPI Norflash guidance is shortened.
As an embodiment, the two alternative cache areas are a first alternative cache area and a second alternative cache area respectively, which may be respectively located in different storage spaces in the MCU boot system; the state machine circuit reads the first guide instruction section and the second guide instruction section successively, wherein the first guide instruction section and the second guide instruction section are not continuous, the second guide instruction section and the third guide instruction section which are read successively are not continuous, the state machine circuit firstly sends the first guide instruction section into a first alternate cache area, then sends the second guide instruction section into a second alternate cache area and then sends the third guide instruction section into a first alternate cache area, wherein storage addresses corresponding to the first guide instruction section and the second guide instruction section in the flash memory are discontinuous, storage addresses corresponding to the second guide instruction section and the third guide instruction section in the flash memory are also discontinuous, and the second guide instruction section and the third guide instruction section correspondingly enter and are maintained in the branch access state; it can be understood that if the state machine circuit reads three or more guiding instruction segments, the state machine circuit maintains and controls the guiding instruction segments read twice consecutively to be cached between the first alternative cache region and the second alternative cache region alternately. The state machine circuit is further used for triggering the first alternate buffer area to send a first guide instruction segment to the MCU after receiving a guide request instruction sent by the MCU in the branch access state, triggering the second alternate buffer area to send a second guide instruction segment to the MCU, and triggering the first alternate buffer area to send a third guide instruction segment to the MCU; that is, in the branch access state, the state machine controls the first and second alternate buffers to alternately transmit one of the boot instruction segments stored in each of the first and second alternate buffers to the MCU, and also allows the same MCU to alternately receive the mutually discontinuous boot instruction segments received from the two alternate buffers, so as to avoid searching for the discontinuous two boot instruction segments address unit by address unit in the same alternate buffer in the same timing cycle.
As another embodiment, the first guiding instruction section and the second guiding instruction section sequentially read from the flash memory by the state machine circuit are not continuous, and the second guiding instruction section and the third guiding instruction section sequentially read from the flash memory are continuous, which can be determined that, in guiding instruction sections sequentially read three times from the flash memory by the state machine circuit, guiding instruction sections continuously read twice are not continuous, and the state machine circuit is correspondingly triggered to jump to the branch access state; then, if the guiding instruction segments read for two other continuous times are continuous, the state machine circuit is correspondingly triggered to jump to the continuous access state. Specifically, when the state machine circuit detects that the first guide instruction segment and the second guide instruction segment which are read successively (equivalent to two continuous reads) are not continuous, the state machine circuit jumps to the branch access state, and sends the first guide instruction segment to a first alternate cache area and sends the second guide instruction segment to a second alternate cache area in the branch access state, so that two guide instruction segments which are discontinuous to each other are respectively stored in the first alternate cache area and the second alternate cache area; then, if the second and third guide instruction sections read by the state machine circuit sequentially (equivalent to two consecutive reads) are consecutive, the state machine circuit jumps from the branch access state to the continuous access state, and the state machine circuit stores the third guide instruction section in the second alternate buffer area in the continuous access state, so as to realize that two guide instruction sections which are consecutive to each other are stored in the same alternate buffer area, especially, the guide instruction section which is read last time (i.e. the second guide instruction section) is stored in the same alternate buffer area (the second alternate buffer area); it can be understood that when the two guiding instruction segments read by the state machine circuit continuously are not continuous, the state machine circuit controls the guiding instruction segments read by the state machine circuit continuously to be buffered between the first alternate buffer area and the second buffer area alternately until the guiding instruction segments read by the state machine circuit continuously are continuous; correspondingly, the state machine circuit is further used for triggering the first alternate buffer area to send the first guide instruction segment to the MCU after receiving the guide request instruction sent by the MCU, and triggering the second alternate buffer area to sequentially send the two guide instruction segments received successively to the MCU, so that discontinuous two guide instruction segments are prevented from being searched one address unit by one address unit in the same alternate buffer area in the same time sequence period, and only continuous two guide instruction segments can be ensured to be searched in the same alternate buffer area in the same time sequence period.
As another embodiment, the two alternative cache areas are a first alternative cache area and a second alternative cache area respectively, which may be respectively located in different storage spaces in the MCU boot system; if the first guide instruction section and the second guide instruction section read by the state machine circuit in sequence are continuous, the state machine circuit jumps to the continuous access state, and the state machine circuit sequentially sends the first guide instruction section and the second guide instruction section into a first alternate buffer area in the continuous access state; the state machine circuit reads a first guide instruction section from the flash memory for the first time, reads a second guide instruction section from the flash memory for the second time, and recognizes two adjacent guide instruction sections by the first guide instruction section and the second guide instruction section which are continuous with corresponding storage addresses in the flash memory. And then, if the second guide instruction section and the third guide instruction section read by the state machine circuit in sequence are not continuous, the state machine circuit jumps from the continuous access state to the branch access state, and the state machine circuit sends the third guide instruction section into a second alternate cache area in the branch access state, wherein the state machine circuit reads the second guide instruction section from the flash memory for the second time, reads the third guide instruction section from the flash memory for the third time, and identifies two non-adjacent guide instruction sections by the fact that the corresponding storage addresses of the second guide instruction section and the third guide instruction section in the flash memory are discontinuous. Correspondingly, the state machine circuit is further used for triggering the first alternate buffer area to sequentially send the first guide instruction section and the second guide instruction section to the MCU after receiving the guide request instruction sent by the MCU, and triggering the second alternate buffer area to send the third guide instruction section to the MCU, so that discontinuous two guide instruction sections are prevented from being searched for one address unit by one address unit in the same alternate buffer area in the same time sequence period, and only continuous two guide instruction sections can be ensured to be searched for in the same alternate buffer area in the same time sequence period. Notably, the state machine circuit receives only one boot instruction segment at a time from the flash memory output. Therefore, if the state machine circuit reads three or more than three guiding instruction segments, when the state machine circuit starts to continuously read two guiding instruction segments, the state machine circuit firstly enters the continuous access state, then controls the guiding instruction segments read continuously twice to store in the same alternate buffer area, until the guiding instruction segments read continuously twice by the state machine circuit are not continuous, the state machine circuit jumps to the branch access state, controls the guiding instruction segments read last time to store in the other alternate buffer area, and repeatedly detects whether the two guiding instruction segments read continuously twice are continuous, so as to schedule the next working state.
Based on the foregoing embodiment, the state machine circuit, whether in the continuous access state or the branch access state, sends one guide instruction segment in one alternate buffer into the MCU or sends another guide instruction segment into another alternate buffer simultaneously during sending the other guide instruction segment in the alternate buffer to the MCU; in some embodiments, during the process of sending the first guiding instruction segment in the first alternate buffer to the MCU, the third guiding instruction segment is synchronously sent in the first alternate buffer under the continuous access state, wherein, for the state machine circuit, the reading time of the second guiding instruction segment is between the reading time of the first guiding instruction segment and the reading time of the third guiding instruction segment, the first guiding instruction segment is not continuous with the third guiding instruction segment, the existing second guiding instruction segment is continuous with the first guiding instruction segment, and the existing third guiding instruction segment is continuous with the second guiding instruction segment. In some embodiments, during the process of sending the first guiding instruction segment in the first alternative cache region to the MCU, the third guiding instruction segment is synchronously sent into the first alternative cache region in the branch access state, wherein, for the state machine circuit, the reading time of the second guiding instruction segment is between the reading time of the first guiding instruction segment and the reading time of the third guiding instruction segment, the first guiding instruction segment is not continuous with the third guiding instruction segment, the second guiding instruction segment is discontinuous with the first guiding instruction segment, and the third guiding instruction segment is discontinuous with the second guiding instruction segment. It is noted that the two alternate buffers are located in different memory spaces within the MCU boot system, respectively. The method avoids the situation that two discontinuous guiding instruction sections are searched in the same alternate buffer area one by one address unit in the same time sequence period, can reduce the influence of the phenomenon that branch codes and instructions jump to the guiding process of the MCU, particularly the influence of continuity of transmission data, improves the adaptability of the MCU to the guiding instruction sections of the flash memory, shortens the guiding starting period of the MCU compared with the prior art, and further shortens the function upgrading period of a small wheeled robot (such as a pet robot and a tumbler robot) using the MCU which does not support the guiding of the flash memory.
It should be noted that, the time consumed by the state machine circuit in the processing procedure of the two guiding instruction segments read successively is configured as a time sequence period, and the corresponding processing procedure includes sending the two guiding instruction segments read successively to the corresponding alternative buffer areas, and sending the two guiding instruction segments read successively to the MCU from the corresponding alternative buffer areas. Therefore, the sum of the time taken for the two successively read guide instruction segments to be sent to the corresponding alternate buffer areas and the time taken for the two successively read guide instruction segments to be sent from the corresponding alternate buffer areas to the MCU is equal to one timing cycle.
In the above embodiment, an SPI interface is provided inside the state machine circuit, where the SPI interface is provided with four data input/output pins, i.e. IO0, IO1, IO2, and IO3, so as to provide four data signal lines to the outside; the SPI interface is also provided with a clock pin SCLK and a chip selection pin/SS 1; each functional pin of the SPI interface of the flash memory is connected with a corresponding functional pin of the SPI interface of the state machine circuit through an SPI bus, as shown in fig. 1, IO0, IO1, IO2, and IO3 of the SPI interface of the flash memory are connected with pins of the same name of the SPI interface of the state machine circuit, a clock pin SCK of the SPI interface of the flash memory is connected with a clock pin SCLK of the SPI interface of the state machine circuit, and a chip select pin/CS of the SPI interface of the flash memory is connected with a chip select pin/SS 1 of the SPI interface of the state machine circuit.
Specifically, the SPI interface of the flash memory is configured in a 4-wire read mode, so that the SPI interface of the state machine circuit is also adaptively adjusted to the 4-wire read mode, and the SPI interface of the flash memory may be connected to the SPI interface of the state machine circuit through an SPI bus; under the triggering action of an external triggering signal or the configuration action of fixed parameters built in the FLASH memory, a 4-wire mode of the FLASH memory is started, at this time, the 4-wire mode configured by the FLASH memory is opposite to a standard single-wire SPI protocol of the FLASH memory, the state machine circuit configures a write protection pin in 4-wire transmission of the FLASH memory as a data input end IO2, a holding pin in 4-wire transmission is configured as a data input end IO3, the write protection pin and the holding pin of an SPI interface of the state machine circuit are also adaptively configured as data input ends so as to form 4 data wires with parallel transceiving functions in one SPI interface, parallel transmission of 4 bits in each clock period SCLK (clock signal transmitted by the clock pin SCLK) can be achieved, a default set of matching parameters of the 4-wire mode is built in the FLASH memory, after the MCU guide system is combined with the FLASH memory, the FLASH memory supports the MCU model difference of different types of MCU models, and the MCU model difference of the FLASH memory is overcome.
The state machine circuit is configured to perform parallel-to-serial conversion on binary numbers corresponding to the guide instruction segments received in parallel by the 4 data input ends in the 4-wire read mode of the SPI interface, and then transmit the binary numbers to a corresponding one of the alternate buffer areas, where the 4 data input ends are connected to the SPI bus, and in this embodiment, the SPI interface in the 4-wire mode is set to be a parallel interface supporting half duplex, and is configured to transmit control signals, address signals, and data signals included in the guide instruction segments in parallel according to a set timing sequence, and accordingly, the SPI bus is a parallel bus in this embodiment; in one embodiment, when the state machine circuit is to send the boot instruction segment to the alternate cache region, since the state machine circuit uses a parallel bus to read boot data (the boot instruction segment) of the flash memory and the alternate cache region is to send and receive data using a serial interface, the parallel-to-serial conversion is: the state machine circuit converts the guiding instruction segments which are sent out in parallel through the SPI interface and transmitted in parallel through the SPI bus into writing data which are transmitted through the serial bus of the alternative buffer area and received through the serial interface. The state machine circuit reads the guide instruction section from the flash memory in parallel by adopting an SPI interface under a 4-wire mode, and the serial interface adopted by the state machine circuit for writing the guide instruction section into the alternate buffer area is compared with the SPI interface under the 4-wire mode, so that the number of signal wires is reduced, the number of pins of a buffer chip is small, the operation burden of the adopted interface for guiding MCU to start is reduced, and the use area of a PCB circuit board is saved.
In the foregoing embodiment, the two guiding instruction segments read by the state machine circuit successively are consecutive, which means that addresses corresponding to the two guiding instruction segments read by the state machine circuit successively are consecutive, that is, a storage address corresponding to one guiding instruction segment read before in the flash memory is adjacent to a storage address corresponding to one guiding instruction segment read after in the flash memory; wherein the state machine circuit reads one boot instruction segment from the flash memory at a time.
On the other hand, in the implementation, in the flash memory, some pieces of bootstrap data corresponding to the jump branches with more occurrence frequency may be stored. For example, for the verification required for starting the MCU, if a loop operation needs to be performed or the same function is called repeatedly, a jump branch corresponding to the function operation is stored in the flash memory in advance. Specifically, the two guiding instruction sections read by the state machine circuit successively are not continuous, which means that addresses corresponding to the two guiding instruction sections read by the state machine circuit successively are not continuous, namely, a storage address corresponding to one guiding instruction section read before in the flash memory is not adjacent to a storage address corresponding to one guiding instruction section read after in the flash memory; the state machine circuit reads one guiding instruction section from the flash memory each time, and further determines that one guiding instruction section read later jumps relative to one guiding instruction section read earlier, namely one guiding instruction section read later generates a conditional branch relative to one guiding instruction section read earlier, a dynamic instruction is formed as a whole, at the moment, the compatibility (time sequence compatibility) of the MCU to the flash memory and the SPI interface becomes unstable, and therefore, the state machine circuit controls the two discontinuous guiding instruction sections read successively to be buffered between a first alternate buffer area and a second buffer area alternately until the guiding instruction sections read twice continuously by the state machine circuit at present become continuous.
It should be noted that, the boot instruction segment is boot program data stored in the flash memory in advance, specifically, boot program data stored before each time of starting the MCU, where the boot program data configures an upgrade request port of the MCU to enter a boot mode, so as to facilitate normal read-write operation on the flash memory, and the MCU does not need to directly call a corresponding boot instruction segment from the flash memory, but supports normal running of a boot start process of the MCU through the MCU boot system; particularly, after the MCU is booted, the upgrade program in the MCU is also used for taking over the SPI interface of the state machine circuit, the SPI interface of the state machine circuit is used as the SPI interface of the MCU boot system, the control authority of the SPI interface of the state machine circuit is handed over to the MCU, the MCU can directly perform read-write operation on the flash memory through the SPI bus, and the read-out data needs to be cached through the alternative cache area in the specific implementation process; therefore, after the MCU is started, the MCU or the MCU starts the guide system to access the data in the flash memory, and the whole process is transmitted through the SPI bus, wherein the SPI interface of the state machine circuit and the SPI bus are used for reducing data conversion between different bus transmissions, so that the conversion process from the MCU to the parallel IO buses of the state machine circuit or the alternative cache area and the SPI bus can be saved, the guide starting period of the MCU in the prior art is shortened, and the function upgrading period of a small wheeled robot (such as a pet robot and a tumbler robot) using the MCU which does not support the guide of the flash memory with the SPI interface is shortened.
Preferably, in the two alternate buffers, when any one of the alternate buffers has no remaining buffer space, the reading of the boot instruction segment from the flash memory is stopped, and the flash memory is configured in a write-protected state. Therefore, the state machine circuit decides whether to continue reading the boot instruction segment from the flash memory or to perform a suspend operation on the flash memory according to the filling condition of each alternate buffer. Notably, if the boot instruction segment is continuously read from the flash memory, the write protection state of the relevant pin of the flash memory is released, so that the flash memory is convenient to receive the request instruction parameters from the state machine circuit, the flash memory maintains to release the write protection state after the MCU is guided to be started, the upgrade program in the MCU is convenient to take over the SPI interface set by the MCU, and the SPI interface of the MCU can perform read-write operation on the flash memory through an SPI bus; if the flash memory is suspended, setting relevant pins of the flash memory to be in a write protection state, and suspending the alternative buffer area by the state machine, so as to avoid damaging the flash memory or the alternative buffer area under unexpected conditions such as power failure and the like, which may occur, and failing to start the MCU guide system, or even failing to correctly guide and upgrade the MCU.
Preferably, the speed at which the state machine circuit reads the boot instruction segment through the SPI bus is greater than the speed at which the MCU extracts the boot instruction segment from the alternate cache region, such that the speed at which the MCU extracts the boot instruction segment from the alternate cache region of the state machine circuit is determined by the size of the program data in the boot instruction segment. In one embodiment, the state machine circuit continuously reads the guiding instruction segments from the flash memory and continuously provides the guiding instruction segments of the current cache to the MCU through two or one of the alternative cache regions, and since the speed of the state machine circuit reading the guiding instruction segments from the flash memory through the SPI bus is greater than the speed of the MCU extracting the guiding instruction segments from the alternative cache regions, it is guaranteed that at least one of the alternative cache regions is not completely read by the MCU, so that the state machine circuit does not have the task of recognizing other access operations of the MCU, it is guaranteed that the MCU guiding system with the SPI interface continuously guides the motion of the MCU, and it is notable that the MCU does not know the specific source of the guiding instruction segments read by the MCU when the MCU guiding the MCU continuously starts, i.e. the MCU does not recognize that the guiding instruction segments are actually stored in the flash memory; the MCU guiding system does not identify the model of the MCU before guiding the MCU to start, and only transmits the guiding instruction section to the MCU to be started.
Based on the foregoing embodiment, the present invention further discloses a chip, in which the MCU guidance system with the SPI interface is disposed inside the chip, and the driving circuit for providing the MCU with the guidance function is provided with logic hardware with higher integration, so that the chip is convenient to be assembled in small wheeled mobile robots or other types of handheld mobile intelligent terminals that need to be guided for upgrading functions, where the guidance upgrading of the small wheeled mobile robots or other types of handheld mobile intelligent terminals depends on the starting of the MCU inside the chip, and the starting of the MCU depends on the guidance of the MCU guidance system; specifically, in the chip, the state machine circuit, the two alternate buffers and the associated configuration registers are all digital circuit modules compiled by a designer using the hardware description language Verilog HDL, or are digital circuit modules compiled or interpreted by a designer on software having circuit rendering or compiling functions. In addition, the MCU, the functional units and the flash memory in the embodiments of the invention can be integrated in a main control circuit board to be assembled into a main control board occupying a small space volume inside an electronic equipment terminal or a mobile robot. The method realizes the support of the MCU by utilizing a default set of guide commands in the flash memory, and meets the requirements of starting the MCU, configuring the MCU and upgrading the MCU. Meanwhile, the probability of abnormal program operation caused by frequent code jump is reduced; furthermore, the upgrade period of small wheeled robots (such as pet robots and tumbler robots) using the part of MCU which does not support SPI Norflash guidance is shortened.
In the embodiments provided in the present application, it should be understood that the disclosed system and chip may be implemented in other manners. For example, the system embodiments described above are merely illustrative, e.g., the division of the elements is merely a logical functional division, and there may be additional divisions when actually implemented, e.g., multiple elements or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form. The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the embodiment.
Claims (9)
1. The MCU guide system with the SPI interface is characterized by comprising a state machine circuit and two alternative cache areas;
The state machine circuit is connected with a flash memory with an SPI interface through an SPI bus and is used for reading a guide instruction section from the flash memory;
when two guiding instruction sections read by a state machine circuit successively are continuous, triggering the state machine circuit to enter a continuous access state, wherein the state machine circuit is used for sending the two guiding instruction sections read successively into one of the alternative cache areas in the continuous access state, and then sequentially sending the two guiding instruction sections received successively in the one of the alternative cache areas to the MCU;
when two guiding instruction sections read by the state machine circuit in sequence are not continuous, triggering the state machine circuit to enter a branch access state, wherein the state machine circuit is used for sending one guiding instruction section read before into one of the alternative cache areas in the branch access state, and sending one guiding instruction section read after into the other alternative cache area;
the state machine circuit is further used for triggering one of the alternative cache areas to send the received one guide instruction segment to the MCU at first and triggering the other alternative cache area to send the received one guide instruction segment to the MCU under the branch access state so as to avoid searching two discontinuous guide instruction segments one by one address unit in the same alternative cache area;
The two alternative cache areas are a first alternative cache area and a second alternative cache area respectively;
if the first guide instruction section and the second guide instruction section read by the state machine circuit in sequence are not continuous, the state machine circuit jumps to the branch access state, and the state machine circuit sends the first guide instruction section to a first alternate buffer area and sends the second guide instruction section to a second alternate buffer area in the branch access state;
then, if the second guiding instruction section and the third guiding instruction section read by the state machine circuit in sequence are continuous, the state machine circuit jumps from the branch access state to the continuous access state, and the state machine circuit sends the third guiding instruction section to a second alternate buffer area in the continuous access state;
the state machine circuit is further used for triggering the first alternate buffer area to send the first guide instruction segment to the MCU, and triggering the second alternate buffer area to sequentially send the two guide instruction segments received successively to the MCU, so that the situation that the two discontinuous guide instruction segments are searched for one address unit by one address unit in the same alternate buffer area in the same time sequence period is avoided;
an SPI interface is arranged in the state machine circuit;
Each functional pin of the SPI interface of the flash memory is respectively connected with the corresponding functional pin of the SPI interface of the state machine circuit through an SPI bus; the SPI interface of the flash memory is configured into a 4-wire read mode, so that the SPI interface of the state machine circuit is also adaptively adjusted into the 4-wire read mode;
the write protection pin and the holding pin of the SPI interface of the state machine circuit are configured as data input ends so as to form 4 data lines with parallel data receiving and transmitting functions in one SPI interface, and one guide instruction section is read in one clock period;
the state machine circuit is used for carrying out parallel-serial conversion on binary numbers corresponding to the guide instruction segments received in parallel by the 4 data input ends in the 4-line reading mode of the SPI interface, and then transmitting the binary numbers to a corresponding alternate buffer area; wherein, the alternate buffer is to use serial interface to send and receive data.
2. The MCU boot system of claim 1, wherein the two alternate cache regions are a first alternate cache region and a second alternate cache region, respectively;
if the first guiding instruction section and the second guiding instruction section which are read successively are not continuous, and the second guiding instruction section and the third guiding instruction section which are read successively are not continuous, the state machine is used for sending the first guiding instruction section into a first alternate cache area, sending the second guiding instruction section into a second alternate cache area and sending the third guiding instruction section into the first alternate cache area under the branch access state; the state machine circuit is further used for triggering the first alternate buffer area to send the first guiding instruction section to the MCU, triggering the second alternate buffer area to send the second guiding instruction section to the MCU, and triggering the first alternate buffer area to send the third guiding instruction section to the MCU under the branch access state, so that the situation that two discontinuous guiding instruction sections are searched in the same alternate buffer area one by one address unit in the same time sequence period is avoided.
3. The MCU boot system of claim 1, wherein when the state machine circuit is continuous between two consecutive read boot instruction segments, the state machine circuit enters the continuous access state and then controls the two consecutive read boot instruction segments to be stored in the same alternate buffer until the state machine circuit jumps to the branch access state and controls the last read boot instruction segment to be stored in another alternate buffer when the current two consecutive read boot instruction segments are not continuous.
4. A MCU boot system according to any of claims 2 to 3 wherein during the transfer of a boot instruction segment in one alternate cache region to the MCU, another boot instruction segment is transferred simultaneously to the alternate cache region or to another alternate cache region; the two alternative cache areas are respectively positioned in different storage spaces in the MCU guide system;
the processing process comprises the steps of sending the two successively read guide instruction segments to corresponding alternative cache areas and sending the two successively read guide instruction segments to an MCU from the corresponding alternative cache areas.
5. A MCU guidance system according to any of claims 2-3, wherein the two guidance instruction segments read sequentially by the state machine circuit are consecutive, meaning that the addresses corresponding to the two guidance instruction segments read sequentially by the state machine circuit are consecutive;
the two guiding instruction sections read by the state machine circuit successively are not continuous, which means that the addresses corresponding to the two guiding instruction sections read by the state machine circuit successively are not continuous, and further, the fact that one guiding instruction section read later is jumped relative to one guiding instruction section read earlier is determined;
the boot instruction section is boot program data which is stored in the flash memory in advance, and the boot program data configures an upgrade request port of the MCU to enter a boot mode.
6. A MCU boot system according to any of claims 2 to 3, wherein in the two alternate buffers, when there is no remaining buffer space in either alternate buffer, the continued reading of the boot instruction segment from the flash memory is stopped and the flash memory is configured to a write protected state.
7. The MCU boot system of claim 6, wherein the rate at which the state machine circuit reads the boot instruction segments over the SPI bus is greater than the rate at which the MCU fetches the boot instruction segments from the alternating cache.
8. The MCU boot system of claim 5, wherein after the MCU is booted, the upgrade program in the MCU is further configured to take over the SPI interface of the state machine circuit, so that the MCU performs read/write operations on the flash memory through the SPI interface and the SPI bus connected thereto, to reduce data conversion between different bus transmissions.
9. A chip, wherein the MCU guide system with SPI interface of claim 1 is provided inside the chip.
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