CN116303163B - SPI Flash access method and system of graphics controller - Google Patents

SPI Flash access method and system of graphics controller Download PDF

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Publication number
CN116303163B
CN116303163B CN202310591011.0A CN202310591011A CN116303163B CN 116303163 B CN116303163 B CN 116303163B CN 202310591011 A CN202310591011 A CN 202310591011A CN 116303163 B CN116303163 B CN 116303163B
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spi
spi flash
mcu
client
double
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CN116303163A (en
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汪玉龙
张程
植永耀
陈树辉
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Shenzhen Lesheng Semiconductor Co ltd
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Shenzhen Lesheng Semiconductor Co ltd
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668Details of memory controller
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/40Bus structure
    • G06F13/4004Coupling between buses
    • G06F13/4022Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00General purpose image data processing
    • G06T1/20Processor architectures; Processor configuration, e.g. pipelining
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00General purpose image data processing
    • G06T1/60Memory management
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Information Transfer Systems (AREA)

Abstract

The invention relates to the technical field of graphic controllers, and provides an SPI Flash access method and system of a graphic controller, wherein the graphic controller comprises a SPI/QSPI interface in a master mode and an SPI/QSPI interface in a slave mode; the method comprises the following steps: detecting whether a signal of directly accessing SPI Flash sent by a client MCU is received or not; if a signal of directly accessing SPI Flash sent by the client MCU is received, the client MCU is communicated with the line of the SPI/QSPI interface of the slave mode through a bypass logic unit and is switched to the line of the client MCU and the SPI/QSPI interface of the master mode, so that the client MCU directly accesses the SPI Flash; the defect that the MCU cannot directly access the SPI Flash is overcome.

Description

SPI Flash access method and system of graphics controller
Technical Field
The invention relates to the technical field of graphic controllers, in particular to an SPI Flash access method and system of a graphic controller.
Background
Currently, in the design architecture of the graphics controller, the graphics controller is designed with an SPI/QSPI (serial peripheral interface) input interface, so that a user can conveniently control the graphics controller by using an MCU or the controller through the SPI/QSPI input interface, and meanwhile, the graphics controller is also designed with an SPI/QSPI interface in a master mode for connecting with an SPI Flash.
At present, the architecture design has a problem that if the MCU wants to access the SPI Flash, the MCU needs to access the SPI Flash through the graphics controller, and the SPI Flash cannot be directly accessed due to the fact that the graphics controller is arranged at intervals, so that the access operation efficiency of the MCU to the SPI Flash is low.
Disclosure of Invention
The invention mainly aims to provide an SPI Flash access method and system of a graphics controller, aiming at overcoming the defect that an MCU cannot directly access the SPI Flash.
In order to achieve the above purpose, the invention provides an SPI Flash access method of a graphics controller, wherein the graphics controller comprises a SPI/QSPI interface of a master mode and a SPI/QSPI interface of a slave mode, the graphics controller is connected with the SPI Flash through the SPI/QSPI interface of the master mode, and the graphics controller is connected with a client MCU through the SPI/QSPI interface of the slave mode;
the method comprises the following steps:
detecting whether a signal of directly accessing SPI Flash sent by a client MCU is received or not;
if a signal of directly accessing SPI Flash sent by the client MCU is received, the client MCU is communicated with the line of the SPI/QSPI interface of the slave mode through a bypass logic unit and is switched to the line of the client MCU and the SPI/QSPI interface of the master mode, so that the client MCU directly accesses the SPI Flash; the bypass logic unit is connected with the SPI/QSPI interface of the master mode and the SPI/QSPI interface of the slave mode.
Further, the SPI Flash is configured to store at least one of a picture, a video, an audio, and a font that the graphics controller needs to display when the power failure is detected.
Further, the graphics controller is further connected with a memory, and the memory is a static random access memory.
Further, the graphic controller is also connected with a display screen, and the display screen is a TFT display screen; the graphics controller outputs a TFT signal to the TFT display screen.
Further, the bypass logic unit comprises a bypass circuit, a pass-through circuit, a first double-throw switch and a second double-throw switch;
one end of the bypass circuit is connected with the first double-throw switch, and the other end of the bypass circuit is connected with the second double-throw switch;
the client MCU is connected with the first double-throw switch; the SPIFAsh is connected with the second double-throw switch;
when the client MCU indirectly accesses the SPI Flash, the bypass circuit controls a first double-throw switch to be communicated with the SPI/QSPI interface of the slave mode and controls a second double-throw switch to be communicated with the SPI/QSPI interface of the master mode;
when the client MCU directly accesses the SPI Flash, the bypass circuit controls the first double-throw switch to be communicated with one end of the through circuit, and controls the second double-throw switch to be communicated with the other end of the through circuit, so that the client MCU directly accesses the SPI Flash.
Further, after the step of switching the line communication between the client MCU and the SPI/QSPI interface in the slave mode through the bypass logic unit to the line communication between the client MCU and the SPI/QSPI interface in the master mode, the step of directly accessing the SPI Flash by the client MCU further includes:
acquiring identification information of a client MCU and a time stamp of a signal of the client MCU for directly accessing SPI Flash;
extracting first time characteristic information in the time stamp; wherein the first time characteristic information is date information including a year, a month and a day;
matching corresponding character segmentation rules in a database based on the first time feature information; wherein, the database stores the mapping relation between the first time characteristic information and the character segmentation rule;
dividing the identification information of the client MCU based on the matched character dividing rule to obtain a plurality of identification character combinations; wherein each of the identification character combinations comprises at least one character;
selecting a combination meeting a preset condition from a plurality of identification character combinations as a target character combination;
extracting second time characteristic information in the time stamp; wherein the second time characteristic information is date information including a year and a month;
matching corresponding encoding tables in a database based on the second time feature information; wherein, the database stores the mapping relation between the second time characteristic information and the coding table;
encoding the time stamp based on the matched encoding table to obtain a corresponding encoding value; splicing the target character with the coding value, and taking the obtained spliced character as a marking code; the marking code is used for marking a signal which is sent by the client MCU and directly accesses the SPI Flash.
The invention also provides an SPI Flash access system of the graphic controller, which comprises: the system comprises a graphics controller, an SPI Flash and a bypass logic unit;
the graphics controller comprises a SPI/QSPI interface of a master mode and a SPI/QSPI interface of a slave mode, the graphics controller is connected with the SPI Flash through the SPI/QSPI interface of the master mode, and the graphics controller is connected with a client MCU through the SPI/QSPI interface of the slave mode; the bypass logic unit is connected with the SPI/QSPI interface of the master mode and the SPI/QSPI interface of the slave mode;
the bypass logic unit detects whether a signal which is sent by the client MCU and directly accesses SPI Flash is received or not;
if a signal of directly accessing the SPI Flash sent by the client MCU is received, the client MCU is communicated with the line of the SPI/QSPI interface of the slave mode through a bypass logic unit and is switched to the line communication of the client MCU and the line of the SPI/QSPI interface of the master mode, so that the client MCU directly accesses the SPI Flash.
Further, the SPI Flash is configured to store at least one of a picture, a video, an audio, and a font that the graphics controller needs to display when the power failure is detected.
Further, the graphics controller is further connected with a memory, and the memory is a static random access memory.
Further, the graphic controller is also connected with a display screen, and the display screen is a TFT display screen; the graphics controller outputs a TFT signal to the TFT display screen.
Further, the bypass logic unit comprises a bypass circuit, a pass-through circuit, a first double-throw switch and a second double-throw switch;
one end of the bypass circuit is connected with the first double-throw switch, and the other end of the bypass circuit is connected with the second double-throw switch;
the client MCU is connected with the first double-throw switch; the SPIFAsh is connected with the second double-throw switch;
when the client MCU indirectly accesses the SPI Flash, the bypass circuit controls a first double-throw switch to be communicated with the SPI/QSPI interface of the slave mode and controls a second double-throw switch to be communicated with the SPI/QSPI interface of the master mode;
when the client MCU directly accesses the SPI Flash, the bypass circuit controls the first double-throw switch to be communicated with one end of the through circuit, and controls the second double-throw switch to be communicated with the other end of the through circuit, so that the client MCU directly accesses the SPI Flash.
The invention provides an SPI Flash access method and system of a graphic controller, wherein the graphic controller comprises a SPI/QSPI interface of a master mode and an SPI/QSPI interface of a slave mode, the graphic controller is connected with the SPI Flash through the SPI/QSPI interface of the master mode, and the graphic controller is connected with a client MCU through the SPI/QSPI interface of the slave mode; the method comprises the following steps: detecting whether a signal of directly accessing SPI Flash sent by a client MCU is received or not; if a signal of directly accessing SPI Flash sent by the client MCU is received, the client MCU is communicated with the line of the SPI/QSPI interface of the slave mode through a bypass logic unit and is switched to the line of the client MCU and the SPI/QSPI interface of the master mode, so that the client MCU directly accesses the SPI Flash; the defect that the MCU cannot directly access the SPI Flash is overcome.
Drawings
FIG. 1 is a schematic diagram illustrating steps of a SPIFASH access method of a graphics controller according to an embodiment of the present invention;
FIG. 2 is a block diagram illustrating an SPI Flash access system of a graphics controller according to one embodiment of the present invention.
The achievement of the objects, functional features and advantages of the present invention will be further described with reference to the accompanying drawings, in conjunction with the embodiments.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Referring to fig. 1, in an embodiment of the present invention, a SPIFlash access method of a graphics controller is provided, and referring to fig. 2, the graphics controller includes a master mode SPI/QSPI interface and a slave mode SPI/QSPI interface, the graphics controller is connected to an SPI Flash through the master mode SPI/QSPI interface, and the graphics controller is connected to a client MCU through the slave mode SPI/QSPI interface;
the method comprises the following steps:
step S1, detecting whether a signal of directly accessing SPI Flash sent by a client MCU is received or not;
step S2, if a signal of directly accessing the SPI Flash sent by the client MCU is received, the client MCU is communicated with the line of the SPI/QSPI interface of the slave mode through a bypass logic unit and is switched to the line of the client MCU and the SPI/QSPI interface of the master mode, so that the client MCU directly accesses the SPI Flash; the bypass logic unit is connected with the SPI/QSPI interface of the master mode and the SPI/QSPI interface of the slave mode.
In this embodiment, the graphics controller performs data transmission in a through transmission manner, where the graphics controller is provided with a master mode SPI/QSPI interface and a slave mode SPI/QSPI interface, and the two modes SPI/QSPI interfaces have different roles. The image controller is connected with the SPIflash through the SPI/QSPI interface of the master mode, and is connected with the client MCU through the SPI/QSPI interface of the slave mode. Typically, the client MCU cannot directly access the SPIFlash, and the graphics controller needs to be spaced. In this embodiment, a bypass logic unit is further provided, and the bypass logic unit is connected to the SPI/QSPI interface of the master mode and the SPI/QSPI interface of the slave mode; the bypass logic unit is used for detecting whether a signal of directly accessing the SPI Flash sent by the client MCU is received or not, and when the signal of directly accessing the SPI Flash sent by the client MCU is detected to be received, the client MCU is communicated with a line of the SPI/QSPI interface of the slave mode and is switched to be communicated with a line of the SPI/QSPI interface of the master mode, so that the client MCU directly accesses the SPI Flash. That is, the client MCU is directly connected to the line of the SPI/QSPI interface of the slave mode, so that the client MCU directly accesses the SPI Flash. And the efficiency of the MCU for accessing the SPI Flash is improved.
The client MCU is a client microcontroller, and the SPI Flash is used for storing at least one of pictures, videos, audios and fonts to be displayed by the graphics controller when power failure is detected. The client MCU accesses the SPI Flash, so that the data can be obtained when the power is off.
In an embodiment, the graphics controller is further connected with a memory, and the memory is a static random access memory.
In an embodiment, the graphic controller is further connected with a display screen, and the display screen is a TFT display screen; the graphics controller outputs a TFT signal to the TFT display screen.
In a specific embodiment, the bypass logic unit comprises a bypass circuit, a pass-through circuit, a first double-throw switch and a second double-throw switch;
one end of the bypass circuit is connected with the first double-throw switch, and the other end of the bypass circuit is connected with the second double-throw switch;
the client MCU is connected with the first double-throw switch; the SPIFAsh is connected with the second double-throw switch;
when the client MCU indirectly accesses the SPI Flash, the bypass circuit controls a first double-throw switch to be communicated with the SPI/QSPI interface of the slave mode and controls a second double-throw switch to be communicated with the SPI/QSPI interface of the master mode;
when the client MCU directly accesses the SPI Flash, the bypass circuit controls the first double-throw switch to be communicated with one end of the through circuit, and controls the second double-throw switch to be communicated with the other end of the through circuit, so that the client MCU directly accesses the SPI Flash.
In an embodiment, after the step of switching, through the bypass logic unit, the line communication between the client MCU and the SPI/QSPI interface in the slave mode to the line communication between the client MCU and the SPI/QSPI interface in the master mode, so that the client MCU directly accesses the SPI Flash, the method further includes:
acquiring identification information of a client MCU and a time stamp of a signal of the client MCU for directly accessing SPI Flash;
extracting first time characteristic information in the time stamp; wherein the first time characteristic information is date information including a year, a month and a day;
matching corresponding character segmentation rules in a database based on the first time feature information; wherein, the database stores the mapping relation between the first time characteristic information and the character segmentation rule; different first time characteristic information corresponds to different character segmentation rules, so that different character segmentation rules are adopted in different years, months and days, and the specificity of the character segmentation rules is enhanced. Even the identification information of the same MCU can obtain different segmentation results, namely identification character combinations.
Dividing the identification information of the client MCU based on the matched character dividing rule to obtain a plurality of identification character combinations; wherein each of the identification character combinations comprises at least one character; for example, the character segmentation rule is two-four-X, namely, the identification information of the client MCU is segmented into three identification character combinations sequentially, wherein the three identification character combinations respectively comprise 2, 4 and X characters, and the total number of the characters of the identification information of the client MCU is (2+4+X).
Selecting a combination meeting a preset condition from a plurality of identification character combinations as a target character combination; the preset condition includes the identification character combination of the arranged designated position, for example, the second position is the first identification character combination (including four characters).
Extracting second time characteristic information in the time stamp; wherein the second time characteristic information is date information including a year and a month;
matching corresponding encoding tables in a database based on the second time feature information; wherein, the database stores the mapping relation between the second time characteristic information and the coding table; the second time characteristic information which is different corresponds to the different coding tables, so that the different coding tables are adopted in different years and months, and the coding specificity is enhanced.
Encoding the time stamp based on the matched encoding table to obtain a corresponding encoding value; splicing the target character with the coding value, and taking the obtained spliced character as a marking code; the marking code is used for marking a signal which is sent by the client MCU and directly accesses the SPI Flash.
Referring to fig. 2, in an embodiment of the present invention, there is further provided a SPIFlash access system of a graphics controller, including: the system comprises a graphics controller, an SPI Flash and a bypass logic unit;
the graphics controller comprises a SPI/QSPI interface of a master mode and a SPI/QSPI interface of a slave mode, the graphics controller is connected with the SPI Flash through the SPI/QSPI interface of the master mode, and the graphics controller is connected with a client MCU through the SPI/QSPI interface of the slave mode; the bypass logic unit is connected with the SPI/QSPI interface of the master mode and the SPI/QSPI interface of the slave mode;
the bypass logic unit detects whether a signal which is sent by the client MCU and directly accesses SPI Flash is received or not;
if a signal of directly accessing the SPI Flash sent by the client MCU is received, the client MCU is communicated with the line of the SPI/QSPI interface of the slave mode through a bypass logic unit and is switched to the line communication of the client MCU and the line of the SPI/QSPI interface of the master mode, so that the client MCU directly accesses the SPI Flash.
In an embodiment, the SPI Flash is used for storing at least one of a picture, a video, an audio, and a font that the graphics controller needs to display when the power failure is detected.
In an embodiment, the graphics controller is further connected with a memory, and the memory is a static random access memory.
In an embodiment, the graphic controller is further connected with a display screen, and the display screen is a TFT display screen; the graphics controller outputs a TFT signal to the TFT display screen.
In one embodiment, the bypass logic unit includes a bypass circuit, a pass-through circuit, a first double-throw switch, and a second double-throw switch;
one end of the bypass circuit is connected with the first double-throw switch, and the other end of the bypass circuit is connected with the second double-throw switch;
the client MCU is connected with the first double-throw switch; the SPIFAsh is connected with the second double-throw switch;
when the client MCU indirectly accesses the SPI Flash, the bypass circuit controls a first double-throw switch to be communicated with the SPI/QSPI interface of the slave mode and controls a second double-throw switch to be communicated with the SPI/QSPI interface of the master mode;
when the client MCU directly accesses the SPI Flash, the bypass circuit controls the first double-throw switch to be communicated with one end of the through circuit, and controls the second double-throw switch to be communicated with the other end of the through circuit, so that the client MCU directly accesses the SPI Flash.
In an embodiment, the bypass logic unit switches the line communication between the client MCU and the SPI/QSPI interface of the slave mode to the line communication between the client MCU and the SPI/QSPI interface of the master mode, so that after the step of directly accessing the SPI Flash by the client MCU, the step is further configured to:
acquiring identification information of a client MCU and a time stamp of a signal of the client MCU for directly accessing SPI Flash;
extracting first time characteristic information in the time stamp; wherein the first time characteristic information is date information including a year, a month and a day;
matching corresponding character segmentation rules in a database based on the first time feature information; wherein, the database stores the mapping relation between the first time characteristic information and the character segmentation rule;
dividing the identification information of the client MCU based on the matched character dividing rule to obtain a plurality of identification character combinations; wherein each of the identification character combinations comprises at least one character;
selecting a combination meeting a preset condition from a plurality of identification character combinations as a target character combination;
extracting second time characteristic information in the time stamp; wherein the second time characteristic information is date information including a year and a month;
matching corresponding encoding tables in a database based on the second time feature information; wherein, the database stores the mapping relation between the second time characteristic information and the coding table;
encoding the time stamp based on the matched encoding table to obtain a corresponding encoding value; splicing the target character with the coding value, and taking the obtained spliced character as a marking code; the marking code is used for marking a signal which is sent by the client MCU and directly accesses the SPI Flash.
In this embodiment, for specific implementation of each unit in the above system embodiment, please refer to the description in the above method embodiment, and no further description is given here.
In summary, in the method and system for accessing SPI Flash of a graphics controller according to the embodiments of the present invention, the graphics controller includes a master mode SPI/QSPI interface and a slave mode SPI/QSPI interface, the graphics controller is connected to the SPI Flash through the master mode SPI/QSPI interface, and the graphics controller is connected to a client MCU through the slave mode SPI/QSPI interface; the method comprises the following steps: detecting whether a signal of directly accessing SPI Flash sent by a client MCU is received or not; if a signal of directly accessing SPI Flash sent by the client MCU is received, the client MCU is communicated with the line of the SPI/QSPI interface of the slave mode through a bypass logic unit and is switched to the line of the client MCU and the SPI/QSPI interface of the master mode, so that the client MCU directly accesses the SPI Flash; the defect that the MCU cannot directly access the SPI Flash is overcome.
Those skilled in the art will appreciate that implementing all or part of the above described methods may be accomplished by way of a computer program stored on a non-transitory computer readable storage medium, which when executed, may comprise the steps of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium provided by the present invention and used in embodiments may include non-volatile and/or volatile memory. The nonvolatile memory can include Read Only Memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual speed data rate SDRAM (SSRSDRAM), enhanced SDRAM (ESDRAM), synchronous Link DRAM (SLDRAM), memory bus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), among others.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, apparatus, article, or method that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, apparatus, article, or method. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, apparatus, article or method that comprises the element.
The foregoing description is only of the preferred embodiments of the present invention and is not intended to limit the scope of the invention, and all equivalent structures or equivalent processes using the descriptions and drawings of the present invention or direct or indirect application in other related technical fields are included in the scope of the present invention.

Claims (9)

1. The SPI Flash access method of the graphic controller is characterized in that the graphic controller comprises a SPI/QSPI interface of a master mode and a SPI/QSPI interface of a slave mode, the graphic controller is connected with the SPI Flash through the SPI/QSPI interface of the master mode, and the graphic controller is connected with a client MCU through the SPI/QSPI interface of the slave mode;
the method comprises the following steps:
detecting whether a signal of directly accessing SPI Flash sent by a client MCU is received or not;
if a signal of directly accessing SPI Flash sent by the client MCU is received, the client MCU is communicated with the line of the SPI/QSPI interface of the slave mode through a bypass logic unit and is switched to the line of the client MCU and the SPI/QSPI interface of the master mode, so that the client MCU directly accesses the SPI Flash; the bypass logic unit is connected with the SPI/QSPI interface of the master mode and the SPI/QSPI interface of the slave mode;
acquiring identification information of a client MCU and a time stamp of a signal of the client MCU for directly accessing SPI Flash;
extracting first time characteristic information in the time stamp; wherein the first time characteristic information is date information including a year, a month and a day;
matching corresponding character segmentation rules in a database based on the first time feature information; wherein, the database stores the mapping relation between the first time characteristic information and the character segmentation rule;
dividing the identification information of the client MCU based on the matched character dividing rule to obtain a plurality of identification character combinations; wherein each of the identification character combinations comprises at least one character;
selecting a combination meeting a preset condition from a plurality of identification character combinations as a target character combination;
extracting second time characteristic information in the time stamp; wherein the second time characteristic information is date information including a year and a month;
matching corresponding encoding tables in a database based on the second time feature information; wherein, the database stores the mapping relation between the second time characteristic information and the coding table;
encoding the time stamp based on the matched encoding table to obtain a corresponding encoding value; splicing the target character with the coding value, and taking the obtained spliced character as a marking code; the marking code is used for marking a signal which is sent by the client MCU and directly accesses the SPI Flash.
2. The method for accessing SPI Flash of a graphic controller according to claim 1, wherein the SPI Flash is used for storing at least one of a picture, a video, an audio, and a font that the graphic controller needs to display when power failure is detected.
3. The SPI Flash access method of a graphics controller according to claim 1, wherein the graphics controller is further connected with a memory, the memory being a static random access memory.
4. The SPI Flash access method of a graphics controller according to claim 1, wherein the graphics controller is further connected with a display screen, the display screen being a TFT display screen; the graphics controller outputs a TFT signal to the TFT display screen.
5. The SPI Flash access method of a graphics controller of claim 1, wherein the bypass logic unit comprises a bypass circuit, a pass-through circuit, a first double-throw switch, and a second double-throw switch;
one end of the bypass circuit is connected with the first double-throw switch, and the other end of the bypass circuit is connected with the second double-throw switch;
the client MCU is connected with the first double-throw switch; the SPI Flash is connected with a second double-throw switch;
when the client MCU indirectly accesses the SPI Flash, the bypass circuit controls a first double-throw switch to be communicated with the SPI/QSPI interface of the slave mode and controls a second double-throw switch to be communicated with the SPI/QSPI interface of the master mode;
when the client MCU directly accesses the SPI Flash, the bypass circuit controls the first double-throw switch to be communicated with one end of the through circuit, and controls the second double-throw switch to be communicated with the other end of the through circuit, so that the client MCU directly accesses the SPI Flash.
6. An SPI Flash access system for a graphics controller, comprising: the system comprises a graphics controller, an SPI Flash and a bypass logic unit;
the graphics controller comprises a SPI/QSPI interface of a master mode and a SPI/QSPI interface of a slave mode, the graphics controller is connected with the SPI Flash through the SPI/QSPI interface of the master mode, and the graphics controller is connected with a client MCU through the SPI/QSPI interface of the slave mode; the bypass logic unit is connected with the SPI/QSPI interface of the master mode and the SPI/QSPI interface of the slave mode;
the bypass logic unit detects whether a signal which is sent by the client MCU and directly accesses SPI Flash is received or not;
if a signal of directly accessing SPI Flash sent by the client MCU is received, the client MCU is communicated with the line of the SPI/QSPI interface of the slave mode through a bypass logic unit and is switched to the line of the client MCU and the SPI/QSPI interface of the master mode, so that the client MCU directly accesses the SPI Flash;
the bypass logic unit is further configured to:
acquiring identification information of a client MCU and a time stamp of a signal of the client MCU for directly accessing SPI Flash;
extracting first time characteristic information in the time stamp; wherein the first time characteristic information is date information including a year, a month and a day;
matching corresponding character segmentation rules in a database based on the first time feature information; wherein, the database stores the mapping relation between the first time characteristic information and the character segmentation rule;
dividing the identification information of the client MCU based on the matched character dividing rule to obtain a plurality of identification character combinations; wherein each of the identification character combinations comprises at least one character;
selecting a combination meeting a preset condition from a plurality of identification character combinations as a target character combination;
extracting second time characteristic information in the time stamp; wherein the second time characteristic information is date information including a year and a month;
matching corresponding encoding tables in a database based on the second time feature information; wherein, the database stores the mapping relation between the second time characteristic information and the coding table;
encoding the time stamp based on the matched encoding table to obtain a corresponding encoding value; splicing the target character with the coding value, and taking the obtained spliced character as a marking code; the marking code is used for marking a signal which is sent by the client MCU and directly accesses the SPI Flash.
7. The SPI Flash access system of the graphics controller according to claim 6, wherein the SPI Flash is configured to store at least one of a picture, a video, an audio, and a font that the graphics controller needs to display when a power failure is detected.
8. The SPI Flash access system of a graphics controller of claim 6, wherein said graphics controller is further coupled to a memory, said memory being a static random access memory; the graphic controller is also connected with a display screen, and the display screen is a TFT display screen; the graphics controller outputs a TFT signal to the TFT display screen.
9. The SPI Flash access system of the graphics controller of claim 6, wherein the bypass logic unit comprises a bypass circuit, a pass-through circuit, a first double-throw switch, and a second double-throw switch;
one end of the bypass circuit is connected with the first double-throw switch, and the other end of the bypass circuit is connected with the second double-throw switch;
the client MCU is connected with the first double-throw switch; the SPI Flash is connected with a second double-throw switch;
when the client MCU indirectly accesses the SPI Flash, the bypass circuit controls a first double-throw switch to be communicated with the SPI/QSPI interface of the slave mode and controls a second double-throw switch to be communicated with the SPI/QSPI interface of the master mode;
when the client MCU directly accesses the SPI Flash, the bypass circuit controls the first double-throw switch to be communicated with one end of the through circuit, and controls the second double-throw switch to be communicated with the other end of the through circuit, so that the client MCU directly accesses the SPI Flash.
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