CN111967212B - Method, system and storage medium for hierarchical design chip timing sequence convergence - Google Patents
Method, system and storage medium for hierarchical design chip timing sequence convergence Download PDFInfo
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Abstract
The application provides a method and a system for hierarchical design chip timing sequence convergence, wherein the method comprises the following steps: finishing the first standard unit placement according to the design data of the whole chip; finishing the placement of the standard unit for the second time according to the design data of the sub-module; wherein the sub-module design data comprises a sub-module timing model; comparing the sub-module time sequence model with the physical delay information at the port of the sub-module to obtain missing time sequence arc data; and performing script language conversion according to the time sequence arc data and the time information to finish time sequence convergence of the interface design of the submodule. The technical scheme can avoid the problem that the design cycle of the chip is prolonged due to the loss of the ETM model time sequence arcs or inaccurate delay information in the early design stage, effectively shorten the design cycle, accelerate the on-chip marketing process and promote the product appearance time.
Description
Technical Field
The invention relates to the technical field of chip design, in particular to a method, a system and a storage medium for hierarchical design of chip timing sequence convergence.
Background
With the increasing difficulty of chip design, the scale enlargement and the process size reduction, the convergence rate of chip physical realization directly influences the time of mass production and marketing of chips, so that the improvement of the physical convergence rate of chips is of great importance. At present, a parallel hierarchical design strategy is adopted in medium-large-scale chip physical design, a physical model and a time sequence model provided by a second level are required to be used in a design process of a first level, and a physical model and a time sequence model provided by a third level are required to be used in a design process of a second level. The time sequence model uses an extracted timing model, ETM for short. ETMs are extracted by EDA tools by second level or third level designers. ETM extraction involves two phases, before and after the clock tree insertion.
The existing method for generating the ETM has the problems of time sequence arc loss, data link physical delay loss, incapability of embodying constant path physical delay, and inconsistency of extracted physical link delay and a first level; loss of timing arcs or data link physical delay can cause the timing convergence efficiency between the first level and the second level to be greatly reduced, and inconsistency between the extracted physical link delay and the first level can cause timing violations not to be seen in the optimization process of the first level, but the timing convergence of a chip can require re-iteration convergence as an example of a very serious timing seen in the splicing stage of the first level and the second level at the later stage of design completion.
Disclosure of Invention
The invention provides a method and a system for hierarchical design of chip timing sequence convergence, which can be used for detecting timing sequence arc loss, data link physical delay loss and constant path physical delay at the early stage of design and improving the timing sequence convergence efficiency at the splicing part of a first level and a second level.
One embodiment of the present invention provides a method for hierarchical design of chip timing convergence, including:
finishing the first standard unit placement according to the design data of the whole chip;
finishing the placement of the standard unit for the second time according to the design data of the sub-module; wherein the sub-module design data comprises a sub-module timing model;
comparing the sub-module time sequence model with the physical delay information at the port of the sub-module to obtain missing time sequence arc data;
and performing script language conversion according to the time sequence arc data and the time information to finish time sequence convergence of the interface design of the submodule.
Further, the method for hierarchical design of chip timing closure further includes: and acquiring the information placed by the first standard unit and the physical delay information at the port of the submodule after pre-winding through a submodule port clock.
Further, the performing script language conversion according to the time sequence arc data and the time information and before completing time sequence convergence of the interface design of the submodule further includes: time information is acquired.
Further, the first standard cell placement comprises timing driven placement and congestion degree driven placement.
Further, the sub-module design data further includes a sub-module physical model.
Further, the first standard cell placement is completed according to the design data of the full chip and the second standard cell placement is completed according to the design data of the sub-module.
One embodiment of the present invention provides a device for hierarchical design of chip timing convergence, including:
the first standard unit placement module is used for finishing first standard unit placement according to the design data of the whole chip;
the second standard unit placement module is used for finishing the second standard unit placement according to the design data of the sub-module; wherein the sub-module design data comprises a sub-module timing model;
the time sequence arc data acquisition module is used for comparing the sub-module time sequence model with the physical delay information at the port of the sub-module to acquire missing time sequence arc data;
and the script language conversion module is used for performing script language conversion according to the time sequence arc data and the time information to finish time sequence convergence of the interface design of the submodule.
Further, the apparatus for hierarchical design chip timing closure is characterized by further comprising: and the physical delay information acquisition module is used for acquiring the information placed by the first standard unit and the physical delay information at the port of the sub-module after pre-winding through a sub-module port clock.
Further, the apparatus for hierarchical design chip timing closure is characterized by further comprising: and the time information acquisition module is used for acquiring the time information.
The present invention also provides a computer-readable storage medium, comprising: the storage medium comprises a stored computer program, wherein when the computer program runs, the device where the computer readable storage medium is located is controlled to execute any one of the methods for hierarchical design chip timing convergence.
Compared with the prior art, the embodiment of the invention has the beneficial effects that:
one embodiment of the present application provides a method for hierarchical design of chip timing convergence, including: finishing the first standard unit placement according to the design data of the whole chip; finishing the placement of the standard unit for the second time according to the design data of the sub-module; wherein the sub-module design data comprises a sub-module timing model; comparing the sub-module time sequence model with the physical delay information at the port of the sub-module to obtain missing time sequence arc data; and performing script language conversion according to the time sequence arc data and the time information to finish time sequence convergence of the interface design of the submodule. The technical scheme can avoid the problem that the design cycle of the chip is prolonged due to the loss of the ETM model time sequence arcs or inaccurate delay information in the early design stage, effectively shorten the design cycle, accelerate the on-chip marketing process and promote the product appearance time.
Drawings
In order to more clearly illustrate the technical solution of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a flowchart of a method for hierarchical design of chip timing closure according to an embodiment of the present invention;
FIG. 2 is a flowchart of a method for hierarchical design of chip timing closure according to another embodiment of the present invention;
FIG. 3 is a block diagram of a system for hierarchical design of chip timing closure according to an embodiment of the present invention;
FIG. 4 is a block diagram of a system for hierarchical design of chip timing closure according to another embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be understood that the step numbers used herein are for convenience of description only and are not intended as limitations on the order in which the steps are performed.
It is to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the specification of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
The terms "comprises" and "comprising" indicate the presence of the described features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
The term "and/or" refers to and includes any and all possible combinations of one or more of the associated listed items.
A first aspect.
Referring to fig. 1, an embodiment of the invention provides a method for hierarchical design of chip timing convergence, including:
and S10, finishing the first standard cell placement according to the design data of the full chip.
In one embodiment, the first standard cell placement comprises a timing driven placement and a congestion driven placement.
S20, finishing the placement of the standard cells for the second time according to the design data of the sub-modules; wherein the sub-module design data comprises a sub-module timing model.
In a specific embodiment, the sub-module design data further includes a sub-module physical model.
In another embodiment, step S10: completing the first standard cell placement according to the design data of the full chip, and step S20: finishing the placement of the standard unit for the second time according to the design data of the sub-module; the design data of the sub-modules comprise sub-module time sequence models, and the sub-module time sequence models are simultaneously carried out, so that the efficiency is improved.
And S30, comparing the sub-module time sequence model with the physical delay information at the sub-module port, and acquiring missing time sequence arc data.
And S40, performing script language conversion according to the time sequence arc data and the time information, and finishing the time sequence convergence of the interface design of the submodule.
Specifically, the method comprises the following steps: and converting the missing time sequence arcs combined with the arrival time into a script language and converting the time sequence arcs of which the port delay is far greater than the arrival time of the first layer and the captured arrival time in the ETM into the script language according to the arrival time of the first layer.
One embodiment of the present application provides a method for hierarchical design of chip timing convergence, including: finishing the first standard unit placement according to the design data of the whole chip; finishing the placement of the standard unit for the second time according to the design data of the sub-module; wherein the sub-module design data comprises a sub-module timing model; comparing the sub-module time sequence model with the physical delay information at the port of the sub-module to obtain missing time sequence arc data; and performing script language conversion according to the time sequence arc data and the time information to finish time sequence convergence of the interface design of the submodule. The technical scheme can avoid the problem that the design cycle of the chip is prolonged due to the loss of the ETM model time sequence arcs or inaccurate delay information in the early design stage, effectively shorten the design cycle, accelerate the on-chip marketing process and promote the product appearance time.
Referring to fig. 2, an embodiment of the present invention provides a method for hierarchical design of chip timing convergence, further including:
and S11, acquiring the information placed by the first standard cell and the physical delay information at the sub-module port after pre-winding through the sub-module port clock.
And S31, acquiring time information.
Specifically, the method comprises the following steps: and comparing the missing time sequence arcs and the consistency of the captured data arrival time and the data time sequence arcs in the ETM.
A second aspect.
Referring to fig. 3-4, an embodiment of the invention provides a system for hierarchical design of chip timing convergence, including:
the first standard cell placement module 10 is configured to complete a first standard cell placement according to design data of a full chip.
In one embodiment, the first standard cell placement comprises a timing driven placement and a congestion driven placement.
The second standard cell placement module 20 is used for completing the second standard cell placement according to the design data of the sub-modules; wherein the sub-module design data comprises a sub-module timing model.
In a specific embodiment, the sub-module design data further includes a sub-module physical model.
In another embodiment, the step of completing the first standard cell placement according to the design data of the full chip, and the step of completing the second standard cell placement according to the design data of the sub-module; the design data of the sub-modules comprise sub-module time sequence models, and the sub-module time sequence models are simultaneously carried out, so that the efficiency is improved.
The time sequence arc data obtaining module 30 is configured to compare the sub-module time sequence model with the physical delay information at the sub-module port, and obtain missing time sequence arc data.
And the script language conversion module 40 is used for performing script language conversion according to the time sequence arc data and the time information to complete time sequence convergence of the interface design of the submodule.
Specifically, the method comprises the following steps: and converting the missing time sequence arcs combined with the arrival time into a script language and converting the time sequence arcs of which the port delay is far greater than the arrival time of the first layer and the captured arrival time in the ETM into the script language according to the arrival time of the first layer.
The physical delay information obtaining module 50 is configured to obtain, through the sub-module port clock, the information placed in the first standard cell and the physical delay information at the sub-module port after the pre-winding.
The time information obtaining module 60 is used for obtaining time information.
Specifically, the method comprises the following steps: and comparing the missing time sequence arcs and the consistency of the captured data arrival time and the data time sequence arcs in the ETM.
In a third aspect.
An embodiment of the present invention provides a computer-readable storage medium, including: the storage medium includes a stored computer program, wherein the computer program, when executed, controls an apparatus on which the computer readable storage medium is located to perform a method of hierarchical design chip timing closure according to any one of claims 1 to 6.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention.
Claims (8)
1. A method for hierarchical design of chip timing closure is characterized by comprising the following steps:
finishing the first standard unit placement according to the design data of the whole chip; the first time of standard unit placement comprises time sequence drive placement and congestion degree drive placement;
meanwhile, finishing the placement of the standard unit for the second time according to the design data of the sub-module; wherein the sub-module design data comprises a sub-module timing model;
comparing the sub-module time sequence model with the physical delay information at the port of the sub-module to obtain missing time sequence arc data;
and performing script language conversion according to the time sequence arc data and the time information, converting the missing time sequence arc combined arrival time into a script language, converting the time sequence arc of which the port delay is far greater than the first layer and the captured arrival time in the ETM into the script language according to the first-layer arrival time, and finishing the design time sequence convergence of the submodule interface.
2. The method of claim 1, further comprising: and acquiring the information placed by the first standard unit and the physical delay information at the port of the submodule after pre-winding through a submodule port clock.
3. The method of claim 1, wherein before performing scripting language conversion according to the timing arc data and time information to complete timing closure of interface design of the submodule, the method further comprises: time information is acquired.
4. The method of claim 1, wherein the sub-module design data further includes a sub-module physical model.
5. An apparatus for hierarchical design of chip timing closure, comprising:
the first standard unit placement module is used for finishing first standard unit placement according to the design data of the whole chip; the first time of standard unit placement comprises time sequence drive placement and congestion degree drive placement;
the second standard unit placement module is used for finishing the second standard unit placement according to the design data of the sub-module; wherein the sub-module design data comprises a sub-module timing model; the first standard cell placing module and the second standard cell placing module are carried out simultaneously;
the time sequence arc data acquisition module is used for comparing the sub-module time sequence model with the physical delay information at the port of the sub-module to acquire missing time sequence arc data;
and the script language conversion module is used for converting the script language according to the time sequence arc data and the time information, converting the missing time sequence arc combined arrival time into the script language, converting the time sequence arc of which the port delay is far greater than the first layer and the captured arrival time in the ETM into the script language according to the first layer arrival time, and finishing the design time sequence convergence of the sub-module interface.
6. The apparatus for hierarchical design chip timing closure according to claim 5, further comprising: and the physical delay information acquisition module is used for acquiring the information placed by the first standard unit and the physical delay information at the port of the sub-module after pre-winding through a sub-module port clock.
7. The apparatus for hierarchical design chip timing closure according to claim 5, further comprising: and the time information acquisition module is used for acquiring the time information.
8. A computer-readable storage medium, comprising: the storage medium includes a stored computer program, wherein the computer program, when executed, controls an apparatus on which the computer readable storage medium is located to perform a method of hierarchical design chip timing closure according to any one of claims 1 to 4.
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| CN106599498A (en) * | 2016-12-20 | 2017-04-26 | 盛科网络（苏州）有限公司 | Method for improving chip verification coverage rate based on tree backtracking algorithm |
| CN108830008B (en) * | 2018-06-28 | 2022-03-08 | 中国科学院微电子研究所 | Test method and test system for full model of standard cell library |
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| CN105138774A (en) * | 2015-08-25 | 2015-12-09 | 中山大学 | Timing sequence post-simulation method based on integrated circuit hiberarchy design |
| CN108984806A (en) * | 2017-05-31 | 2018-12-11 | 深圳市中兴微电子技术有限公司 | A kind of clock tree synthesis method and computer readable storage medium |
| CN109948221A (en) * | 2019-03-12 | 2019-06-28 | 天津芯海创科技有限公司 | A kind of method of top layer exact constraint block port timing |
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Denomination of invention: A Method, System and Storage Medium of Hierarchical Design Chip Timing closure Effective date of registration: 20230322 Granted publication date: 20210518 Pledgee: Shanghai Pudong Development Bank Limited by Share Ltd. Guangzhou branch Pledgor: UNICMICRO (GUANGZHOU) Co.,Ltd. Registration number: Y2023980035757 |
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