CN108984806A - A kind of clock tree synthesis method and computer readable storage medium - Google Patents
A kind of clock tree synthesis method and computer readable storage medium Download PDFInfo
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- CN108984806A CN108984806A CN201710405083.6A CN201710405083A CN108984806A CN 108984806 A CN108984806 A CN 108984806A CN 201710405083 A CN201710405083 A CN 201710405083A CN 108984806 A CN108984806 A CN 108984806A
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
- G06F30/3312—Timing analysis
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Abstract
The invention discloses a kind of clock tree synthesis method and computer readable storage mediums, it include: after submodule in full chip finishes clock tree balance, it obtains and top-level module has clock delay of the register of timing inspection inside submodule, calculate several statistical values of the clock delay grabbed out；A statistical value reactionary slogan, anti-communist poster of clock delay is chosen to full chip, full chip is instructed to carry out global clock tree balance.The present invention passes through the clock delay numerical value of acquisition submodule and top-level module interface register inside submodule, reactionary slogan, anti-communist poster carries out global clock tree balance to full chip, have ignored the clock delay for not having a large amount of unrelated registers of logic interaction inside submodule with top-level module, improve the accuracy of reactionary slogan, anti-communist poster numerical value, so that submodule and top-level module interface are not in that a large amount of timing breaks rules, the speed for accelerating full chip timing closure, shortens the design cycle.
Description
Technical field
The present invention relates to chip design art field more particularly to a kind of clock tree synthesis method and computer-readable deposit
Storage media.
Background technique
In digital integrated electronic circuit, timing reference of the clock signal as entire chip, performance and work to chip are surely
It is qualitative to play a crucial role.Timing closure is one of most important task in Design of Digital Integrated Circuit.With integrated
Circuit design enters deep sub-micron era, and chip-scale is continuously increased, and designs increasingly sophisticated, and the difficulty of timing closure is also therewith
It is increasing.
Hierarchical Design is a kind of design method of the chip of most common integrated circuit, in the design method, to be set
The chip of meter has been partitioned into many submodules, and each submodule is individually designed, is then called by top-level module, this design side
Huge and complicated design is divided into several segmentation blocks (Partition) in physical design phase by method, to each submodule list
Clock tree balance is solely carried out, full chip only needs to pay close attention to the clock delay of the register of submodule interface, can make in this way
The period of design significantly improves, and sequence problem is made to localize.
But existing Digital Design realizes that (Encounter Digital Implementation, EDI) tool quotes son
The clock delay of all registers in module, and provide the maximum value and minimum value of clock delay, the data come out with
The true clock delay of register has certain deviation, and the clock delay numerical value for thereby resulting in reactionary slogan, anti-communist poster to top layer is distorted, and causes complete
The clock delay of chip global clock tree balance is different in size between full chip register and submodule block register, occurs a large amount of
Timing breaks rules.
Summary of the invention
In order to solve the above-mentioned technical problems, the present invention provides a kind of clock tree synthesis method and computer-readable storages
Medium can accelerate the speed of full chip timing closure and shorten the design cycle.
In order to reach the object of the invention, the technical solution of the embodiment of the present invention is achieved in that
The embodiment of the invention provides a kind of clock tree synthesis methods, comprising:
After submodule in full chip finishes clock tree balance, obtains and top-level module has the register of timing inspection in son
The clock delay of inside modules calculates several statistical values of the clock delay of acquisition；
Submodule chooses a statistical value reactionary slogan, anti-communist poster of clock delay to full chip, instructs full chip to carry out global clock tree flat
Weighing apparatus.
Further, the acquisition and top-level module have clock delay packet of the register of timing inspection inside submodule
It includes:
The submodule generates all timing paths relevant to port, and described and top is selected from the timing path
Layer module has clock delay of the register of timing inspection inside submodule.
Further, several statistical values of the clock delay include maximum value, minimum value, average value and distributed area
Between.
Further, before the method further include:
The full chip is divided into several described submodules and a top-level module；
Each submodule individually carries out clock tree balance.
The embodiment of the invention also provides a kind of computer readable storage medium, the computer-readable recording medium storage
There is one or more program, one or more of programs can be executed by one or more processor, following to realize
Step:
After submodule in full chip finishes clock tree balance, obtains and top-level module has the register of timing inspection in son
The clock delay of inside modules calculates several statistical values of the clock delay of acquisition；
Submodule chooses a statistical value reactionary slogan, anti-communist poster of clock delay to full chip, instructs full chip to carry out global clock tree flat
Weighing apparatus.
Further, the acquisition and top-level module have clock delay of the register of timing inspection inside submodule
Before step, one or more of programs can also be executed by one or more of processors, to perform the steps of
The submodule generates all timing paths relevant to port, and described and top is selected from the timing path
Layer module has clock delay of the register of timing inspection inside submodule.
Further, several statistical values of the clock delay include maximum value, minimum value, average value and distributed area
Between.
Further, before the submodule in the full chip finishes the step after clock tree balance, it is one or
Multiple programs can also be executed by one or more of processors, to perform the steps of
The full chip is divided into several described submodules and a top-level module；
Each submodule individually carries out clock tree balance.
Technical solution of the present invention has the following beneficial effects:
Clock tree synthesis method provided by the invention and computer readable storage medium, pass through acquisition submodule and top layer
Clock delay (Clock Latency) numerical value of register inside submodule at module interface, reactionary slogan, anti-communist poster carry out complete to full chip
Office clock tree balance (Clock Tree Balance), has ignored inside submodule with top-level module that not have logic to interact a large amount of
The clock delay of unrelated register improves the accuracy of reactionary slogan, anti-communist poster numerical value, so that submodule and top-level module interface will not go out
Now a large amount of timing breaks rules, and accelerates the speed of full chip timing closure, shortens the design cycle.
Detailed description of the invention
The drawings described herein are used to provide a further understanding of the present invention, constitutes part of this application, this hair
Bright illustrative embodiments and their description are used to explain the present invention, and are not constituted improper limitations of the present invention.In the accompanying drawings:
Fig. 1 is existing Clock Tree equilibrium principle schematic diagram；
Fig. 2 is a kind of flow diagram of clock tree synthesis method of the embodiment of the present invention；
Fig. 3 is that the timing at Neutron module of embodiment of the present invention port checks schematic diagram；
Fig. 4 is the clock delay schematic diagram of full chip and submodule interface in the embodiment of the present invention.
Specific embodiment
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with attached drawing to the present invention
Embodiment be described in detail.It should be noted that in the absence of conflict, in the embodiment and embodiment in the application
Feature can mutual any combination.
Usually there is a large amount of register in one chip design, register is timing unit of the clock along triggering, from not
Open clock signal.Clock signal will drive associated all registers, and the time that clock signal reaches register, we claimed
Be clock delay (Clock Latency), as shown in Figure 1, an ideal clock tree balance is each register of arrival
Clock delay is equally big.
As shown in Fig. 2, a kind of clock tree synthesis method according to the present invention, includes the following steps:
Step 201: after the submodule in full chip finishes clock tree balance, obtaining and top-level module has posting for timing inspection
Clock delay of the storage inside submodule calculates several statistical values of the clock delay of acquisition；
Further, before the step 201, the method also includes:
Full chip is divided into several submodules and a top-level module, each submodule individually carries out clock tree balance.
It is worth noting that for the submodule for finishing clock tree synthesis, clock of the clock signal to each register
Delay it has been determined that submodule internal register to the timing between register whether can restrain also substantially determine, uniquely cannot
Determining sequence problem is exactly the place of submodule and top-level module interface.Therefore, the present invention is only obtained with top-level module sometimes
Clock delay of the register of sequence inspection inside submodule, and ignore inside submodule does not have logic to interact with top-level module
The clock delay of a large amount of unrelated registers, to obtain submodule and top-level module interface register is true inside submodule
The numerical value of real-time clock (RTC) delay, accurate due to reactionary slogan, anti-communist poster numerical value, after full chip finishes clock tree balance, submodule and top-level module are connect
Be not in that a large amount of timing break rules at mouthful, the speed of full chip timing closure can be accelerated and shorten the design cycle.
Further, the acquisition and top-level module have clock delay packet of the register of timing inspection inside submodule
Include: submodule generates all timing paths relevant to port, and selects from the timing path and have timing with top-level module
Clock delay of the register of inspection inside submodule.
In an embodiment of the present invention, as shown in figure 3, the first register FF1 and the second register FF2 are located in submodule
Portion, and mutually independent clock signal clk A ' and CLKB ' is used respectively, the port DIN is data-in port, and the port DOUT is
Data-out port, the BUF in submodule are to finish the clock buffer being inserted into after clock tree balance inside submodule.Submodule
Generate all timing paths relevant to port, the timing path include the port DIN to FF1 data input pin (FF1/D),
CLKA ' arrives FF2 input end of clock (FF2/CK) to FF1 input end of clock (FF1/CK) and CLKB ', selected and top-level module
The register for having timing inspection is FF1 and FF2, the clock delay inside submodule be respectively CLKA ' to FF1/CK when
Clock delay and CLKB ' arrive the clock delay of FF2/CK.
Further, several statistical values of the clock delay include maximum value, minimum value, average value and distributed area
Between.
Step 202: submodule chooses a statistical value reactionary slogan, anti-communist poster of clock delay to full chip, instructs full chip to carry out global
Clock tree balance.
It should be noted that choosing which statistical value (maximum value, minimum value, average value or the distributed area of clock delay
Between) reactionary slogan, anti-communist poster give full chip, need to be repeated trial using each statistical value, and determine according to the timing results obtained after trial
It is fixed which statistical value finally used, select timing results closest to the statistical value reactionary slogan, anti-communist poster of clock tree balance to full chip.Or
Rule of thumb, maximum value reactionary slogan, anti-communist poster is generally selected to full chip.The present invention is it is emphasised that only obtaining has timing inspection with top-level module
Clock delay of the register inside submodule, as chip complete in step 202 how according to the statistical value of clock delay into
Row global clock tree balance can realize by timing budget method in the prior art, and the present invention is to this and with no restrictions.
As shown in figure 4, third register FF3 and the 4th register FF4 are located at outside submodule, third register FF3 and
First register FF1 common clock signal CLKA, the 4th register FF4 and the second register FF2 common clock signal CLKB.From
The clock delay reactionary slogan, anti-communist poster of the clock delay and CLKB ' of the CLKA ' Dao FF1/CK selected in step 203 to FF2/CK give full chip
Afterwards, pass through EDA (Electronics Design Automation) tool autobalance CLKA to FF1/CK and CLKA to FF3
The clock delay of input end of clock (FF3/CK) can similarly obtain the clock tree balance between FF2 and FF4.
The present invention also provides a kind of computer readable storage medium, the computer-readable recording medium storage has one
Or multiple programs, one or more of programs can be executed by one or more processor, to perform the steps of
After submodule in full chip finishes clock tree balance, obtains and top-level module has the register of timing inspection in son
The clock delay of inside modules calculates several statistical values of the clock delay of acquisition；
Submodule chooses a statistical value reactionary slogan, anti-communist poster of clock delay to full chip, instructs full chip to carry out global clock tree flat
Weighing apparatus.
Further, before the submodule in the full chip finishes the step after clock tree balance, it is one or
Multiple programs can also be executed by one or more of processors, to perform the steps of
Full chip is divided into several submodules and a top-level module；
Each submodule individually carries out clock tree balance.
It is worth noting that for the submodule for finishing clock tree synthesis, clock of the clock signal to each register
Delay it has been determined that submodule internal register to the timing between register whether can restrain also substantially determine, uniquely cannot
Determining sequence problem is exactly the place of submodule and top-level module interface.Therefore, the present invention is only obtained with top-level module sometimes
Clock delay of the register of sequence inspection inside submodule, and ignore inside submodule does not have logic to interact with top-level module
The clock delay of a large amount of unrelated registers, to obtain submodule and top-level module interface register is true inside submodule
The numerical value of real-time clock (RTC) delay, accurate due to reactionary slogan, anti-communist poster numerical value, after full chip finishes clock tree balance, submodule and top-level module are connect
Be not in that a large amount of timing break rules at mouthful, the speed of full chip timing closure can be accelerated and shorten the design cycle.
Further, the acquisition and top-level module have clock delay of the register of timing inspection inside submodule
Before step, one or more of programs can also be executed by one or more of processors, to perform the steps of
Submodule generates all timing paths relevant to port, and selects from the timing path and have with top-level module
Clock delay of the register of timing inspection inside submodule.
In an embodiment of the present invention, described as shown in figure 3, submodule generates all timing paths relevant to port
Timing path includes the port DIN to FF1 data input pin (FF1/D), CLKA ' to FF1 input end of clock (FF1/CK) and CLKB '
To FF2 input end of clock (FF2/CK), selected has the register of timing inspection for FF1 and FF2 with top-level module, in son
The clock delay of inside modules is respectively the clock delay of CLKA ' to FF1/CK and the clock delay of CLKB ' to FF2/CK.
Further, several statistical values of the clock delay include maximum value, minimum value, average value and distributed area
Between.
It should be noted that choosing which statistical value (maximum value, minimum value, average value or the distributed area of clock delay
Between) reactionary slogan, anti-communist poster give full chip, need to be repeated trial using each statistical value, and determine according to the timing results obtained after trial
It is fixed which statistical value finally used, select timing results closest to the statistical value reactionary slogan, anti-communist poster of clock tree balance to full chip.Or
Rule of thumb, maximum value reactionary slogan, anti-communist poster is generally selected to full chip.The present invention is it is emphasised that only obtaining has timing inspection with top-level module
Clock delay of the register inside submodule, how global clock carried out according to the statistical value of clock delay as full chip
Tree balance can realize by timing budget method in the prior art, and the present invention is to this and with no restrictions.
As shown in figure 4, the clock delay of the CLKA ' selected to FF1/CK and CLKB ' to be arrived to the clock delay of FF2/CK
It is automatic by electric design automation (Electronics Design Automation, EDA) tool after reactionary slogan, anti-communist poster gives full chip
The clock delay for balancing CLKA to FF1/CK and CLKA to FF3/CK, can similarly obtain the clock tree balance between FF2 and FF4.
Those of ordinary skill in the art will appreciate that all or part of the steps in the above method can be instructed by program
Related hardware is completed, and described program can store in computer readable storage medium, such as read-only memory, disk or CD
Deng.Optionally, one or more integrated circuits also can be used to realize, accordingly in all or part of the steps of above-described embodiment
Ground, each module/unit in above-described embodiment can take the form of hardware realization, can also use the shape of software function module
Formula is realized.The present invention is not limited to the combinations of the hardware and software of any particular form.
The foregoing is only a preferred embodiment of the present invention, is not intended to restrict the invention, for the skill of this field
For art personnel, the invention may be variously modified and varied.All within the spirits and principles of the present invention, made any to repair
Change, equivalent replacement, improvement etc., should all be included in the protection scope of the present invention.
Claims (8)
1. a kind of clock tree synthesis method characterized by comprising
After submodule in full chip finishes clock tree balance, obtains and top-level module has the register of timing inspection in submodule
Internal clock delay, calculates several statistical values of the clock delay of acquisition；
Submodule chooses a statistical value reactionary slogan, anti-communist poster of clock delay to full chip, and full chip is instructed to carry out global clock tree balance.
2. clock tree synthesis method according to claim 1, which is characterized in that the acquisition and top-level module have timing inspection
Clock delay of the register looked into inside submodule include:
The submodule generates all timing paths relevant to port, and described and top layer mould is selected from the timing path
Block has clock delay of the register of timing inspection inside submodule.
3. clock tree synthesis method according to claim 1, which is characterized in that several statistical values of the clock delay
Including maximum value, minimum value, average value and distributed area.
4. clock tree synthesis method according to claim 1, which is characterized in that before the method further include:
The full chip is divided into several described submodules and a top-level module；
Each submodule individually carries out clock tree balance.
5. a kind of computer readable storage medium, which is characterized in that the computer-readable recording medium storage have one or
Multiple programs, one or more of programs can be executed by one or more processor, to perform the steps of
After submodule in full chip finishes clock tree balance, obtains and top-level module has the register of timing inspection in submodule
Internal clock delay, calculates several statistical values of the clock delay of acquisition；
Submodule chooses a statistical value reactionary slogan, anti-communist poster of clock delay to full chip, and full chip is instructed to carry out global clock tree balance.
6. computer readable storage medium according to claim 5, which is characterized in that the acquisition and top-level module are sometimes
Before the step of clock delay of the register of sequence inspection inside submodule, one or more of programs can also be described
One or more processor executes, to perform the steps of
The submodule generates all timing paths relevant to port, and described and top layer mould is selected from the timing path
Block has clock delay of the register of timing inspection inside submodule.
7. computer readable storage medium according to claim 5, which is characterized in that several systems of the clock delay
Evaluation includes maximum value, minimum value, average value and distributed area.
8. computer readable storage medium according to claim 5, which is characterized in that the submodule in the full chip is done
Before step after complete clock tree balance, one or more of programs can also be held by one or more of processors
Row, to perform the steps of
The full chip is divided into several described submodules and a top-level module；
Each submodule individually carries out clock tree balance.
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| CN110555269A (en) * | 2019-09-02 | 2019-12-10 | 天津飞腾信息技术有限公司 | Top-level clock tree structure of system on chip |
| CN110825210A (en) * | 2019-11-12 | 2020-02-21 | 天津飞腾信息技术有限公司 | Method, apparatus, device and medium for designing clock tree structure of system on chip |
| CN111046624A (en) * | 2019-12-17 | 2020-04-21 | 天津飞腾信息技术有限公司 | Method, device, equipment and medium for constructing chip module interface clock structure |
| CN111539176A (en) * | 2019-03-29 | 2020-08-14 | 成都海光集成电路设计有限公司 | Multi-instance time budget for integrated circuit design and fabrication |
| CN111753480A (en) * | 2020-07-01 | 2020-10-09 | 无锡中微亿芯有限公司 | Multi-die FPGA for implementing clock tree by using active silicon connection layer |
| CN111967212A (en) * | 2020-08-06 | 2020-11-20 | 广芯微电子（广州）股份有限公司 | Method, system and storage medium for hierarchical design chip timing sequence convergence |
| CN112331243A (en) * | 2020-11-26 | 2021-02-05 | 安徽省东科半导体有限公司 | Logic decoupling method of registers under same clock domain |
| CN113505562A (en) * | 2021-07-05 | 2021-10-15 | 广东工业大学 | Clock tree comprehensive optimal strategy prediction method, system and application |
| CN114818595A (en) * | 2022-06-24 | 2022-07-29 | 飞腾信息技术有限公司 | Chip module interface clock construction method and device, storage medium and electronic equipment |
| CN115470747A (en) * | 2022-09-29 | 2022-12-13 | 西安工程大学 | Clock tree synthesis method for realizing rapid time sequence convergence |
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| CN111967212A (en) * | 2020-08-06 | 2020-11-20 | 广芯微电子（广州）股份有限公司 | Method, system and storage medium for hierarchical design chip timing sequence convergence |
| CN111967212B (en) * | 2020-08-06 | 2021-05-18 | 广芯微电子（广州）股份有限公司 | Method, system and storage medium for hierarchical design chip timing sequence convergence |
| CN112331243B (en) * | 2020-11-26 | 2021-07-23 | 安徽省东科半导体有限公司 | Logic decoupling method of registers under same clock domain |
| CN112331243A (en) * | 2020-11-26 | 2021-02-05 | 安徽省东科半导体有限公司 | Logic decoupling method of registers under same clock domain |
| CN113505562A (en) * | 2021-07-05 | 2021-10-15 | 广东工业大学 | Clock tree comprehensive optimal strategy prediction method, system and application |
| CN114818595B (en) * | 2022-06-24 | 2022-09-13 | 飞腾信息技术有限公司 | Chip module interface clock construction method and device, storage medium and electronic equipment |
| CN114818595A (en) * | 2022-06-24 | 2022-07-29 | 飞腾信息技术有限公司 | Chip module interface clock construction method and device, storage medium and electronic equipment |
| CN115470747A (en) * | 2022-09-29 | 2022-12-13 | 西安工程大学 | Clock tree synthesis method for realizing rapid time sequence convergence |
| CN115470747B (en) * | 2022-09-29 | 2023-12-15 | 西安工程大学 | Clock tree synthesis method for realizing rapid convergence of time sequence |
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