CN113505562A - Clock tree comprehensive optimal strategy prediction method, system and application - Google Patents

Clock tree comprehensive optimal strategy prediction method, system and application Download PDF

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CN113505562A
CN113505562A CN202110759875.XA CN202110759875A CN113505562A CN 113505562 A CN113505562 A CN 113505562A CN 202110759875 A CN202110759875 A CN 202110759875A CN 113505562 A CN113505562 A CN 113505562A
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clock tree
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黄泽武
詹瑞典
熊晓明
蔡述庭
何柏声
梁润华
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Guangdong University of Technology
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Abstract

In order to solve the defects of the prior art, the invention provides a clock tree comprehensive optimal strategy prediction method, a system and application, wherein the method comprises the following steps: optimizing a clock tree of a chip to be used by utilizing a particle swarm optimization algorithm to obtain an optimal design scheme; recording a common design scheme aiming at the standby chip and design information data of the optimal design scheme to form a total design data set by acquiring a script; setting a neural network model, learning the total design data set by using the neural network model, training the neural network model, and obtaining a trained model; and predicting the comprehensive optimal strategy of the clock tree by utilizing the trained model. The invention establishes the prediction model of the clock tree comprehensive optimal strategy through the machine learning algorithm, can greatly shorten the design period of the chip, and simultaneously reduces the chip failure risk caused by the unsatisfactory clock tree comprehensive result.

Description

Clock tree comprehensive optimal strategy prediction method, system and application
Technical Field
The invention relates to the technical field of electronics, in particular to a clock tree comprehensive optimal strategy prediction method, a clock tree comprehensive optimal strategy prediction system, an electronic device and application.
Background
The method for generating clock tree codes commonly used at present comprises the following steps: establishing a clock structure information table, wherein the clock structure information table comprises at least one clock signal source representing a first stage and at least one clock generating unit cascaded with the clock signal source; acquiring clock structure information in a clock structure information table; the clock constraint file or the code of the clock tree is generated by applying the preset description rule of the clock generation unit according to the clock structure information, the description of the clock tree can be directly converted into the clock constraint file of the clock tree, the consistency of the document and the code is ensured, and the degree and the reliability of automation are improved.
However, the current clock tree code generation method needs to manually establish a clock structure information table; in the design of increasingly larger digital chips, the clock structure is increasingly complex, it obviously takes a very long time to establish a refined information table aiming at the complex clock structure, meanwhile, manual definition is not always the optimal solution of a clock tree, and a continuous optimization space exists.
Disclosure of Invention
In order to solve the defects of the prior art, the invention provides a clock tree comprehensive optimal strategy prediction method, a clock tree comprehensive optimal strategy prediction system and application, which are used for solving at least one technical problem in the background art.
The technical scheme adopted by the invention is as follows:
a clock tree comprehensive optimal strategy prediction method comprises the following steps:
optimizing a clock tree of a chip to be used by utilizing a particle swarm optimization algorithm to obtain an optimal design scheme;
recording a common design scheme aiming at the standby chip and design information data of the optimal design scheme to form a total design data set by acquiring a script;
setting a neural network model, learning the total design data set by using the neural network model, training the neural network model, and obtaining a trained model;
and predicting the comprehensive optimal strategy of the clock tree by utilizing the trained model.
The "learning the total design data set using the neural network model" includes:
utilizing data of the total design dataset as a dataset of a machine learning prediction model;
taking the design information data of the common design scheme as a feature vector; and taking the script of the optimal design scheme as label information to train the neural network model.
The "design information data" includes:
and designing one or more of timing sequence, clock tree and physical design information in the scheme.
The method for optimizing the clock tree of the chip to be used by utilizing the particle swarm optimization algorithm comprises the following steps of:
according to the requirement of a user, defining a particle as a certain constraint object in a clock tree or a combination of all constraints;
setting a fitness function, determining the number of particles, determining a learning factor, determining the value of an inertia weight and updating the speed and position of the particles;
and obtaining an optimal constraint solution by setting iteration times or optimizing exit conditions.
The step of setting a neural network model, learning the total design data set by using the neural network model, training the neural network model to obtain a trained model includes:
when the particle swarm optimization algorithm is used for optimizing the clock tree of the chip to be used, the obtained optimization constraint solution is used as label information of machine learning;
extracting data features before the clock tree is comprehensively optimized by using a data extraction script to serve as feature vectors of machine learning;
synthesizing the optimization constraint solution and the data characteristics into a machine learning data set, and dividing the machine learning data set into a training set, a testing set and a verification set;
training and outputting a model with optimal constraint prediction output by using the data set, setting a training algorithm and a model structure and using a supervised machine learning method;
and outputting an optimal machine learning prediction model.
The method for outputting the optimal machine learning prediction model comprises the following steps:
and adjusting the training algorithm according to the prediction accuracy until an ideal prediction accuracy is obtained, and finally outputting an optimal machine learning prediction model.
The "predicting the clock tree comprehensive optimal strategy by using the trained model" includes:
storing the total design data set in a specified location prior to making a prediction;
inputting the total design data set into the neural network model to obtain a predicted constraint value, and corresponding the content of the predicted constraint value to the content of a set constraint value;
combining the predicted constraint value with a set clock tree comprehensive script command to obtain a special clock tree comprehensive script;
reading the script before predicting the clock tree comprehensive optimal strategy, and carrying out constraint setting;
and predicting the clock tree comprehensive optimal strategy to obtain an optimal clock tree comprehensive result.
A clock tree integrated optimal strategy prediction system, comprising:
the particle swarm optimization module is used for optimizing the clock tree of the chip to be used by utilizing a particle swarm optimization algorithm to obtain an optimal design scheme;
the prediction model module is used for exchanging data with the particle swarm optimization module, recording design information data aiming at the common design scheme of the standby chip and the optimal design scheme to form a total design data set through collecting scripts, setting a neural network model, and training the neural network model to obtain a trained model;
and the optimal strategy prediction module exchanges data with the prediction model module and is used for predicting the clock tree comprehensive optimal strategy by utilizing the trained model.
An electronic device for clock tree comprehensive optimal strategy prediction, comprising: a storage medium and a processing unit; a storage medium for storing a computer program;
the processing unit performs data exchange with the storage medium, and is configured to execute the computer program through the processing unit when performing clock tree comprehensive optimal policy prediction, so as to perform the steps of the clock tree comprehensive optimal policy prediction method.
Use of a method as described above in the design of a digital chip.
The invention has the beneficial effects that:
the invention firstly utilizes the particle swarm optimization algorithm to optimize and explore the clock tree design of various chips, utilizes tcl to compile design information acquisition scripts on the basis of obtaining the optimal design, records the time sequence, the clock tree and the physical design information of various designs, and simultaneously records the optimization scripts. And then, a data set of a machine learning prediction model is made by using the recorded data, time sequence, clock tree and physical design information of various designs are respectively used as characteristic vectors, an optimized script is used as label information, and a neural network model is trained. Finally, by utilizing the model, the physical information of the design itself can be utilized in various clock tree comprehensive scenes, the clock tree comprehensive optimal strategy script can be rapidly predicted, and the design efficiency and the performance of the chip are greatly improved.
According to the invention, the prediction model of the clock tree comprehensive optimal strategy is established through the machine learning algorithm, so that the design period of the chip can be greatly shortened, and the chip failure risk caused by the unsatisfactory clock tree comprehensive result is reduced; meanwhile, an optimization object and a prediction script can be flexibly set according to the requirements of a user, and the optimization object and the prediction script can be used as an auxiliary tool for chip design and also can be used as a reference tool for generating a clock tree comprehensive script.
Drawings
FIG. 1 is an overall process of the present invention.
FIG. 2 is a flow chart of particle swarm optimization in the method of the present invention.
FIG. 3 is a flow chart of machine learning prediction model building.
FIG. 4 is a flow diagram of a predictive optimal policy constraint script.
Detailed Description
The present application is further described below with reference to the accompanying drawings.
The present invention provides an embodiment:
in order to solve the problems in the prior art, the clock tree comprehensive optimal strategy prediction method provided by the invention is divided into the following three parts, namely optimizing a clock tree by a time-dependent particle swarm algorithm, building a machine learning prediction model and performing prediction output, and as shown in fig. 1, the method specifically comprises the following steps:
1. the particle swarm optimization algorithm optimizes the clock tree, as shown in fig. 2:
a) firstly, defining the specific meaning of the particle, wherein in the design, the particle can be determined as a certain constraint object in the clock tree synthesis or the combination of all constraints according to the requirement of a user;
b) setting a fitness function, wherein the fitness function can be determined according to an optimization target of a user and can be an object of worst path allowance, total path allowance, clock delay, clock skew and the like;
c) determining the number of particles;
d) determining values of learning factors and inertial weights;
e) setting a velocity and position update function of a particle
Figure BDA0003148834650000061
Where v is the velocity of the particle, w is the inertial weight, c1 and c2 are two learning factors, r1 and r2 are random numbers; p is a radical ofi,jIs the individual optimum of each iteration particle swarm, pg,jIs globally optimal; x is the position of the particle, and the final solution.
f) Then, iteration times or optimization exit conditions are set, namely, after the optimization target reaches a certain value or the iteration times reaches, the iteration optimization exits, and therefore the optimal constraint solution is obtained;
g) and if the iteration exit condition is not reached, updating the position according to the formula in the step e, and continuing the iteration until the iteration exit condition is reached.
2. Constructing a machine learning prediction model, as shown in FIG. 3
a) Running the particle swarm optimization flow in the step 1 in a large number of designs to obtain a large number of optimization constraint solutions, wherein the solutions are used as label information of supervised machine learning;
b) compiling a data extraction script, extracting various characteristics of data before clock tree synthesis, such as time sequence and design information of the number of time sequence paths, the time sequence allowance of key paths, the number of clocks, the size of time sequence constraint and the like, wherein the information is used as a feature vector of supervised machine learning;
c) synthesizing the data extracted in a) and b) into a data set for supervised machine learning, and dividing the data set into a training set, a test set, a verification set and the like according to a proportion;
d) training and outputting a model with optimal constraint prediction output for subsequent use by using the data set, setting a training algorithm and a model structure and using a supervised machine learning method;
e) and adjusting the training algorithm according to the prediction accuracy until an ideal prediction accuracy is obtained, and finally outputting an optimal machine learning prediction model.
3. Optimal constraint prediction flow, as shown in FIG. 4
a) Before prediction, corresponding data needs to be extracted before clock tree synthesis according to the data determined in the step 2.b and stored in a specific file;
b) inputting the data extracted in the step a) into a prediction model output in the step 2.e, and calculating;
c) obtaining a predicted constraint value from the prediction model, wherein the content of the constraint value corresponds to the constraint value specified by the user in the step 2. a;
d) combining the predicted constraint value with a clock tree comprehensive specific script command to obtain a special clock tree comprehensive script, and storing the special clock tree comprehensive script as a tcl-format file;
e) and reading the script before clock tree synthesis, performing constraint setting, and performing clock tree synthesis to obtain an optimal clock tree synthesis result.
The method comprises the steps of firstly exploring the optimal design of a clock tree by using a particle swarm algorithm, then building a prediction model based on design information and a particle swarm optimization algorithm output result by using a machine learning algorithm, inputting the design information into the prediction model in integrated circuit layout and wiring software to the maximum extent, then obtaining a recommended clock tree comprehensive optimal strategy, generating a corresponding tcl command, and carrying out clock tree synthesis to obtain an optimal clock tree comprehensive result. Through actual test, the clock tree generated by the particle swarm optimization algorithm is utilized, the buffer on the clock path can be reduced by more than normal, the power consumption of the clock network can be greatly reduced, and the power consumption optimization of the chip is facilitated.
The invention also discloses a clock tree comprehensive optimal strategy prediction system, which comprises: the system comprises a particle swarm optimization module, a prediction model module and an optimal strategy prediction module; the particle swarm optimization module is used for optimizing a clock tree of the chip to be used by utilizing a particle swarm optimization algorithm to obtain an optimal design scheme; the prediction model module and the particle swarm optimization module exchange data and are used for recording a general design scheme aiming at the standby chip and design information data of the optimal design scheme to form a total design data set through collecting a script, setting a neural network model, training the neural network model and obtaining a trained model; and the optimal strategy prediction module exchanges data with the prediction model module and is used for predicting the clock tree comprehensive optimal strategy by utilizing the trained model.
The invention also discloses an electronic device, comprising: a storage medium and a processing unit; a storage medium for storing a computer program; the processing unit performs data exchange with the storage medium, and is configured to execute the computer program through the processing unit when performing the clock tree comprehensive optimal policy prediction, so as to perform the steps of the clock tree comprehensive optimal policy prediction method.
In the electronic device, the storage medium is preferably a storage device such as a mobile hard disk, a solid state disk, or a usb disk; a processing unit, preferably a CPU, for exchanging data with the storage medium, and executing the computer program through the processing unit when performing the clock tree comprehensive optimal policy prediction, so as to perform the steps of the clock tree comprehensive optimal policy prediction method described above.
The CPU described above can execute various appropriate actions and processes according to a program stored in a storage medium. The electronic device also includes peripherals including an input part for a keyboard, a mouse, etc., and an output part such as a Cathode Ray Tube (CRT), a Liquid Crystal Display (LCD), etc., and a speaker, etc.; in particular, according to the disclosed embodiments of the invention, the processes as described in any of FIGS. 1-4 may be implemented as computer software programs.
An embodiment provided by the present invention comprises a computer program product comprising a computer program embodied on a computer readable medium, the computer program comprising program code for performing a method as illustrated in the flow chart of any one of figures 1-4. The computer program may be downloaded and installed from a network. The computer program, when executed by the CPU, performs the above-described functions defined in the system of the present invention.
The present invention also provides a computer-readable storage medium having a computer program stored therein; the computer program, when running, performs the clock tree synthesis optimal strategy prediction method steps as described above. In the present invention, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.
In the present invention, however, a computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take many forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wire, fiber optic cable, RF, etc., or any suitable combination of the foregoing.
The method provided by the invention provides a clock tree comprehensive optimal strategy prediction method and system based on a particle swarm optimization algorithm and a machine learning algorithm, wherein the clock tree is optimized and explored through the particle swarm optimization algorithm, and the machine learning algorithm is utilized for optimization prediction to generate an optimal constraint script; the optimal constraint script content can be specified by a user to meet the specific requirements of the user; moreover, the particle swarm optimization can be replaced by other optimization algorithms for optimization exploration.
The above disclosure is only a few specific implementation scenarios of the present invention, however, the present invention is not limited thereto, and any variations that can be made by those skilled in the art are intended to fall within the scope of the present invention. The above-mentioned invention numbers are merely for description and do not represent the merits of the implementation scenarios.

Claims (10)

1. A clock tree comprehensive optimal strategy prediction method is characterized by comprising the following steps:
optimizing a clock tree of a chip to be used by utilizing a particle swarm optimization algorithm to obtain an optimal design scheme;
recording a common design scheme aiming at the standby chip and design information data of the optimal design scheme to form a total design data set by acquiring a script;
setting a neural network model, learning the total design data set by using the neural network model, training the neural network model, and obtaining a trained model;
and predicting the comprehensive optimal strategy of the clock tree by utilizing the trained model.
2. The method for predicting clock tree comprehensive optimal strategy according to claim 1, wherein the learning the total design data set by the neural network model includes:
utilizing data of the total design dataset as a dataset of a machine learning prediction model;
taking the design information data of the common design scheme as a feature vector; and taking the script of the optimal design scheme as label information to train the neural network model.
3. The clock tree comprehensive optimal strategy prediction method according to claim 1, wherein the "design information data" comprises:
and designing one or more of timing sequence, clock tree and physical design information in the scheme.
4. The method for predicting the clock tree comprehensive optimal strategy according to claim 1, wherein the optimizing the clock tree of the chip to be used by using the particle swarm optimization algorithm comprises:
according to the requirement of a user, defining a particle as a certain constraint object in a clock tree or a combination of all constraints;
setting a fitness function, determining the number of particles, determining a learning factor, determining the value of an inertia weight and updating the speed and position of the particles;
and obtaining an optimal constraint solution by setting iteration times or optimizing exit conditions.
5. The method for predicting the clock tree comprehensive optimal strategy according to claim 1, wherein the step of setting a neural network model, learning the total design data set by using the neural network model, training the neural network model, and obtaining a trained model comprises the steps of:
when the particle swarm optimization algorithm is used for optimizing the clock tree of the chip to be used, the obtained optimization constraint solution is used as label information of machine learning;
extracting data features before the clock tree is comprehensively optimized by using a data extraction script to serve as feature vectors of machine learning;
synthesizing the optimization constraint solution and the data characteristics into a machine learning data set, and dividing the machine learning data set into a training set, a testing set and a verification set;
training and outputting a model with optimal constraint prediction output by using the data set, setting a training algorithm and a model structure and using a supervised machine learning method;
and outputting an optimal machine learning prediction model.
6. The clock tree comprehensive optimal strategy prediction method according to claim 5, wherein the outputting an optimal machine learning prediction model comprises:
and adjusting the training algorithm according to the prediction accuracy until an ideal prediction accuracy is obtained, and finally outputting an optimal machine learning prediction model.
7. The method for predicting the clock tree integrated optimal strategy according to claim 1, wherein the "predicting the clock tree integrated optimal strategy by using the trained model" comprises:
storing the total design data set in a specified location prior to making a prediction;
inputting the total design data set into the neural network model to obtain a predicted constraint value, and corresponding the content of the predicted constraint value to the content of a set constraint value;
combining the predicted constraint value with a set clock tree comprehensive script command to obtain a special clock tree comprehensive script;
reading the script before predicting the clock tree comprehensive optimal strategy, and carrying out constraint setting;
and predicting the clock tree comprehensive optimal strategy to obtain an optimal clock tree comprehensive result.
8. A clock tree integrated optimal strategy prediction system, comprising:
the particle swarm optimization module is used for optimizing the clock tree of the chip to be used by utilizing a particle swarm optimization algorithm to obtain an optimal design scheme;
the prediction model module is used for exchanging data with the particle swarm optimization module, recording design information data aiming at the common design scheme of the standby chip and the optimal design scheme to form a total design data set through collecting scripts, setting a neural network model, and training the neural network model to obtain a trained model;
and the optimal strategy prediction module exchanges data with the prediction model module and is used for predicting the clock tree comprehensive optimal strategy by utilizing the trained model.
9. An electronic device for clock tree comprehensive optimal strategy prediction, comprising: a storage medium and a processing unit; a storage medium for storing a computer program;
the processing unit exchanges data with the storage medium, and is configured to execute the computer program through the processing unit when performing clock tree comprehensive optimal policy prediction, so as to perform the steps of the clock tree comprehensive optimal policy prediction method according to any one of claims 1 to 7.
10. Use of the method of any of claims 1 to 7 in digital chip design.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113962174A (en) * 2021-12-21 2022-01-21 佛山芯珠微电子有限公司 Software and hardware compatible method based on information security chip of Internet of things
CN117195821A (en) * 2023-11-08 2023-12-08 深圳鸿芯微纳技术有限公司 Clock tree synthesis method, electronic equipment and storage medium

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108984806A (en) * 2017-05-31 2018-12-11 深圳市中兴微电子技术有限公司 A kind of clock tree synthesis method and computer readable storage medium
US20200104457A1 (en) * 2018-09-28 2020-04-02 Taiwan Semiconductor Manufacturing Co., Ltd. Design rule check violation prediction systems and methods
CN111241778A (en) * 2020-01-06 2020-06-05 武汉理工大学 FPGA automatic parameter adjustment optimization method and system based on machine learning
CN112163394A (en) * 2020-09-28 2021-01-01 海光信息技术股份有限公司 CPU chip design method and device and electronic equipment
CN112257378A (en) * 2020-10-30 2021-01-22 东南大学 Method for realizing robust clock tree comprehensive algorithm aiming at near threshold
US10963618B1 (en) * 2020-01-06 2021-03-30 Cadence Design Systems, Ine. Multi-dimension clock gate design in clock tree synthesis

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108984806A (en) * 2017-05-31 2018-12-11 深圳市中兴微电子技术有限公司 A kind of clock tree synthesis method and computer readable storage medium
US20200104457A1 (en) * 2018-09-28 2020-04-02 Taiwan Semiconductor Manufacturing Co., Ltd. Design rule check violation prediction systems and methods
CN111241778A (en) * 2020-01-06 2020-06-05 武汉理工大学 FPGA automatic parameter adjustment optimization method and system based on machine learning
US10963618B1 (en) * 2020-01-06 2021-03-30 Cadence Design Systems, Ine. Multi-dimension clock gate design in clock tree synthesis
CN112163394A (en) * 2020-09-28 2021-01-01 海光信息技术股份有限公司 CPU chip design method and device and electronic equipment
CN112257378A (en) * 2020-10-30 2021-01-22 东南大学 Method for realizing robust clock tree comprehensive algorithm aiming at near threshold

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
SUNWHA KOH等: "Pre-Layout Clock Tree Estimation and Optimization Using Artificial Neural Network", 《ISLPED \'20: PROCEEDINGS OF THE ACM/IEEE INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN》, 31 August 2020 (2020-08-31), pages 193 - 196 *
YI-CHEN LU等: "GAN-CTS: A Generative Adversarial Framework for Clock Tree Prediction and Optimization", 《2019 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD)》, 30 November 2019 (2019-11-30), pages 1 - 8, XP033678130 *
江立强等: "一种有效的多时钟网络时钟树综合方案", 《计算机与数字工程》, no. 11, 20 October 2006 (2006-10-20), pages 91 - 93 *
郑丹丹等: "基于粒子群优化算法的有用时钟偏差规划", 《浙江大学学报(工学版)》, no. 4, 15 April 2010 (2010-04-15), pages 665 - 669 *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113962174A (en) * 2021-12-21 2022-01-21 佛山芯珠微电子有限公司 Software and hardware compatible method based on information security chip of Internet of things
CN117195821A (en) * 2023-11-08 2023-12-08 深圳鸿芯微纳技术有限公司 Clock tree synthesis method, electronic equipment and storage medium
CN117195821B (en) * 2023-11-08 2024-02-23 深圳鸿芯微纳技术有限公司 Clock tree synthesis method, electronic equipment and storage medium

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