CN117195821B

CN117195821B - Clock tree synthesis method, electronic equipment and storage medium

Info

Publication number: CN117195821B
Application number: CN202311474975.3A
Authority: CN
Inventors: 郭毅勃; 林明豪; 刘丽红; 王磊
Original assignee: Shenzhen Hongxin Micro Nano Technology Co ltd
Current assignee: Shenzhen Hongxin Micro Nano Technology Co ltd
Priority date: 2023-11-08
Filing date: 2023-11-08
Publication date: 2024-02-23
Anticipated expiration: 2043-11-08
Also published as: CN117195821A

Abstract

The invention provides a clock tree synthesis method, electronic equipment and a storage medium, and relates to the technical field of circuit design. The clock tree synthesis method comprises the following steps: acquiring data of a to-be-processed clock tree, wherein the data of the to-be-processed clock tree are used for representing the structure of the to-be-processed clock tree; processing the data of the clock tree to be processed by adopting a target network model to obtain a first adjustment action aiming at the clock tree to be processed; adjusting the structure of the clock tree to be processed according to the first adjusting action to obtain a first clock tree; and if the first clock tree meets the preset termination condition, taking the first clock tree as a final clock tree. The method has the advantages that a complex clock structure in a circuit is not required to be manually disassembled, the data of the clock tree to be processed is processed by adopting a trained target network model, the first adjustment action is output efficiently, and the efficient adjustment of the clock tree to be processed can be realized according to the first adjustment action, so that the comprehensive efficiency of the clock tree can be improved.

Description

Clock tree synthesis method, electronic equipment and storage medium

Technical Field

The present invention relates to the field of circuit design technologies, and in particular, to a clock tree synthesis method, an electronic device, and a storage medium.

Background

In digital integrated circuit design, the clock signal coordinates and synchronizes the actions of each standard cell in the digital system, which is the reference for data transmission. As the scale of integrated circuits is gradually increased, the requirements for integrated circuit functions and delay time information are also gradually increased, and for high-frequency large-scale circuits, it is becoming more and more challenging to meet the time requirements, and this work is mainly accomplished through clock tree synthesis.

The design scale of the existing integrated circuit is gradually complex, the existing integrated circuit is more biased to a complex hierarchical design circuit, the difference between modules is large, and aiming at the complex design circuit, the internal clock structure needs to be manually disassembled, so that the operation calculation time is too long.

In the related art, the problem of inefficiency exists in the process of clock tree synthesis.

Disclosure of Invention

The present invention is directed to a clock tree synthesis method, an electronic device, and a storage medium, which address the above-mentioned shortcomings of the prior art.

In order to achieve the above purpose, the technical scheme adopted by the embodiment of the invention is as follows:

in a first aspect, an embodiment of the present invention provides a clock tree synthesis method, where the method includes:

Acquiring data of a clock tree to be processed, wherein the data of the clock tree to be processed are used for representing the structure of the clock tree to be processed;

processing the data of the clock tree to be processed by adopting a target network model to obtain a first adjustment action aiming at the clock tree to be processed;

adjusting the structure of the clock tree to be processed according to the first adjusting action to obtain a first clock tree;

and if the first clock tree meets the preset termination condition, taking the first clock tree as a final clock tree.

Optionally, the method further comprises:

if the first clock tree does not meet the preset termination condition, acquiring data of the first clock tree;

and processing the data of the first clock tree by adopting the target network model to obtain a second adjustment action for the first clock tree, adjusting the structure of the first clock tree according to the second adjustment action until the obtained second clock tree meets the preset termination condition, and taking the second clock tree as a final clock tree.

Optionally, the target network model includes: the graph network model and the strategy network model are used for processing the data of the clock tree to be processed by adopting a target network model to obtain a first adjustment action aiming at the clock tree to be processed, and the method comprises the following steps:

Carrying out feature extraction on the data of the clock tree to be processed by adopting the graph network model to obtain a clock tree feature vector;

processing according to the clock tree feature vector and preset global metadata by adopting the strategy network model to obtain probability distribution aiming at a plurality of preset adjustment actions, wherein the preset global metadata are used for representing the global state of the clock tree to be processed;

and determining a first adjustment action of the clock tree to be processed from the preset adjustment actions according to probability distribution of the preset adjustment actions.

Optionally, the plurality of preset adjustment actions includes at least two of: the method comprises the steps of clock tree traversing direction, advancing action for selecting next node, clustering action for clustering child nodes under a current node and adding new nodes, adding action for inserting a buffer between the current node and a corresponding father node, deleting the current node and setting the current node as the next node according to the traversing direction, amplifying action for replacing the current node with a strong driving device, shrinking action for replacing the current node with a weak driving device, roundabout action for increasing the line length between the current node and the father node, and roundabout action for bypassing the father node of the current node and connecting the ancestor node.

Optionally, the target network model is obtained by training by adopting the following method:

training an initial graph network model according to the data of the sample clock tree to obtain the graph network model;

adopting the graph network model to respectively process the data of the sample clock tree to obtain a sample clock tree feature vector;

and training an initial strategy network model and an initial value network model according to the sample clock tree feature vector and sample global metadata of the sample clock tree until the strengthening training termination condition is met, so as to obtain the strategy network model.

Optionally, training model parameters of an initial policy network model and an initial value network model according to the feature vector of the sample clock tree and the sample global metadata of the sample clock tree until a training termination condition is satisfied, to obtain the policy network model, including:

processing the sample clock tree feature vector and preset sample global metadata by adopting the initial strategy network model, and outputting a sample adjustment action;

processing the sample clock tree feature vector and preset sample global metadata by adopting the initial value network model, and outputting monovalent value information;

Adjusting the structure of the sample clock tree according to the sample adjustment action to obtain an adjusted sample clock tree, and updating model parameters of the initial strategy network model according to the monovalent value information;

processing the adjusted sample clock tree by adopting the updated initial strategy network model, and outputting the next sample adjustment action until the obtained target sample clock tree meets the preset termination condition;

and updating the updated model parameters of the initial strategy network model and the initial value network model according to index data corresponding to the data of the target sample clock tree until the reinforcement training termination condition is met, so as to obtain the strategy network model.

Optionally, the training the initial graph network model according to the data of the sample clock tree to obtain the graph network model includes:

adopting an initial graph network model, and processing according to the data of the sample clock tree and the corresponding sample rewards to obtain the predicted rewards of the sample clock tree;

and updating model parameters of the initial graph network model according to the predicted reward value and the sample reward value until migration training termination conditions are met, so as to obtain the graph network model.

Optionally, before the first clock tree is used as the final clock tree if the first clock tree meets the preset termination condition, the method further includes:

judging whether the state of the first clock tree is a preset state or not, or whether the adjustment times from the clock tree to be processed to the first clock tree are larger than or equal to preset adjustment times or not;

if the state of the first clock tree is the preset state, or the adjustment times are greater than or equal to the preset adjustment times, determining that the first clock tree meets the preset termination condition;

and if the state of the first clock tree is not the preset state or the adjustment times are smaller than the preset adjustment times, determining that the first clock tree does not meet the preset termination condition.

In a second aspect, an embodiment of the present invention further provides a clock tree synthesis apparatus, where the apparatus includes:

the first acquisition module is used for acquiring data of a clock tree to be processed, wherein the data of the clock tree to be processed are used for representing the structure of the clock tree to be processed;

the first processing module is used for processing the data of the clock tree to be processed by adopting a target network model to obtain a first adjustment action aiming at the clock tree to be processed;

The adjusting module is used for adjusting the structure of the clock tree to be processed according to the first adjusting action to obtain a first clock tree; and if the first clock tree meets the preset termination condition, taking the first clock tree as a final clock tree.

Optionally, the apparatus further includes:

the second acquisition module is used for acquiring the data of the first clock tree if the first clock tree does not meet the preset termination condition;

and the second processing module is used for processing the data of the first clock tree by adopting the target network model to obtain a second adjustment action for the first clock tree, adjusting the structure of the first clock tree according to the second adjustment action until the obtained second clock tree meets the preset termination condition, and taking the second clock tree as a final clock tree.

Optionally, the target network model includes: the first processing module is specifically configured to perform feature extraction on the data of the clock tree to be processed by using the graph network model to obtain a clock tree feature vector; processing according to the clock tree feature vector and preset global metadata by adopting the strategy network model to obtain probability distribution aiming at a plurality of preset adjustment actions, wherein the preset global metadata are used for representing the global state of the clock tree to be processed; and determining a first adjustment action of the clock tree to be processed from the preset adjustment actions according to probability distribution of the preset adjustment actions.

Optionally, the target network model is obtained by training the following devices:

the first training module is used for training the initial graph network model according to the data of the sample clock tree to obtain the graph network model;

the third processing module is used for respectively processing the data of the sample clock tree by adopting the graph network model to obtain a sample clock tree feature vector;

and the second training module is used for training the initial strategy network model and the initial value network model according to the characteristic vector of the sample clock tree and the sample global metadata of the sample clock tree until the intensive training termination condition is met, so as to obtain the strategy network model.

Optionally, the second training module is specifically configured to process the feature vector of the sample clock tree and preset sample global metadata by using the initial policy network model, and output a sample adjustment action; processing the sample clock tree feature vector and preset sample global metadata by adopting the initial value network model, and outputting monovalent value information; adjusting the structure of the sample clock tree according to the sample adjustment action to obtain an adjusted sample clock tree, and updating model parameters of the initial strategy network model according to the monovalent value information; processing the adjusted sample clock tree by adopting the updated initial strategy network model, and outputting the next sample adjustment action until the obtained target sample clock tree meets the preset termination condition; and updating the updated model parameters of the initial strategy network model and the initial value network model according to index data corresponding to the data of the target sample clock tree until the reinforcement training termination condition is met, so as to obtain the strategy network model.

Optionally, the first training module is specifically configured to process, by using an initial graph network model, according to the data of the sample clock tree and the corresponding sample reward value, to obtain a predicted reward value of the sample clock tree; and updating model parameters of the initial graph network model according to the predicted reward value and the sample reward value until migration training termination conditions are met, so as to obtain the graph network model.

Optionally, the apparatus further includes:

the judging module is used for judging whether the state of the first clock tree is a preset state or not, or whether the adjustment times from the clock tree to be processed to the first clock tree are larger than or equal to preset adjustment times or not;

the determining module is configured to determine that the first clock tree meets the preset termination condition if the state of the first clock tree is the preset state, or the adjustment frequency is greater than or equal to the preset adjustment frequency; and if the state of the first clock tree is not the preset state or the adjustment times are smaller than the preset adjustment times, determining that the first clock tree does not meet the preset termination condition.

In a third aspect, an embodiment of the present invention further provides an electronic device, including: a memory storing a computer program executable by the processor, and a processor implementing the clock tree synthesis method of any one of the first aspects when the processor executes the computer program.

In a fourth aspect, an embodiment of the present invention further provides a computer readable storage medium, where a computer program is stored, where the computer program is read and executed to implement the clock tree synthesis method according to any one of the first aspect.

The beneficial effects of the invention are as follows: the embodiment of the invention provides a clock tree synthesis method, which comprises the following steps: acquiring data of a to-be-processed clock tree, wherein the data of the to-be-processed clock tree are used for representing the structure of the to-be-processed clock tree; processing the data of the clock tree to be processed by adopting a target network model to obtain a first adjustment action aiming at the clock tree to be processed; adjusting the structure of the clock tree to be processed according to the first adjusting action to obtain a first clock tree; and if the first clock tree meets the preset termination condition, taking the first clock tree as a final clock tree. The method has the advantages that a complex clock structure in a circuit is not required to be manually disassembled, the data of the clock tree to be processed is processed by adopting a trained target network model, the first adjustment action is output efficiently, and the efficient adjustment of the clock tree to be processed can be realized according to the first adjustment action, so that the comprehensive efficiency of the clock tree can be improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a flowchart illustrating a clock tree synthesis method according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a clock tree according to an embodiment of the present invention;

FIG. 3 is a second flow chart of a clock tree synthesis method according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a state change of a clock tree according to an embodiment of the present invention;

fig. 5 is a flowchart of a clock tree synthesis method according to an embodiment of the present application;

fig. 6 is a schematic structural diagram of a target network model according to an embodiment of the present application;

fig. 7a and fig. 7b are schematic diagrams of a clock tree traversal direction according to an embodiment of the present application;

FIG. 8 is a schematic diagram of a forward motion provided in an embodiment of the present application;

FIG. 9 is a schematic diagram of a binary cluster action according to an embodiment of the present disclosure;

FIG. 10 is a schematic diagram of an adding action provided in an embodiment of the present application;

FIG. 11 is a schematic diagram of a deletion action provided in an embodiment of the present application;

FIG. 12 is a schematic diagram of an amplifying action provided in an embodiment of the present application;

FIG. 13 is a schematic diagram of a zoom-out action according to an embodiment of the present disclosure;

FIG. 14 is a schematic diagram of a detour action according to an embodiment of the present disclosure;

FIG. 15 is a schematic diagram of a bypass action according to an embodiment of the present application;

fig. 16 is a flowchart of a clock tree synthesis method according to an embodiment of the present application;

FIG. 17 is a schematic diagram of a connection structure of a graph network model, an initial policy network model, and an initial value network model according to an embodiment of the present application;

fig. 18 is a flowchart fifth of a clock tree synthesis method according to an embodiment of the present application;

fig. 19 is a flowchart sixth of a clock tree synthesis method provided in an embodiment of the present application;

fig. 20 is a schematic structural diagram of a sensing network according to an embodiment of the present application;

fig. 21 is a flow chart seventh of a clock tree synthesis method provided in an embodiment of the present application;

fig. 22 is a schematic structural diagram of a clock tree synthesis device according to an embodiment of the present application;

fig. 23 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention.

Thus, the following detailed description of the embodiments of the present application, as provided in the accompanying drawings, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.

In the description of the present application, it should be noted that, if the terms "upper", "lower", and the like indicate an azimuth or a positional relationship based on the azimuth or the positional relationship shown in the drawings, or an azimuth or the positional relationship that is commonly put when the product of the application is used, it is merely for convenience of description and simplification of the description, and does not indicate or imply that the apparatus or element to be referred to must have a specific azimuth, be configured and operated in a specific azimuth, and therefore should not be construed as limiting the present application.

Furthermore, the terms first, second and the like in the description and in the claims and in the above-described figures, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

It should be noted that, without conflict, features in embodiments of the present application may be combined with each other.

The embodiment of the application provides a clock tree synthesis method, which is applied to electronic equipment, wherein the electronic equipment is terminal equipment or a server, and the terminal equipment can be any one of the following: desktop computers, notebook computers, tablet computers, smart phones, and the like.

The following explains a clock tree synthesis method provided in the embodiment of the present application.

Fig. 1 is a schematic flow chart of a clock tree synthesis method according to an embodiment of the present invention, as shown in fig. 1, the method may include:

s101, acquiring data of a clock tree to be processed.

The data of the clock tree to be processed is used for representing the structure of the clock tree to be processed.

In some embodiments, the structure of the clock tree to be processed is obtained, the structure of the clock tree to be processed may be represented by a structure of a directed acyclic graph, and the structure of the clock tree to be processed is converted into a graph node attribute vector and an adjacency matrix of connection relations between graph nodes connected in series, so as to obtain data of the clock tree to be processed, where the graph node attribute vector stores indexes of nodes or node connection lines.

In the embodiment of the application, the following manner is adopted to obtain the index of the node or the node connection:

line length of current node: the center of the surrounding rectangle formed by all the subsequent nodes is calculated first, and the current line length is defined as the distance from the current node to the center. Load of the current node: the sum of the load of the current node line length and the load of the subsequent node. The load coefficients of the different types of subsequent nodes are different, and the total load of the subsequent nodes is multiplied by the respective load coefficients and the quantity. Load types include capacitive and resistive loads. Signal transition time of current node: the index is calculated by taking the signal transition time of the precursor node and the load of the current node as inputs. Current node signal transition time violations: the difference between the current node signal transition time and the maximum signal transition time. Delay propagated to the current node: the capacitive and resistive loads of the current node and the subsequent nodes are known to calculate the delay from the clock input to the current node using the delay. Maximum deflection: the difference between the maximum delay and the minimum delay of the leaf node. Total transition time violations: the sum of all node transition time violations. Bus length: the sum of the line lengths stored by all nodes. Total number of driving units of each type: the number of drive units inserted by the clock tree characterizes the consumed area resources.

Fig. 2 is a schematic diagram of a clock tree according to an embodiment of the present invention, where, as shown in fig. 2, the diagram of the clock tree includes: the root node of the tree represents a clock source, and the leaf node represents a terminal of a clock such as a register; the intermediate node represents a driving device such as a buffer, a gate control unit and the like, the edge of the graph is used as a connection line of a clock tree, and the signal is transmitted from the clock input to the terminal of the clock through the clock connection line as a medium.

S102, processing data of the clock tree to be processed by adopting a target network model to obtain a first adjustment action for the clock tree to be processed.

The target network model is a model trained in advance according to data of a sample clock tree.

In the embodiment of the application, data of a clock tree to be processed is input into a target network model, the target network model processes the data of the clock tree to be processed, probability distribution aiming at a plurality of preset adjustment actions is output, and a preset adjustment action with highest probability is determined from the probability distribution of the plurality of preset adjustment actions to be used as a first adjustment action.

S103, adjusting the structure of the clock tree to be processed according to the first adjusting action to obtain a first clock tree.

S104, if the first clock tree meets the preset termination condition, the first clock tree is used as a final clock tree.

Wherein, since the structure of the to-be-processed clock tree and the structure of the first clock tree are different, the state of the to-be-processed clock tree and the state of the first clock tree are also different, the state of the to-be-processed clock tree may be represented as St, and the state of the first clock tree may be represented as st+1.

In some embodiments, the structure of the clock tree to be processed is adjusted according to the first adjustment action to obtain a first clock tree, whether the first clock tree meets the preset termination condition is judged, if the first clock tree meets the preset termination condition, the first clock tree is used as a final clock tree, and if the first clock tree does not meet the preset termination condition, the first clock tree needs to be continuously adjusted until the final clock tree meets the preset termination condition.

In the embodiment of the application, the final clock tree comprehensive result can ensure that the key time sequence requirements can be met under the conditions of provided process, voltage and temperature, so that the functions, performance and stability of the digital integrated circuit can be improved.

In summary, an embodiment of the present invention provides a clock tree synthesis method, including: acquiring data of a to-be-processed clock tree, wherein the data of the to-be-processed clock tree are used for representing the structure of the to-be-processed clock tree; processing the data of the clock tree to be processed by adopting a target network model to obtain a first adjustment action aiming at the clock tree to be processed; adjusting the structure of the clock tree to be processed according to the first adjusting action to obtain a first clock tree; and if the first clock tree meets the preset termination condition, taking the first clock tree as a final clock tree. The method has the advantages that a complex clock structure in a circuit is not required to be manually disassembled, the data of the clock tree to be processed is processed by adopting a trained target network model, the first adjustment action is output efficiently, and the efficient adjustment of the clock tree to be processed can be realized according to the first adjustment action, so that the comprehensive efficiency of the clock tree can be improved.

Optionally, fig. 3 is a second flow chart of a clock tree synthesis method according to an embodiment of the present invention, as shown in fig. 3, where the method may further include:

s201, if the first clock tree does not meet the preset termination condition, acquiring the data of the first clock tree.

If the first clock tree does not meet the preset termination condition, the data of the first clock tree is obtained according to the structure of the first clock tree, wherein the method is similar to the method for obtaining the data of the to-be-processed clock tree according to the structure of the to-be-processed clock tree, and is not repeated here.

S202, processing data of the first clock tree by adopting a target network model to obtain a second adjustment action for the first clock tree, adjusting the structure of the first clock tree according to the second adjustment action until the obtained second clock tree meets a preset termination condition, and taking the second clock tree as a final clock tree.

In some embodiments, data of the first clock tree is input into a target network model, the target network model processes the data of the first clock tree, probability distribution of a plurality of preset adjustment actions is output, and a preset adjustment action with highest probability is determined from the probability distribution of the plurality of preset adjustment actions to be used as a second adjustment action; and adjusting the structure of the first clock tree according to the second adjusting action to obtain a second clock tree, and taking the second clock tree as a final clock tree if the second clock tree meets the preset termination condition.

And if the second clock tree does not meet the preset termination condition, inputting the data of the second clock tree into the target network model, and repeatedly executing the process until the final clock tree meets the preset termination condition.

Alternatively, t adjustment actions may be determined sequentially using the target network model.

Fig. 4 is a schematic diagram of a state change of a clock tree according to an embodiment of the present invention, as shown in fig. 4, S0 represents a state of a clock tree to be processed (0 th clock tree), a first adjustment action is adopted to adjust a structure of the clock tree to be processed, so as to obtain a first clock tree (1 st clock tree), and S1 represents the state of the first clock tree; and adjusting the structure of the first clock tree by adopting a second adjusting action to obtain a second clock tree (2 nd clock tree), wherein S2 represents the state of the second clock tree, and the like, adjusting the structure of the t-1 St clock tree by adopting a t adjusting action to obtain a t clock tree, and St represents the state of the t clock tree.

Optionally, the target network model includes: graph network model and policy network model.

Fig. 5 is a flowchart third of a clock tree synthesis method provided in the embodiment of the present application, as shown in fig. 5, a process for processing data of a clock tree to be processed by using a target network model in S102 to obtain a first adjustment action for the clock tree to be processed may include:

S301, carrying out feature extraction on data of a clock tree to be processed by adopting a graph network model to obtain a clock tree feature vector.

The method comprises the steps of inputting data of a clock tree to be processed into a graph network model, extracting features of the data of the clock tree to be processed by the graph network model, and outputting a clock tree feature vector.

Fig. 6 is a schematic structural diagram of a target network model according to an embodiment of the present application, where, as shown in fig. 6, the target network model includes: the graph network model comprises the following components: a plurality of sets of subnetworks and GAT (Graph Attention Networks, schematic illustration network) layers connected in sequence, each set of subnetworks comprising: and the GAT layers and TopKPooling layers are sequentially connected, and the data of the clock tree to be processed is input into the GAT layers in the first group of subnetworks in the graph network model. Alternatively, the number of GAT layers in the graph network model may be a preset number, and in an example, the preset number may be 4, which may, of course, be selected according to actual requirements, which is not specifically limited in the embodiment of the present application.

The to-be-processed clock tree is a clock tree composed of N nodes, the GAT layer is composed of 8 attention headers with the length of 64, and a 512 XN-dimensional matrix can be obtained after the processing of the GAT layer. And extracting global average and maximum pooling vectors from the matrix by one GAT layer in each graph network model, summing the global average and maximum pooling vectors output by each GAT layer, and outputting the clock tree feature vectors.

It should be noted that, the topepolling layer in the first group of subnetworks may further perform K header pooling operation with parameters of 0.8 on the 512×n-dimensional matrix output by the GAT layer, that is, retain 80% of relatively important node information as input of the next GAT layer.

Of course, other graph neural networks may be used instead of the GAT layer, for example, GCN (Graph Convolutional Network, graph convolution network) or graph sage (Graph SAmple and aggreGatE, a graph-based inductive learning method); instead of the toppkpooling layer, other Pooling layers may be used, such as SAG Pooling (Self-Attention Pooling).

S302, processing is carried out according to the clock tree feature vector and the preset global metadata by adopting a strategy network model, and probability distribution aiming at a plurality of preset adjustment actions is obtained. The preset global metadata are used for representing the global state of the clock tree to be processed.

The method comprises the steps of obtaining preset global metadata, inputting the global metadata into a first full-connection layer, and outputting the processed global metadata by a feedforward network by the first full-connection layer, and inputting a clock tree feature vector into the feedforward network as shown in fig. 6; the feedforward network connects the processed global metadata with the clock tree feature vector to obtain clock tree feature data; the feed forward network inputs the clock tree feature data into the policy network model.

In addition, as shown in fig. 6, the action metadata is input into the second full connection layer, and the second full connection layer may output the processed action metadata, and input the processed action metadata into the policy network model, and the policy network model may output probability distributions of a plurality of preset adjustment actions.

It is noted that the global metadata records a vector of global states of the clock tree to be processed, such as canvas size, maximum fan-out number, current graph node number, etc., and is the same for the same clock tree to be processed no matter how many times the adjustment actions are performed. The action raw data records the traversing direction, the number of continuous actions allowed by the current node, the number of actions already executed, and the like.

S303, determining a first adjustment action of the clock tree to be processed from the plurality of preset adjustment actions according to probability distribution of the plurality of preset adjustment actions.

In some embodiments, as shown in fig. 6, probability distributions of a plurality of preset adjustment actions are input into a Softmax (normalized exponential function) layer, the Softmax layer outputs the normalized probability distribution, and a probability setting low process of the non-compliant preset adjustment actions in the normalized probability distribution is adopted by a preset action mask, so as to obtain probability distributions of the processed plurality of preset adjustment actions, and a preset adjustment action with the highest probability is selected from the probability distributions of the processed plurality of preset adjustment actions to be used as a first adjustment action of a clock tree to be processed.

In the embodiment of the application, the policy network model may also be referred to as an agent, and the plurality of preset adjustment actions are a set of actions that the agent can take on the clock tree. In theory, our goal is to simply add a suitable clock driving device at a suitable position and reasonably change the connection relationship. However, because netlist topologies of various scales are encountered in practical applications, canvas size and aspect ratio conditions are greatly different, which corresponds to a huge state and action space. The huge state and action space represents the result of the huge resources needed for training the neural network and the difficulty in convergence. In order to reasonably and effectively reduce the action space, a series of preset adjustment actions capable of changing the state of the current clock tree are designed according to the comprehensive characteristics of the clock tree.

The clock tree traversing direction may also be referred to as a clock tree traversing policy, the policy network model determines a policy of traversing clock tree nodes, the clock tree traversing direction may be top-down or bottom-up layer-by-layer traversing, fig. 7a and fig. 7b are schematic diagrams of clock tree traversing directions provided in the embodiments of the present application, as shown in fig. 7a, the clock tree traversing directions are top-down traversing, as shown in fig. 7b, and the clock tree traversing directions are bottom-up traversing. The forward action refers to setting the next node as the current node according to the traversal direction of the clock tree, and fig. 8 is a schematic diagram of a forward action provided in the embodiment of the present application, where, as shown in fig. 8, the forward action is performed for the left graph, and the next node is taken as the current node. The clustering work may be a binary clustering action, and fig. 9 is a schematic diagram of a binary clustering action provided in the embodiment of the present application, and as shown in fig. 9, the binary clustering action is performed for the left graph, and child nodes under the current node may be clustered into two classes, and new nodes are added at respective centroids.

Fig. 10 is a schematic diagram of an adding action provided in an embodiment of the present application, where, as shown in fig. 10, the adding action is performed for the left graph, and a buffer is inserted between the current node and its parent node. Fig. 11 is a schematic diagram of a deletion action provided in the embodiment of the present application, where, as shown in fig. 11, the deletion action is performed for the left graph, the current node is deleted, and the next node is set as the current node according to the clock tree traversal direction. Fig. 12 is a schematic diagram of an amplifying operation provided in the embodiment of the present application, and as shown in fig. 12, the amplifying operation is performed for the left graph, and the current node is replaced with a device with stronger driving capability. Fig. 13 is a schematic diagram of a shrinking operation provided in the embodiment of the present application, and as shown in fig. 13, the shrinking operation is performed for the left graph, and the current node is replaced with a device with weaker driving capability.

Fig. 14 is a schematic diagram of a detour action provided in the embodiment of the present application, as shown in fig. 14, where a left graph is connected between a current node and a parent node, and the detour action is performed for the left graph, so as to increase the line length between the current node and the parent node. Fig. 15 is a schematic diagram of a bypass action provided in the embodiment of the present application, as shown in fig. 15, in the left graph, a current node is connected to a child node through a parent node, and the bypass action is performed on the left graph, so that the current node and a progenitor node are directly connected.

In practical application, the plurality of preset adjustment actions can be set according to practical requirements, and the embodiment of the application is not particularly limited.

It should be noted that, according to the preset adjustment action, the structure of the clock tree to be processed is adjusted to obtain a first clock tree, the state of the clock to be processed may be St, and the state of the first clock tree may be st+1.

In the embodiment of the application, the target network model is to obtain a commonly used clock tree synthesis strategy, and although the state space is greatly optimized in design, the clock tree at the input end can have very huge differences, including various attributes such as the number of nodes, the topology structure, the placement position, the size of the device, the length and width of the layout, and the like. To address such training challenges, we divide the whole system into two sets of neural networks, namely a graph network model capable of perceiving the state of the clock tree, and a reinforcement learning network for training action strategies, wherein the reinforcement learning network comprises: an initial policy network model and an initial value network model. The state sensing network is trained firstly by adopting the transfer learning method, and then the reinforcement learning network is trained on the basis, so that the training complexity can be greatly reduced.

The sensing network is a network formed by a graph network model, a first full-connection layer and a feedforward network.

Optionally, the target network model is obtained by training the following method:

fig. 16 is a flow chart four of a clock tree synthesis method provided in an embodiment of the present application, and as shown in fig. 16, the method may include:

s401, training an initial graph network model according to data of a sample clock tree to obtain a graph network model.

The training process of the graph network model is a transfer learning process. The graph network model is the above-mentioned perception network.

S402, adopting a graph network model to respectively process the data of the sample clock tree to obtain the characteristic vector of the sample clock tree.

The number of the sample clock trees is multiple, and accordingly, in the embodiment of the present application, data of multiple sample clock trees also exist.

FIG. 17 is a schematic diagram of a connection structure of a graph network model, an initial policy network model, and an initial value network model according to an embodiment of the present application, where, as shown in FIG. 17, the structure of the graph network model may be the same as that of the graph network model shown in FIG. 6, and will not be described herein again; the data of the sample clock tree is input into a graph network model, which can output sample clock tree feature vectors.

S403, training the initial strategy network model and the initial value network model according to the characteristic vector of the sample clock tree and the sample global metadata of the sample clock tree until the strengthening training termination condition is met, and obtaining the strategy network model.

Wherein the training process for the initial strategy network model and the initial value network model is a reinforcement learning process.

In this embodiment of the present application, after reinforcement learning is finished, the initial value network model is removed to obtain a target network model, where the target network model is the structure shown in fig. 6, and by using the target network model, data of the clock tree to be processed may be processed in a subsequent application process, and the first adjustment action is output, so that the processes from S101 to S104 may be executed. Wherein, after the reinforcement learning is finished, the initial policy network model in fig. 17 is the policy network model in fig. 6.

It should be noted that, satisfying the reinforcement training termination condition means that the number of iterations of the initial policy network model and the initial value network model is greater than or equal to a preset number of times.

Optionally, fig. 18 is a flowchart fifth of a clock tree synthesis method provided in the embodiment of the present application, as shown in fig. 18, training model parameters of an initial policy network model and an initial value network model according to a feature vector of a sample clock tree and sample global metadata of the sample clock tree until a training termination condition is met, to obtain a policy network model, including:

S501, processing the sample clock tree feature vector and the preset sample global metadata by adopting an initial strategy network model, and outputting a sample adjustment action.

S502, processing the sample clock tree feature vector and the preset sample global metadata by adopting an initial value network model, and outputting monovalent value information.

In the embodiment of the present application, the above-mentioned processes of S501 and S502 may be performed simultaneously, the process of S501 may be performed first and then the process of S502 may be performed, and the process of S502 may be performed first and then the process of S501 may be performed, which is not particularly limited in the embodiment of the present application.

As shown in fig. 17, the sample clock tree feature vector output by the graph network model is input into the feedforward network, the sample global metadata is input into the first full connection layer, the first full connection layer can output the processed sample global metadata to the feedforward network, and the feedforward network connects the processed sample global metadata and the sample clock tree feature vector to obtain sample clock tree feature data; the feed forward network inputs the sample clock tree feature data into the initial policy network model.

As shown in fig. 17, the sample action metadata is input into the second full connection layer, and the second full connection layer may output the processed sample action metadata, and input the processed sample action metadata into the initial policy network model, and the initial policy network model may output sample probability distributions of a plurality of preset adjustment actions.

As shown in fig. 17, the sample probability distribution of the plurality of preset adjustment actions is input into a Softmax (normalized exponential function) layer, the Softmax layer outputs the normalized sample probability distribution, and the sample probability of the non-compliant preset adjustment actions in the normalized sample probability distribution is subjected to a low processing by using a preset action mask, so as to obtain the processed sample probability distribution of the plurality of preset adjustment actions, and the preset adjustment action with the highest sample probability is selected from the processed sample probability distribution of the plurality of preset adjustment actions, so as to obtain the sample adjustment action.

S503, adjusting the structure of the sample clock tree according to the sample adjusting action to obtain an adjusted sample clock tree, and updating model parameters of the initial strategy network model according to the monovalent value information.

S504, adopting the updated initial strategy network model to process the adjusted sample clock tree, and outputting the next sample adjustment action until the obtained target sample clock tree meets the preset termination condition.

After the adjusted sample clock tree is obtained, the data of the adjusted sample clock tree is input into a graph network model, then the updated initial strategy network model and the initial value network model are adopted for processing, next sample adjustment action output by the updated initial strategy network model and next value information output by the initial value network model are obtained, and then the updated initial strategy network model is updated again according to the next value information.

It should be noted that, the above process is repeatedly executed, and the adjustment may be performed by using a plurality of sample adjustment actions, in this embodiment of the present application, a plurality of actions may be performed on a current node until the forward action is executed or the number of continuous operations exceeds the maximum number of times N, a next node is set as the current node, all nodes in the sample clock tree are accessed, and a round is represented as an end, so that the process is repeated for a plurality of rounds, and the last sample clock tree is obtained as a target sample clock tree, and the state of the target sample clock tree is a preset state, or the number of adjustment times from the sample clock tree to the target sample clock tree is greater than or equal to the preset adjustment number, and it is determined that the target sample clock tree meets a preset termination condition, so as to complete a round, where a round includes multiple rounds.

Before each round starts, the action of determining the clock tree traversing direction needs to be executed, so that the clock tree traversing direction of the round can be obtained, and after the round starts, the clock tree can be traversed according to the clock tree traversing direction of the round until the round ends.

S505, updating model parameters of the updated initial strategy network model and the updated initial value network model according to index data corresponding to the data of the target sample clock tree until the reinforcement training termination condition is met, and obtaining the strategy network model.

In some embodiments, after the adjustment of one office is completed, a target sample clock tree is obtained, a negative weighted sum is calculated according to indexes such as the maximum deflection, the total transition time violations, the bus length, the average node action times and the like of the target sample clock tree, index data corresponding to the data of the target sample clock tree is obtained, the model parameters of the updated initial strategy network model and the model parameters of the initial value network model are updated once according to the index data, multi-office operation can be performed, finally multi-office index data can be obtained, and the model parameters of the updated initial strategy network model and the model parameters of the initial value network model can be updated many times according to the multi-office index data until the intensive training termination condition is met, so that the strategy network model is obtained. The number of the multiple offices can be preset according to actual requirements or experience values.

When the multi-office operation is performed, data of one sample clock tree can be randomly selected from the data of a plurality of sample clock trees for each office to obtain the data of the sample clock tree of each office, a graph network model is adopted to process the data of the sample clock tree of each office to obtain feature vectors of the sample clock tree of each office, and the operation of each office is performed according to the feature vectors of the sample clock tree of each office and sample global metadata of the sample clock tree of each office.

In the embodiment of the application, the initial policy network model can determine the environmental state S of the sample clock tree according to the data of the sample clock tree, and output the selection of the action a, and the value network model can evaluate the quality of the environmental state S. The initial strategy network model perceives the state of the current environment according to the abstract feature vector, the global metadata and the action metadata of the data of the sample clock tree.

It should be noted that, with the help of the transfer learning, we can obtain the feature vector of the sample clock tree through the trained sensing network (graph network model). And connecting the characteristic vector of the sample clock tree with the embedded result of the sample action metadata to serve as the input of a reinforcement learning network, wherein the reinforcement learning network consists of a strategy network and a value network, and the reinforcement learning network consists of a feedforward network consisting of two fully connected layers. And processing the result output by the initial strategy network model through a Softmax layer and an action mask to obtain the probability distribution of each action finally output, wherein the initial value network model is finally output as a one-dimensional value to evaluate the current state.

The model parameters theta of the initial strategy network model and the model parameters W of the initial value network model are trained by using a proximity strategy optimization method, so that the final rewards expected value obtained after one office is finished is maximum.

Optionally, fig. 19 is a flowchart sixth of a clock tree synthesis method provided in the embodiment of the present application, as shown in fig. 19, where training an initial graph network model according to data of a sample clock tree to obtain a graph network model includes:

s601, adopting an initial graph network model, and processing according to data of the sample clock tree and corresponding sample rewards to obtain predicted rewards of the sample clock tree.

And S602, updating model parameters of the initial graph network model according to the predicted reward value and the sample reward value until the migration training termination condition is met, so as to obtain the graph network model.

Wherein the data of the sample clock tree and the corresponding sample prize values may form a data set. And inputting the data of the sample clock tree, the corresponding sample rewarding value and the preset sample global metadata into an initial graph network model, and obtaining the predicted rewarding value of the sample clock tree by the initial graph network model according to the data of the sample clock tree.

It should be noted that, the sample reward value corresponding to the data of the sample clock tree is a tag value, so that we can convert the training state sensing network into a form of supervised learning. Fig. 20 is a schematic structural diagram of a sensing network according to an embodiment of the present application, where, as shown in fig. 20, the sensing network includes: in the initial graph network model, the preset sample global metadata is input into a first full-connection layer, the output of the first full-connection layer is connected with a feedforward network, the output of a graph neural network is also connected with the feedforward network, and the feedforward network is also connected with a reward prediction layer.

And in the training process, the predicted reward value of the sample clock tree can be output by adopting the reward prediction layer, and the reward prediction layer is removed after the training is completed.

Optionally, fig. 21 is a flow chart seventh of a clock tree synthesis method provided in the embodiment of the present application, as shown in fig. 21, before the process of taking the first clock tree as the final clock tree if the first clock tree meets the preset termination condition in S104, the method may further include:

s701, judging whether the state of the first clock tree is a preset state or not, or whether the adjustment times from the clock tree to be processed to the first clock tree are greater than or equal to preset adjustment times or not;

s702, if the state of the first clock tree is a preset state, or the adjustment times are greater than or equal to the preset adjustment times, determining that the first clock tree meets a preset termination condition;

s703, if the state of the first clock tree is not the preset state, or the adjustment times are smaller than the preset adjustment times, determining that the first clock tree does not meet the preset termination condition.

It should be noted that, the embodiment of the present application may include: the two parts of the target network model and the environment can adopt the environment to execute the processes of S701 to S703, and the environment can also respond to the adjustment action output by the target network model to adjust the structure of the clock tree to be processed, thereby updating the clock tree to a new state and feeding back a rewarding value for evaluating the current state. In the training process, after one office is completed, the reward value calculated by the environment for the target sample clock tree is index data of the target sample clock tree.

In the embodiment of the application, the clock tree synthesis is performed by adopting a reinforcement learning method. As the scale of training samples increases, the agent can learn more experience, constantly optimizing its own strategy. Compared with the traditional experience mode designed according to human experience, the method can abstract the state of the current clock tree well, thereby selecting actions for optimizing the final result, saving a plurality of invalid attempts and obtaining an even better clock tree comprehensive result similar to the traditional mode. In addition, the complex clock structure in the circuit is not required to be disassembled manually, the data of the clock tree to be processed is processed by adopting the trained target network model, the first adjustment action is output efficiently, and the efficient adjustment of the clock tree to be processed can be realized according to the first adjustment action, so that the comprehensive efficiency of the clock tree can be improved.

The following describes a clock tree synthesis device, an electronic device, a storage medium, etc. for executing the clock tree synthesis method provided in the present application, and specific implementation processes and technical effects of the clock tree synthesis device and the storage medium are referred to in the relevant content of the clock tree synthesis method, which are not described in detail below.

Optionally, fig. 22 is a schematic structural diagram of a clock tree synthesis device provided in an embodiment of the present application, and as shown in fig. 22, the clock tree synthesis device includes:

A first obtaining module 101, configured to obtain data of a clock tree to be processed, where the data of the clock tree to be processed is used to characterize a structure of the clock tree to be processed;

the first processing module 102 is configured to process data of the clock tree to be processed by using a target network model, so as to obtain a first adjustment action for the clock tree to be processed;

an adjusting module 103, configured to adjust the structure of the clock tree to be processed according to the first adjusting action, so as to obtain a first clock tree; and if the first clock tree meets the preset termination condition, taking the first clock tree as a final clock tree.

Optionally, the apparatus further includes:

Optionally, the second training module is specifically configured to process the feature vector of the sample clock tree and preset sample global metadata by using the initial policy network model, and output a sample adjustment action; processing the sample clock tree feature vector and preset sample global metadata by adopting the initial value network model, and outputting monovalent value information; adjusting the structure of the sample clock tree according to the sample adjustment action to obtain an adjusted sample clock tree, and updating model parameters of the initial strategy network according to the monovalent value information; processing the adjusted sample clock tree by adopting the updated initial strategy network model, and outputting the next sample adjustment action until the obtained target sample clock tree meets the preset termination condition; and updating the updated model parameters of the initial strategy network model and the initial value network model according to index data corresponding to the data of the target sample clock tree until the reinforcement training termination condition is met, so as to obtain the strategy network model.

Optionally, the apparatus further includes:

The foregoing apparatus is used for executing the method provided in the foregoing embodiment, and its implementation principle and technical effects are similar, and are not described herein again.

The above modules may be one or more integrated circuits configured to implement the above methods, for example: one or more application specific integrated circuits (Application Specific Integrated Circuit, abbreviated as ASIC), or one or more microprocessors (digital singnal processor, abbreviated as DSP), or one or more field programmable gate arrays (Field Programmable Gate Array, abbreviated as FPGA), or the like. For another example, when a module above is implemented in the form of a processing element scheduler code, the processing element may be a general-purpose processor, such as a central processing unit (Central Processing Unit, CPU) or other processor that may invoke the program code. For another example, the modules may be integrated together and implemented in the form of a system-on-a-chip (SOC).

Fig. 23 is a schematic structural diagram of an electronic device according to an embodiment of the present application, as shown in fig. 23, where the apparatus includes: processor 201, memory 202.

The memory 202 is used for storing a program, and the processor 201 calls the program stored in the memory 202 to execute the above-described method embodiment. The specific implementation manner and the technical effect are similar, and are not repeated here.

Optionally, the present invention also provides a program product, such as a computer readable storage medium, comprising a program for performing the above-described method embodiments when being executed by a processor.

In the several embodiments provided by the present invention, it should be understood that the disclosed apparatus and method may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in the embodiments of the present invention may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in hardware plus software functional units.

The integrated units implemented in the form of software functional units described above may be stored in a computer readable storage medium. The software functional unit is stored in a storage medium, and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor (english: processor) to perform some of the steps of the methods according to the embodiments of the invention. And the aforementioned storage medium includes: u disk, mobile hard disk, read-Only Memory (ROM), random access Memory (Random Access Memory, RAM), magnetic disk or optical disk, etc.

The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method of clock tree synthesis, the method comprising:

if the first clock tree meets the preset termination condition, the first clock tree is used as a final clock tree;

the target network model includes: the graph network model and the strategy network model are used for processing the data of the clock tree to be processed by adopting a target network model to obtain a first adjustment action aiming at the clock tree to be processed, and the method comprises the following steps:

2. The method according to claim 1, wherein the method further comprises:

3. The method of claim 1, wherein the plurality of preset adjustment actions includes at least two of: the method comprises the steps of clock tree traversing direction, advancing action for selecting next node, clustering action for clustering child nodes under a current node and adding new nodes, adding action for inserting a buffer between the current node and a corresponding father node, deleting the current node and setting the current node as the next node according to the traversing direction, amplifying action for replacing the current node with a strong driving device, shrinking action for replacing the current node with a weak driving device, roundabout action for increasing the line length between the current node and the father node, and roundabout action for bypassing the father node of the current node and connecting the ancestor node.

4. The method of claim 1, wherein the target network model is trained by:

5. The method according to claim 4, wherein training model parameters of an initial policy network model and an initial value network model according to the sample clock tree feature vector and sample global metadata of the sample clock tree until a training termination condition is satisfied, to obtain the policy network model, includes:

processing the adjusted sample clock tree by adopting the updated initial strategy network model, and outputting the next sample adjustment action until the target sample clock tree obtained after traversing meets the preset termination condition;

6. The method of claim 4, wherein training the initial graph network model based on the data of the sample clock tree results in the graph network model, comprising:

7. The method of claim 1, wherein before the first clock tree is considered a final clock tree if the first clock tree meets a preset termination condition, the method further comprises:

8. An electronic device, comprising: a memory and a processor, the memory storing a computer program executable by the processor, the processor implementing the clock tree synthesis method of any one of the preceding claims 1-7 when the computer program is executed.

9. A computer readable storage medium, characterized in that the storage medium has stored thereon a computer program which, when read and executed, implements the clock tree synthesis method of any of the preceding claims 1-7.