WO2023035250A1

WO2023035250A1 - Method for placement in chip, and device, medium and program product

Info

Publication number: WO2023035250A1
Application number: PCT/CN2021/117822
Authority: WO
Inventors: 陈翰轩; 王智生; 芮祥麟
Original assignee: 华为技术有限公司
Priority date: 2021-09-10
Filing date: 2021-09-10
Publication date: 2023-03-16
Also published as: CN117940931A

Abstract

A method for a placement in a chip, and a device, a medium and a program product. According to the method, a tree structure may be used during a placement process to organize and record historical placement data which has previously been assessed and is associated with candidate placements; and by means of taking the historical placement data into consideration during a subsequent process of exploring other candidate placements, the method can have a better exploration capability, and a placement scheme with a better evaluation result can be found, thereby improving the placement quality.

Description

Method, device, medium and program product for laying out chips

technical field

Embodiments of the present disclosure generally relate to the field of chip design, and more specifically relate to methods, devices, media and program products for laying out chips.

Background technique

In integrated circuit (Integrated Circuit, IC) chip design, physical design is the process of converting gate-level netlist into geometric layout. Physical design mainly includes steps such as division, layout planning, layout, clock tree synthesis, and wiring, among which layout is an important step in the early stage of physical design. The layout mainly determines the placement of the circuit units in the chip, and can be further subdivided into macro placement (Macro Placement, MP), overall layout and detailed layout.

At present, the layout quality of conventional MP tools is poor, and cannot meet the requirements of automated MP in terms of routability, delay and other indicators. In the conventional MP stage, the back-end engineers are still mainly relied on for manual layout based on experience. This makes the entire MP stage time-consuming and inefficient, and leads to a longer physical design cycle and lower chip development efficiency.

Contents of the invention

In view of the above problems, embodiments of the present disclosure aim to provide a solution for laying out chips.

According to a first aspect of the present disclosure, there is provided a method for laying out a chip, the method comprising: determining a plurality of candidates corresponding to a plurality of first circuit units in the chip based on netlist data of the chip a plurality of evaluation results associated with the layout, wherein each evaluation result in the plurality of evaluation results indicates the layout quality of the corresponding candidate layout, the netlist data at least indicates a plurality of first circuit cells and their connection relationships, and the plurality of candidate layouts The layout process data of a plurality of first circuit units in each candidate layout is organized in a tree structure, and a plurality of candidate layouts correspond to leaf nodes of the tree structure; and based on a plurality of evaluation results, selecting from a plurality of candidate layouts target layout. By using a tree structure to organize and record the historical layout data associated with previously visited candidate layouts, and considering the historical layout data in the subsequent exploration of other candidate layouts, the method can obtain better exploration capabilities and be able to find The layout scheme with a better evaluation result is used to improve the layout quality.

In some implementations, the multiple candidate layouts include an initial candidate layout and at least one optimized candidate layout, and determining the multiple evaluation results includes: based on a predetermined arrangement sequence of the multiple first circuit units, and indicating the multiple first circuit units in the netlist data. The data of the connection relationship of the circuit unit determines the initial evaluation result associated with the initial candidate layout, wherein the predetermined arrangement order indicates the order in which the plurality of first circuit units are arranged according to the predetermined strategy; based on the initial candidate layout and the initial candidate layout associated with the initial candidate layout constructing an initial tree structure; and based on the netlist data, the initial candidate layout and the initial tree structure, determining at least one optimization candidate layout and at least one optimization evaluation result respectively associated with the at least one optimization candidate layout. In this way, the first circuit unit can be arranged by taking historical placement data into consideration during the process of determining an optimized candidate placement to determine an optimized candidate placement. Therefore, the exploration ability of the method according to the present disclosure can be improved, and the possibility of finding an optimized candidate layout with a better evaluation result can be improved, thereby improving the layout quality.

In some implementations, determining at least one optimization candidate layout and at least one optimization evaluation result includes: setting the initial tree structure as a reference tree structure; Candidate layout; Based on the data indicating the connection relationship of a plurality of first circuit cells in the netlist data, determine an optimization evaluation result associated with an optimized candidate layout; determine whether the layout termination condition is satisfied; and if it is determined that the placement termination condition is not Satisfied, based on the reference tree structure, one optimization candidate layout and placement process data associated with one optimization candidate layout, constructing the optimization tree structure to update the reference tree structure. In such an implementation manner, when to end the exploration of candidate layouts is controlled by setting layout termination conditions. In this way, a proper balance can be achieved between the layout efficiency and the quality of the target layout, so as to obtain a layout result with better quality at higher efficiency.

In some implementations, determining an optimized candidate layout includes: setting one of the plurality of first circuit units as a unit to be arranged based on a predetermined arrangement sequence; iteratively performing the following at least once: based on the reference tree structure, The current arrangement of the chip and the unit to be arranged determine the updated arrangement of the chip, wherein the updated arrangement includes the arrangement of the unit to be arranged and the first circuit unit that has been arranged before among the plurality of first circuit units; update by using the updated arrangement current arrangement; determining whether at least one first circuit unit among the plurality of first circuit units is not included in the current arrangement; and if it is determined that at least one first circuit unit among the plurality of first circuit units is not included in the current arrangement In the method, based on a predetermined arrangement order, the next first circuit unit among the plurality of first circuit units is set as a unit to be arranged. Determining an optimal candidate layout also includes determining the current arrangement of chips as an optimal candidate layout. In this way, historical layout data can be considered in the process of exploring other candidate layouts, better exploration capabilities can be obtained, and layout schemes with better evaluation results can be found, thereby improving layout quality.

In some implementations, determining the updated arrangement includes: based on the current arrangement, determining a candidate arrangement set, the candidate arrangement set includes at least one of the following items: a first candidate arrangement corresponding to a child node of the current arrangement, and by adding A second candidate arrangement obtained by the unit to be arranged, wherein the second candidate arrangement is different from the first candidate arrangement; based on the reference tree structure, determining an evaluation set associated with the candidate arrangement set; and based on the evaluation set, selecting an updated arrangement from the candidate arrangement set . In this way, historical layout data can be considered in the process of exploring other candidate layouts, better exploration capabilities can be obtained, and layout schemes with better evaluation results can be found, thereby improving layout quality.

In some implementations, determining the evaluation set associated with the candidate arrangement set includes: calculating a first mean value of the evaluation results of the candidate arrangement associated with the first candidate arrangement; determining based on the number of times the first candidate arrangement and the current arrangement are visited A first weighted value; obtaining a probability set associated with the set of candidate arrangements; and determining the first candidate arrangement in the evaluation set based on the first mean value, the first weighted value, and the first probability associated with the first candidate arrangement in the probability set An associated first evaluation, wherein the candidate layouts associated with the first candidate arrangement include candidate layouts corresponding to leaf nodes of the first candidate arrangement. By evaluating the first candidate arrangement included in the current parameter tree structure in this way, a sufficient and comprehensive evaluation of the first candidate arrangement can be achieved, thereby helping to determine the most suitable candidate arrangement, and improving the evaluation results. Possibility of better optimizing candidate layouts.

In some implementations, determining the evaluation set associated with the candidate arrangement set includes: calculating a second mean value of the evaluation results of the candidate layouts corresponding to all leaf nodes of the reference tree structure; based on the number of times the nodes corresponding to the current arrangement are visited determining a second weighted value; obtaining a set of probabilities associated with the set of candidate arrangements; and based on a second mean value, a second weighted value, and a second probability associated with the second candidate arrangement in the set of probabilities, A second evaluation associated with the candidate placement. Evaluating the second candidate arrangement that is not included in the current parameter tree structure in this way can make the first evaluation and the second evaluation comparable, thus helping to determine the best candidate arrangement by comparing the evaluation results of each candidate arrangement. suitable candidate placements, and increase the probability of finding optimized candidate placements with better evaluation results.

In some implementations, the layout termination condition includes at least one of the following: the number of multiple candidate layouts reaches a predetermined number threshold; or the duration of iterations reaches a predetermined time threshold. By appropriately setting the predetermined number threshold and/or the predetermined time threshold, the layout efficiency and the quality of the target layout can be balanced, so as to obtain a layout result of better quality with higher efficiency.

In some implementations, the chip further includes at least one second circuit unit, and the netlist data also indicates the connection relationship between the at least one second circuit unit and the plurality of first circuit units, and determining a plurality of evaluation results includes: based on the netlist data and A candidate layout among a plurality of candidate layouts, determining a complete layout associated with a candidate layout, the complete layout at least indicates the arrangement and wiring of a plurality of first circuit units and at least one second circuit unit; and determining that it is related to the complete layout Associated complete evaluation results to determine an evaluation result associated with a candidate layout among the plurality of evaluation results. In this way, the evaluation result of the candidate layout can be determined based on the final complete layout, so that the evaluation result can measure the quality of the candidate layout more accurately. This helps to improve the quality of the finalized target layout.

In some implementations, the evaluation result is determined based on at least one of: line length, congestion, maximum delay, or total delay. With the help of these evaluation indicators, the quality of candidate layouts can be comprehensively evaluated from multiple dimensions, which helps to select the candidate layout with the best overall performance as the target layout.

According to a second aspect of the present disclosure, an electronic device is provided. The electronic device includes: an evaluation result determining module, configured to determine a plurality of evaluation results respectively associated with a plurality of candidate layouts of a plurality of first circuit units in the chip based on the netlist data of the chip, wherein the plurality of Each of the evaluation results indicates the layout quality of the corresponding candidate layout, the netlist data at least indicates a plurality of first circuit cells and their connection relationships, and the plurality of first circuits in each candidate layout of the plurality of candidate layouts The arrangement process data of the unit is organized in a tree structure, and a plurality of candidate layouts correspond to leaf nodes of the tree structure; and a target layout selection module for selecting a target layout from the plurality of candidate layouts based on a plurality of evaluation results. The electronic device can obtain better exploration capabilities by using a tree structure to organize and record historical layout data associated with previously visited candidate layouts, and consider the historical layout data in the subsequent exploration of other candidate layouts, and can Find a layout scheme with a better evaluation result, so as to improve the layout quality.

In some implementations, the multiple candidate layouts include an initial candidate layout and at least one optimized candidate layout, and the evaluation result determination module includes: an initial evaluation result determination module, configured to be based on a predetermined arrangement sequence of a plurality of first circuit units, and a netlist The data indicating the connection relationship of the plurality of first circuit units in the data determines the initial evaluation result associated with the initial candidate layout, wherein the predetermined arrangement order indicates the order in which the plurality of first circuit units are arranged according to a predetermined strategy; initial tree structure construction A module for constructing an initial tree structure based on the initial candidate placement and placement process data associated with the initial candidate placement; and an optimization evaluation result determination module for determining at least one based on the netlist data, the initial candidate placement, and the initial tree structure Optimization candidate layouts and at least one optimization evaluation result respectively associated with at least one optimization candidate layout. In such an implementation manner, the electronic device may arrange the first circuit unit by considering historical layout data during the process of determining the optimized candidate layout, so as to determine the optimized candidate layout. Therefore, the exploration capability of the electronic device according to the present disclosure can be improved, and the possibility of finding an optimized candidate layout with a better evaluation result can be improved, thereby improving the layout quality.

In some implementations, the optimization evaluation result determination module includes: a reference tree structure setting module, configured to set the initial tree structure as a reference tree structure; and a reference tree structure update module, configured to iteratively perform at least one of the following: based on a predetermined arrangement Order and reference tree structure, determine an optimization candidate layout; Based on the data indicating the connection relationship of a plurality of first circuit units in the netlist data, determine an optimization evaluation result associated with an optimization candidate layout; determine whether the layout termination condition is satisfied ; and if it is determined that the layout termination condition is not satisfied, based on the reference tree structure, an optimization candidate layout, and placement process data associated with an optimization candidate layout, constructing an optimization tree structure to update the reference tree structure. In such an implementation manner, when to end the exploration of candidate layouts is controlled by setting layout termination conditions. In this way, the electronic device can achieve a proper balance between the layout efficiency and the quality of the target layout, so as to obtain a better quality layout result with higher efficiency.

In some implementations, the reference tree structure updating module is further configured to: set one of the plurality of first circuit units as a unit to be arranged based on a predetermined arrangement order; iteratively perform the following at least once: based on the reference tree structure, the current layout of the chip and the unit to be arranged, and determine the updated layout of the chip, wherein the updated layout includes the layout of the first circuit unit that has been previously arranged in the unit to be arranged and a plurality of first circuit units; using the updated layout to update the current arrangement; determine whether there is at least one first circuit unit in the plurality of first circuit units that is not included in the current arrangement; and if it is determined that at least one first circuit unit in the plurality of first circuit units is not included in In the current arrangement, based on a predetermined arrangement sequence, the next first circuit unit among the plurality of first circuit units is set as the unit to be arranged. The reference tree structure update module is also used to determine the current arrangement of chips as an optimized candidate arrangement. In this way, the electronic device can consider historical layout data in the process of exploring other candidate layouts, obtain better exploration capabilities, and find a layout scheme with a better evaluation result, thereby improving layout quality.

In some implementations, the reference tree structure update module is further configured to: determine a candidate arrangement set based on the current arrangement, and the candidate arrangement set includes at least one of the following items: a first candidate arrangement corresponding to a child node of the current arrangement, and by adding a second candidate arrangement obtained by the unit to be arranged to the current arrangement, wherein the second candidate arrangement is different from the first candidate arrangement; based on the reference tree structure, determining an evaluation set associated with the candidate arrangement set; and based on the evaluation set, selecting from the candidate arrangement Focus on selecting the update layout. In this way, the electronic device can consider historical layout data in the process of exploring other candidate layouts, obtain better exploration capabilities, and find a layout scheme with a better evaluation result, thereby improving layout quality.

In some implementations, the reference tree structure update module is further configured to: calculate a first mean value of evaluation results of candidate layouts associated with the first candidate layout; determine a first weight based on the number of times the first candidate layout and the current layout are visited value; obtain a probability set associated with the set of candidate arrangements; and determine the evaluation set associated with the first candidate arrangement based on the first mean value, the first weighted value, and the first probability associated with the first candidate arrangement in the probability set A first evaluation, wherein the candidate layouts associated with the first candidate arrangement include candidate layouts corresponding to leaf nodes of the first candidate arrangement. By evaluating the first candidate arrangement included in the current parameter tree structure in this way, a sufficient and comprehensive evaluation of the first candidate arrangement can be achieved, thereby helping to determine the most suitable candidate arrangement, and improving the evaluation results. Possibility of better optimizing candidate layouts.

In some implementations, the reference tree structure update module is further configured to: calculate the second mean value of the evaluation results of the candidate layouts corresponding to all the leaf nodes of the reference tree structure; weighted value; obtaining a probability set associated with the set of candidate arrangements; and based on a second mean value, a second weighted value, and a second probability associated with the second candidate arrangement in the probability set, determine the probability set associated with the second candidate arrangement in the evaluation set Union's second evaluation. Evaluating the second candidate arrangement that is not included in the current parameter tree structure in this way can make the first evaluation and the second evaluation comparable, thus helping to determine the best candidate arrangement by comparing the evaluation results of each candidate arrangement. suitable candidate placements, and increase the probability of finding optimized candidate placements with better evaluation results.

In some implementations, the layout termination condition includes at least one of the following: the number of multiple candidate layouts reaches a predetermined number threshold; or the duration of iterations reaches a predetermined time threshold. By properly setting the predetermined number threshold and/or the predetermined time threshold, the layout efficiency and the quality of the target layout can be balanced, so as to obtain a layout result with better quality at higher efficiency.

In some implementations, the chip further includes at least one second circuit unit, and the netlist data also indicates the connection relationship between the at least one second circuit unit and a plurality of first circuit units, and the evaluation result determination module includes: a complete layout determination module, using Determining a complete layout associated with a candidate layout based on the netlist data and one of the plurality of candidate layouts, the complete layout at least indicating the arrangement and wiring of a plurality of first circuit cells and at least one second circuit cell; and a complete evaluation result determining module, configured to determine a complete evaluation result associated with the complete layout, so as to determine an evaluation result associated with a candidate layout among the plurality of evaluation results. In this way, the evaluation result of the candidate layout can be determined based on the final complete layout, so that the evaluation result can measure the quality of the candidate layout more accurately. This helps to improve the quality of the finalized target layout.

According to a third aspect of the present disclosure, an electronic device is provided. The electronic device comprises: at least one computing unit; at least one memory, the at least one memory being coupled to the at least one computing unit and storing instructions for execution by the at least one computing unit, the instructions, when executed by the at least one computing unit, cause the device A method according to the first aspect of the present disclosure is performed. The electronic device can obtain better exploration capabilities by using a tree structure to organize and record historical layout data associated with previously visited candidate layouts, and consider the historical layout data in the subsequent exploration of other candidate layouts, and can Find a layout scheme with a better evaluation result, so as to improve the layout quality.

According to a fourth aspect of the present disclosure, a computer readable storage medium is provided. The computer readable storage medium stores a computer program. The computer program implements the method according to the first aspect of the present disclosure when executed by a processor. By using a tree structure to organize and record the historical placement data associated with previously visited candidate layouts, and taking the historical placement data into account during the subsequent exploration of other candidate layouts, better exploration capabilities and the ability to find evaluation results A better layout scheme, thereby improving the layout quality.

According to a fifth aspect of the present disclosure, a computer program product is provided. The computer program product comprises computer-executable instructions which, when executed by a processor, cause a computer to implement the method according to the first aspect. By using a tree structure to organize and record the historical placement data associated with previously visited candidate layouts, and taking the historical placement data into account during the subsequent exploration of other candidate layouts, better exploration capabilities and the ability to find evaluation results A better layout scheme, thereby improving the layout quality.

This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or principal characteristics of the disclosure, nor is it intended to limit the scope of the disclosure.

Description of drawings

The above and other objects, features and advantages of embodiments of the present disclosure will become readily understood by reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of the present disclosure are shown by way of example and not limitation.

Figure 1 shows a flow chart of the design and manufacture process of an integrated circuit;

Figure 2 shows a block diagram of an example environment according to some embodiments of the present disclosure;

Fig. 3 shows a schematic diagram of a tree structure for recording arrangement process data according to some embodiments of the present disclosure;

FIG. 4 shows a flowchart of a method for laying out a chip according to some embodiments of the present disclosure;

FIG. 5 shows a flowchart of a method for determining candidate layouts and their evaluation results according to some embodiments of the present disclosure;

FIG. 6 shows a flowchart of a method for determining an optimization candidate layout and an optimization evaluation result according to some embodiments of the present disclosure;

FIG. 7 shows a flowchart of a method for determining an optimized candidate layout according to some embodiments of the present disclosure;

Fig. 8 shows a schematic diagram of the process of constructing a tree structure according to some embodiments of the present disclosure;

Figure 9 shows a block diagram of an example apparatus for laying out chips according to some embodiments of the present disclosure; and

Figure 10 shows a schematic block diagram of an example device that may be used to implement some embodiments of the present disclosure.

Detailed ways

Preferred embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although preferred embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

As used herein, the term "comprise" and its variants mean open inclusion, ie "including but not limited to". The term "or" means "and/or" unless otherwise stated. The term "based on" means "based at least in part on". The terms "one example embodiment" and "one embodiment" mean "at least one example embodiment." The term "another embodiment" means "at least one further embodiment". The terms "upper", "lower", "front", "rear" and other words indicating placement or positional relationship are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the principles of the present disclosure, rather than indicating or implying References to elements must have a particular orientation, be constructed, or operate in a particular orientation, and thus should not be construed as limiting the disclosure.

As mentioned above, with the development of integrated circuit manufacturing process and the reduction of feature size, the complexity of physical design has also increased exponentially. Macrocell layout is the first step in the layout phase, and its layout quality has a major impact on the final physical design index.

Conventional macrocell layout schemes usually include the following two: first, with the help of an appropriate layout coding method, the macrocell arrangement is encoded as a sequence, and adjusted using a stochastic optimization method; second, the layout problem is transformed into a mathematical Planning problem, and the evaluation index of layout quality is modeled as a function, so as to use optimization algorithm to solve the layout problem. However, these two schemes each have corresponding problems. For example, for the first solution, there are often limitations in macro-unit coding, such as the inability to reflect the area information of the macro-unit, etc., making it difficult to obtain a layout result with better quality. For the second solution, the general law of macro-unit layout is not considered, and macro-units can be arranged in the entire area to be laid out, so that the range to be explored is too large, making it difficult to obtain better-quality layout results.

Embodiments of the present disclosure propose a scheme for laying out chips to address one or more of the above-mentioned problems and other potential problems. In the present disclosure, better exploration capabilities can be obtained by using a tree structure to organize and record historical layout data associated with previously visited candidate layouts, and considering the historical layout data in the subsequent exploration of other candidate layouts, And a layout scheme with a better evaluation result can be found, thereby improving the layout quality.

FIG. 1 shows a flowchart of a design and manufacture process 100 for an integrated circuit. The design-to-manufacture process 100 begins with specification development 110 . In the stage of specification formulation 110, the functional and performance requirements that the integrated circuit needs to meet are determined. Then, in the stage of integrated circuit design 120, circuit design 122 is first performed by means of EDA (electronic design automation, EDA) software. After the circuit is determined, the physical design 124 is performed to determine the layout and wiring of the circuit units in the integrated circuit, so as to obtain the circuit layout. After obtaining the circuit layout, mask fabrication 126 may be performed to obtain masks for forming the designed circuits on the wafer. Subsequently, in the stage of manufacturing 130, integrated circuits are formed on the wafer through processes such as photolithography, etching, ion implantation, thin film deposition, and polishing. In the stage of packaging 140 , the wafer is cut to obtain bare chips, and the bare chips are packaged by bonding, welding, molding and other processes to obtain chips. The resulting chip is tested in a testing 150 stage to ensure that the performance of the finished chip meets the requirements established in specification 110 . Finally, the tested chips 160 can be delivered to customers.

Physical design 124 mainly includes steps such as division, layout planning, layout, clock tree synthesis, and wiring, and involves evaluation indicators such as routability, delay, power consumption, area, and manufacturability. These evaluation indicators often need to be accurately obtained after the entire physical design 124 process is completed. Therefore, when the final evaluation index does not meet the design requirements, it is often necessary to return to the previous different physical design steps for iterative optimization. Conventional physical design processes often require multiple rounds of iterative evaluation, which is inefficient and time-consuming. Macrocell layout is the first step in the layout phase, and its layout quality has a significant impact on the final evaluation index. Therefore, it is expected to improve the automation degree and layout quality of macrocell layout, thereby shortening the physical design cycle and improving chip development efficiency.

FIG. 2 shows a block diagram of an example environment 200 according to some embodiments of the present disclosure. As shown in FIG. 2 , example environment 200 may generally include electronic device 220 . In some embodiments, the electronic device 220 may be a device having computing functions such as a personal computer, a workstation, a server, and the like. This disclosure does not limit this.

Electronic device 220 takes as input netlist data 210 representing the circuits in the chip. The chip can include, for example, a plurality of first circuit units. In some embodiments, the first circuit unit is a macro unit to be arranged. In the context of the present disclosure, a "macro unit" refers to a predefined logic function realization unit composed of flip-flops, arithmetic logic units, etc., which have a higher abstraction level than logic gates. In some embodiments, the first circuit unit may also be any other suitable circuit unit to be arranged. This disclosure does not limit this.

In some embodiments, the netlist data 210 may indicate a plurality of first circuit units included in the chip and connection relationships of these first circuit units. In some embodiments, the netlist data 210 may also indicate the area to be laid out of the chip, process parameters and other information. This disclosure does not limit this.

In some embodiments, netlist data 210 may be entered into electronic device 220 by a user. In some embodiments, the netlist data 210 may have been pre-stored in the electronic device 220 . In some embodiments, electronic device 220 may also be communicatively coupled to other devices to obtain netlist data 210 from other devices. This disclosure does not limit this.

The electronic device 220 arranges the first circuit unit in the to-be-layout area of the chip based on the netlist data 210 to determine a candidate layout. The electronic device 220 organizes and records the determined candidate layouts and the layout process data used to obtain the candidate layouts in a tree structure 230 . In a subsequent process of determining another layout candidate, the electronic device 220 may arrange the first circuit unit by considering the arrangement process data recorded in the tree structure 230 . The electronic device 220 selects the target layout 240 of the plurality of first circuit units from the candidate layouts based on the evaluation result of the candidate layouts. This will be described in detail below with reference to FIGS. 3 to 8 .

FIG. 3 shows a schematic diagram of a tree structure 230 for recording arrangement process data according to some embodiments of the present disclosure. For the purpose of illustration and simplification, in the embodiment shown in FIG. circuit unit 340). It should be understood that the number of first circuit units 340 to be arranged may also be less than 3 or greater than 3, which is not limited in the present disclosure.

The root node 310 of the tree structure 230 corresponds to a blank layout, ie, an area to be laid out in which the first circuit unit 340 has not been arranged yet. The four leaf nodes 330-1, 330-2, 330-3 and 330-4 (separately or collectively referred to as leaf nodes 330) included in the tree structure 230 in FIG. layout. In the context of the present disclosure, "candidate layout" means a layout in which the arrangement manner of all the first circuit units 340 to be arranged has been determined. In the tree structure 230 , the nodes on the branches passed from the root node 310 to the leaf nodes 330 indicate an arrangement process for obtaining the layout candidates corresponding to the corresponding leaf nodes 330 . For example, starting from the root node 310, go through the partial layouts corresponding to the nodes 320-1 and 320-3, and obtain the candidate layout corresponding to the leaf node 330-3. In the context of the present disclosure, "partial layout" means a layout in which the arrangement manner of at least one of the first circuit units 340 to be arranged has not yet been determined.

With the help of the tree structure 230, the electronic device 220 can organize and record the layout process data in an orderly manner, so that the previously recorded layout process data can be considered in the subsequent process of determining a new candidate layout, thereby improving the probability of obtaining a candidate layout with a better evaluation result. probability, thereby improving the layout quality. This will be further described in detail below with reference to FIGS. 4 to 8 .

FIG. 4 shows a flowchart of a method 400 for laying out a chip according to some embodiments of the present disclosure. In some embodiments, the method 400 may be executed by the electronic device 220 as shown in FIG. 2 . It should be appreciated that method 400 may also include additional blocks not shown and/or blocks shown may be omitted, and that the scope of the present disclosure is not limited in this regard.

In block 402, the electronic device 220 determines a plurality of evaluation results respectively associated with a plurality of candidate layouts of the plurality of first circuit units 340 in the chip based on the netlist data 210, wherein the netlist data 210 at least indicates the plurality of first The circuit units 340 and their connection relationships, the arrangement process data of the plurality of first circuit units 340 in each of the plurality of candidate layouts are organized in a tree structure 230, and the plurality of candidate layouts correspond to the leaves of the tree structure 230 Node 330.

In some embodiments, the electronic device 220 may arrange a plurality of first circuit units 340 in the area to be laid out of the chip based on the netlist data 210 to determine candidate layouts. This will be described in further detail below with reference to FIGS. 5 to 8 .

In some embodiments, the electronic device 220 can perform routing (routing) according to the data indicating the connection relationship of the plurality of first circuit units 340 in the netlist data 210, that is, connect the first circuit units 340 in the candidate layout with wires . The electronic device 220 can evaluate the candidate layout by means of evaluation indicators such as line length, congestion (congestion), maximum delay (worst negative slack, WNS) and total delay (total negative slack, TNS), to determine Evaluation results associated with candidate layouts. For example, the electronic device 220 can determine the line length by calculating the total length of the lines connecting the first circuit unit 340, determine the congestion by calculating the line density in the area with the densest line density in the candidate layout, and determine the congestion by calculating the total length of the lines in the netlist. to determine the maximum delay and/or total delay. In some embodiments, the electronic device 220 may determine the evaluation result based on the weighted sum of the line length, congestion, maximum delay, and total delay of the candidate layout. In this way, the quality of candidate layouts can be comprehensively evaluated from multiple dimensions, which helps to select the candidate layout with the best overall performance as the target layout. It should be understood that the electronic device 220 may also determine the evaluation result associated with the candidate layout based on any other suitable evaluation index. This disclosure does not limit this.

In some embodiments, the chip may further include at least one second circuit unit. Exemplarily, the second circuit unit is a standard unit such as gate circuit and flip-flop. In this case, the netlist data 210 may further indicate the connection relationship between the second circuit unit and the first circuit unit 340, and the electronic device 220 may further determine the layout of the second circuit unit to determine the layout associated with the candidate layout. evaluation result. In this regard, the electronic device 220 determines a complete layout associated with the candidate layout based on the netlist data 210 and the candidate layout, the complete layout at least indicating the arrangement and wiring of the plurality of first circuit units 340 and at least one second circuit unit.

In some embodiments, the electronic device 220 can arrange the second circuit unit based on the candidate layout, and perform routing based on the data indicating the connection relationship of each circuit unit in the netlist data 210, so as to determine the complete layout associated with the candidate layout. layout. In a manner similar to that described above, the electronic device 220 can evaluate the complete layout by means of evaluation indicators such as line length, congestion, maximum delay, and total delay to determine the complete layout associated with the complete layout. evaluation result. The electronic device 220 may set the complete evaluation result of the complete layout as the evaluation result of the corresponding candidate layout. In this way, the electronic device 220 can determine the evaluation result of the candidate layout based on the final complete layout, so that the evaluation result can measure the quality of the candidate layout more accurately. This helps to improve the quality of the finalized target layout 240 .

In some embodiments, for each candidate layout among the plurality of candidate layouts, the electronic device 220 may determine a complete layout associated with the corresponding candidate layout, so as to determine the corresponding candidate layout according to the complete evaluation result of the complete layout. evaluation result.

It should be understood that the electronic device 220 may also determine the evaluation results associated with the candidate layouts in any other suitable manner. This disclosure does not limit this.

In some embodiments, the electronic device 220 may organize the determined candidate layouts, evaluation results, and layout process data of the first circuit unit 340 according to the tree structure 230 shown in FIG. 3 . In the context of the present disclosure, the candidate layouts, evaluation results, and layout process data of the first circuit unit 340 recorded in the tree structure 230 may be collectively referred to as historical layout data. It should be understood that historical placement data may also include additional items not listed and/or listed items may be omitted, and that the scope of the present disclosure is not limited in this regard. In the subsequent process of exploring another candidate layout, the electronic device 220 may select the layout of the first circuit unit 340 by considering the historical layout data. This will be described in further detail below with reference to FIGS. 5 to 8 . In this way, the method 400 can obtain better exploration capabilities, and can find a layout solution with a better evaluation result, thereby improving the layout quality.

At block 404, the electronic device 220 selects the target layout 240 from the plurality of candidate layouts based on the plurality of evaluation results. In some embodiments, the electronic device 220 may select a candidate layout with the best evaluation result among multiple candidate layouts as the target layout 240 . It should be understood that the target layout 240 may also be selected in any other suitable manner. This disclosure does not limit this.

In some embodiments, the electronic device 220 may output the information of the target layout 240 for the user to use or further adjust the determined layout. In some embodiments, the electronic device 220 may provide the information of the target layout 240 as an input to other layout software or devices, so as to execute a subsequent design process. This disclosure does not limit this.

FIG. 5 shows a flowchart of a method 500 for determining candidate layouts and their evaluation results according to some embodiments of the present disclosure. For example, method 500 may be implemented as an example of block 402 as shown in FIG. 4 . In some embodiments, the method 500 may be executed by the electronic device 220 as shown in FIG. 2 . It should be appreciated that method 500 may also include additional blocks not shown and/or blocks shown may be omitted, and that the scope of the present disclosure is not limited in this respect.

In block 502, the electronic device 220 determines the initial evaluation associated with the initial candidate layout based on the predetermined arrangement sequence of the plurality of first circuit units 340 and the data indicating the connection relationship of the plurality of first circuit units 340 in the netlist data 210 As a result, wherein the predetermined arrangement order indicates the order in which the plurality of first circuit units 340 are arranged according to a predetermined strategy.

In some embodiments, the electronic device 220 may arrange the plurality of first circuit units 340 to be arranged according to the data indicating the area of the first circuit unit 340 in the netlist data 210, for example, according to the area from the largest to the smallest, so as to determine the predetermined Arrangement order. Referring to the tree structure 230 shown in FIG. 3, for each layout, the electronic device 220 sequentially arranges the first circuit units 340-1, 340-2 and 340-3 in the area to be laid out in descending order of area . In some embodiments, the electronic device 220 may also arrange the plurality of first circuit units 340 to be arranged according to the module division according to the information indicating the module to which the first circuit unit 340 belongs in the netlist data 210, so as to determine the predetermined Arrangement order. This disclosure does not limit this.

In some embodiments, the electronic device 220 may arrange the first circuit unit 340 to be arranged in the area to be laid out according to the aforementioned predetermined arrangement order, so as to determine an initial candidate layout. In the context of this disclosure, an "initial candidate layout" means the first candidate layout obtained during the layout process. In other words, before the initial candidate layout is obtained, no other candidate layouts and arrangement process data have been recorded in the tree structure 230 . Therefore, in the process of determining the initial candidate layout, the electronic device 220 does not consider the historical layout data since there is no historical layout data. In some embodiments, the electronic device 220 may randomly arrange the first circuit units 340 to determine an initial candidate layout. The electronic device 220 may also arrange the first circuit unit 340 in any other suitable manner to determine the initial candidate layout. This disclosure does not limit this.

In some embodiments, the electronic device 220 may determine the initial evaluation result associated with the initial candidate layout in a manner similar to that described above in conjunction with FIG. 4 , which will not be repeated here.

At block 504, the electronic device 220 builds an initial tree structure based on the initial candidate layout and placement process data associated with the initial candidate layout. FIG. 8 shows a schematic diagram of a process 800 of constructing a tree structure according to some embodiments of the present disclosure. In some embodiments, as shown in FIG. 8 , the electronic device 220 may construct an initial tree structure 810 - 1 by organizing the initial candidate layout and partial layouts used to obtain the initial candidate layout in a tree structure. In the initial tree structure 810-1 shown in FIG. 8, the data of the leaf node 330-1 represent the initial candidate layout, and the data of the ancestor nodes 310, 320-1, 320-2 of the leaf node 330-1 respectively represent the Get a partial layout of the initial candidate layout. In some embodiments, the electronic device 220 may also store an initial evaluation result associated with the initial candidate layout, eg, 1.2, together with the initial candidate layout at the leaf node 330-1. It should be understood that the electronic device 220 may also construct the initial tree structure 810-1 in any other suitable manner. This disclosure does not limit this.

In block 506, the electronic device 220 determines at least one optimized candidate layout and at least one optimized evaluation result respectively associated with the at least one optimized candidate layout based on the netlist data 210, the initial candidate layout and the initial tree structure 810-1. In the context of this disclosure, an "optimized candidate layout" means a candidate layout determined after an initial candidate layout during a layout process. In other words, during the process of determining the optimization candidate layout, historical layout data has been recorded in the tree structure 230 . Accordingly, the electronic device 220 may arrange the first circuit unit 340 by considering the historical arrangement data to determine an optimization candidate layout. This will be described in further detail below with reference to FIGS. 6 to 8 . In this way, the exploration capability of the solution according to the present disclosure can be improved, and the possibility of finding an optimized candidate layout with a better evaluation result can be improved, thereby improving the layout quality.

FIG. 6 shows a flowchart of a method 600 for determining optimization candidate layouts and optimization evaluation results according to some embodiments of the present disclosure. For example, method 600 may be implemented as an example of block 506 as shown in FIG. 5 . In some embodiments, the method 600 may be executed by the electronic device 220 as shown in FIG. 2 . It should be appreciated that method 600 may also include additional blocks not shown and/or blocks shown may be omitted, and that the scope of the present disclosure is not limited in this regard.

At block 602, the electronic device 220 may set the initial tree structure 810-1 as a reference tree structure. At block 604, the electronic device 220 may determine an optimal candidate layout based on the predetermined arrangement order and the reference tree structure. This will be described in further detail below with reference to FIGS. 7 to 8 .

In block 606 , the electronic device 220 determines an optimization evaluation result associated with an optimization candidate layout based on the data indicating the connection relationship of the plurality of first circuit units 340 in the netlist data 210 . In some embodiments, the electronic device 220 may determine the optimization evaluation result associated with the optimization candidate layout in a manner similar to that described above in conjunction with FIG. 4 , which will not be repeated here.

At block 608, the electronic device 220 determines whether a placement termination condition is satisfied. A chip often includes a large number of first circuit units 340 , for example hundreds of first circuit units 340 . Therefore, in the case of limited computing power, it is expected that it will take a long time to select the globally optimal candidate layout as the target layout 240 by exploring all possible candidate layouts of the first circuit unit 340 . Therefore, in some embodiments according to the present disclosure, when to end the exploration of the candidate layout is controlled by setting the layout termination condition. In other words, the electronic device 220 only explores a limited number of candidate layouts of the first circuit unit 340 to select a locally optimal candidate layout as the target layout 240 . In this way, a proper balance can be achieved between the layout efficiency and the quality of the target layout 240 , so as to obtain a layout result with better quality with higher efficiency. It should be understood that the solution according to the present disclosure is also applicable to the case of exploring all possible candidate layouts of the first circuit unit 340 to select the globally optimal candidate layout as the target layout 240 . This disclosure does not limit this.

In some embodiments, the layout termination condition may include that the number of determined plurality of candidate layouts reaches a predetermined number threshold. In some embodiments, the predetermined number threshold may be pre-entered by the user. In some embodiments, a default value may be used for the predetermined number threshold. This disclosure does not limit this. By appropriately setting the predetermined number threshold, the layout efficiency and the quality of the target layout 240 can be balanced, so as to obtain a layout result with better quality with higher efficiency.

In some embodiments, the layout termination condition may include iteratively determining the optimization candidate layout and the duration of the optimization evaluation result reaching a predetermined time threshold. In some embodiments, the predetermined time threshold may be pre-input by the user. In some embodiments, the predetermined time threshold may adopt a default value. This disclosure does not limit this. By properly setting the predetermined time threshold, the layout efficiency and the quality of the target layout 240 can be taken into consideration, so that a layout result with better quality can be obtained with higher efficiency. In some other embodiments, the layout termination condition may also be set in any other suitable manner. This disclosure does not limit this.

If at block 608 it is determined that the layout termination condition has not been met, then method 600 proceeds to block 610 . At block 610, the electronic device 220 constructs an optimized tree structure to update the reference tree structure based on the reference tree structure, one optimized candidate layout, and placement process data associated with one optimized candidate layout. In some embodiments, as shown in FIG. 8 , the electronics can construct an optimization tree structure 810 - 2 by adding optimization candidate layouts and their placement process data on the basis of the reference tree structure. In the optimized tree structure 810-2 shown in FIG. 8, the data of the leaf node 330-2 represents a determined optimized candidate layout, and the data of the ancestor nodes 310, 320-1, 320-2 of the leaf node 330-2 Respectively denote partial layouts used to obtain the optimized candidate layout. In some embodiments, the electronic device 220 may also store an optimization evaluation result associated with the optimized candidate layout, eg, 1.5, together with the optimized candidate layout at the leaf node 330-2. This disclosure does not limit this. The electronic device 220 can use the constructed optimized tree structure to update the current reference tree structure, so that in the subsequent process of determining another optimized candidate layout, all candidate layouts that have been explored before can be considered, so as to improve the finding and evaluation results. The likelihood of candidate layouts for .

Then, the method 600 returns to block 604, and the electronic device 220 continues to iteratively determine additional optimized candidate layouts and their optimized evaluation results in the manner described above. If at block 608 it is determined that the layout termination condition is met, then method 600 ends.

FIG. 7 shows a flowchart of a method 700 for determining an optimization candidate layout according to some embodiments of the present disclosure. For example, method 700 may be implemented as an example of block 604 as shown in FIG. 6 . In some embodiments, the method 700 may be executed by the electronic device 220 as shown in FIG. 2 . It should be appreciated that method 700 may also include additional blocks not shown and/or blocks shown may be omitted, and that the scope of the present disclosure is not limited in this regard.

In block 702 , the electronic device 220 sets one first circuit unit 340 among the plurality of first circuit units 340 as a unit to be arranged based on a predetermined arrangement order. Referring to FIG. 8 , the electronic device 220 sets the first circuit unit 340 - 1 having the largest area as a unit to be arranged in the predetermined arrangement order based on area as described above in connection with FIG. 5 .

In block 704, the electronic device 220 determines an updated arrangement of the chip based on the reference tree structure, the current arrangement of the chip, and the units to be arranged, wherein the updated arrangement includes the unit to be arranged and the previously arranged ones of the plurality of first circuit units 340 The layout of the first circuit unit 340 .

In some embodiments, the electronic device 220 determines the set of candidate arrangements based on the current arrangement of the chips. For example, the electronic device 220 may determine an unoccupied area in the area to be arranged according to the current arrangement, and determine at least one candidate position in which the unit to be arranged can be arranged according to the area information of the unit to be arranged, so as to determine that the at least one candidate A set of arrangements is also called a candidate arrangement set. Here, the candidate arrangement associated with a candidate position may indicate: based on the current arrangement, an arrangement manner obtained by arranging the units to be arranged at the candidate position. It should be understood that the set of candidate arrangements may also be determined in any other suitable manner. This disclosure does not limit this.

For the purpose of illustration, it is assumed in the following description about FIG. 7 that the current reference tree structure corresponds to the tree structure 810-2 shown in FIG. Arrangement in the manner indicated by -1, that is, the current arrangement of the chip corresponds to the node 320-1, and the unit to be arranged is the first circuit unit 340-2. Exemplarily, based on the current layout and the area information of the first circuit unit 340-2, the electronic device 220 may determine two possible different candidate layouts, wherein the first candidate layout corresponds to the part represented by the child node 320-2 of the current layout layout, and the second candidate layout corresponds to the partial layout represented by node 320-3. It should be noted that since the node 320-3 has not been used to represent the partial layout in the previous layout process, the node 320-3 represents that the partial layout has not been included in the tree structure 810-2 at this time.

In some embodiments, in order to select a suitable candidate arrangement from the candidate arrangement set, the electronic device 220 may determine an evaluation set associated with the candidate arrangement set based on the reference tree structure. For example, the set of reviews includes a first review associated with a first candidate arrangement and a second review associated with a second candidate arrangement.

In some embodiments, for the first candidate arrangement included in the current parameter tree structure, the electronic device 220 may calculate the first evaluation based on the following formula (1):

Among them, A represents the first candidate arrangement to be evaluated; R1(A) represents the first evaluation associated with the first candidate arrangement A; Q(A) represents the evaluation result of the candidate layout associated with the first candidate arrangement A The first mean value, wherein the candidate layout associated with the first candidate arrangement A includes the candidate layout corresponding to the leaf node 330 of the first candidate arrangement A; c represents the exploration factor; P(A) represents that associated with the first candidate arrangement A N(A) represents the number of times the first candidate arrangement A is visited; and N(S) represents the number of times the current arrangement is visited.

Exemplarily, for the reference tree structure 810-2, if the first candidate arrangement A corresponds to the partial layout represented by the child node 320-2 of the current arrangement, then Q(A) corresponds to the leaf node 330 of the first candidate arrangement A The average of the evaluation results 1.2 and 1.5 of the candidate layouts corresponding to -1 and 330-2 is 1.35; N(A) corresponds to the number of times the first candidate layout A is visited, that is, the number of times node 320-2 is visited 2; N(S ) corresponds to the number of times the current arrangement is visited, that is, the number of times node 340-1 is visited 2.

In some embodiments, in Equation (1), the first mean value Q(A) indicates the average evaluation result of the candidate layouts previously obtained using the first candidate layout A, so that The average quality of the candidate layouts obtained by arrangement A. first weighted value

Compensation may be made for candidate arrangements that have been visited less times before, so as to prevent the electronic device 220 from ignoring such candidate arrangements when selecting. Therefore, the first evaluation R1(A) enables the electronic device 220 to fully and comprehensively evaluate the first candidate layout A, thereby helping to determine the most suitable candidate layout, and improving the possibility of finding an optimized candidate layout with a better evaluation result .

In some embodiments, the exploration factor c is a constant and can be preset by the user. By setting a relatively large exploration factor c, a relatively large first weighted value can be obtained

In this case, the candidate arrangement that has been visited less times before will get a relatively higher evaluation, so that the electronic device 220 is more inclined to use the candidate arrangement that has been visited less times before, that is, it is more inclined to explore new candidate arrangements. layout. In contrast, by setting a relatively small exploration factor c, a relatively small first weighted value can be obtained

In this case, the candidate arrangement that has been visited less times before will get a relatively lower evaluation, so that the electronic device 220 is more inclined to use the candidate arrangement that has been visited more times before, that is, it is more inclined to use the known Candidate placement. In some embodiments, the exploration factor may adopt a default value. This disclosure does not limit this.

In some embodiments, the electronic device 220 may obtain the probability set associated with the candidate arrangement set based on the current arrangement. In some embodiments, the electronic device 220 may determine the probability set by means of a neural network. The electronic device 220 takes information such as the netlist data 210 , the current arrangement and the units to be arranged as the input of the neural network. The neural network encodes the input data to generate an embedding (embedding), and encodes the generated embedding, and outputs the candidate arrangement set through a subnetwork composed of a deconvolution layer and a batch normalization layer included in the neural network. Associated set of probabilities. The first probability P(A) in the set of probabilities indicates the probability that a corresponding first candidate arrangement A in the set of candidate arrangements is selected. In some embodiments, the electronic device 220 can also train the neural network by means of a reinforcement learning algorithm, so as to improve the prediction performance of the neural network. Here, the reward used in the reinforcement learning can also be determined based on the aforementioned evaluation indicators such as line length, congestion, maximum delay, and total delay. It should be understood that the electronic device 220 may also determine the probability set associated with the candidate arrangement set in any other suitable manner, which is not limited in the present disclosure. It should also be understood that, in some embodiments, the first probability P(A) in formula (1) may also be omitted, that is, the first probability P(A) is not an essential element of the solution according to the present disclosure.

It should be understood that although one specific evaluation method for the first candidate arrangement is shown in equation (1), any other suitable evaluation method may also be used. This disclosure does not limit this.

In some embodiments, for the second candidate arrangement not included in the current parameter tree structure, the electronic device 220 may calculate the second evaluation based on the following formula (2):

Wherein, B represents the second candidate arrangement to be evaluated; R2(B) represents the second evaluation associated with the second candidate arrangement B; T(B) represents the evaluation of the candidate layouts corresponding to all leaf nodes 330 of the reference tree structure The second mean of the results; c represents the exploration factor; P(B) represents the second probability associated with the second candidate arrangement B; N(B) represents the number of times the second candidate arrangement B is visited; and N(S) represents The number of times the current layout was accessed. Since the second candidate arrangement B is not included in the current parameter tree structure, in other words, the number N(B) of the second candidate arrangement B being visited is always 0. Therefore, Equation (2) can be simplified to Equation (3) below.

Exemplarily, for the reference tree structure 810-2, if the second candidate arrangement B corresponds to the partial layout represented by the node 320-3, then T(B) corresponds to all the leaf nodes 330-1 and 330 of the current parameter tree structure The mean of the evaluation results 1.2 and 1.5 of -2 is 1.35; N(S) corresponds to the number of times the current arrangement is visited, that is, the number 2 of node 340-1 being visited.

Since the second candidate arrangement B is not included in the current parameter tree structure, there is no candidate layout associated with the second candidate arrangement B. Therefore, the second mean value T(B) is used in formula (2) to replace the first mean value Q(A) in formula (1), and the second mean value T(B) indicates all candidate layouts previously determined Average evaluation result. It should be understood that the second mean value T(B) may also be set in any other suitable manner, for example, set as the average evaluation result of the five recently determined candidate layouts. This disclosure does not limit this. In this way, the first evaluation and the second evaluation can be made comparable, which helps to determine the most suitable candidate layout by comparing the evaluation results of each candidate layout, and improves the efficiency of finding optimized candidate layouts with better evaluation results. possibility.

second weighted value

Compensation may be performed for the second candidate arrangement B that has not been visited, so as to prevent the electronic device 220 from ignoring the second candidate arrangement B during selection. Therefore, the second evaluation R2(B) enables the electronic device 220 to fully and comprehensively evaluate the second candidate arrangement, thereby helping to determine the most suitable candidate arrangement.

In some embodiments, the exploration factor c and the second probability P(B) in the formula (3) can be determined in a manner similar to that described above with reference to the formula (1), and details are not repeated here. By properly setting the exploration factor c, an appropriate balance can be achieved between exploring new candidate arrangements and utilizing known candidate arrangements. Similarly, in some embodiments, the second probability P(B) in the formulas (2) and (3) can also be omitted, that is, the second probability P(B) is not an essential element of the solution according to the present disclosure.

It should be understood that although one specific evaluation manner for the second candidate arrangement is shown in equations (2) and (3), any other suitable evaluation manner may also be used. This disclosure does not limit this.

The electronic device 220 may select an update arrangement from the set of candidate arrangements based on the evaluation set associated with the set of candidate arrangements determined in the above-described manner. In some embodiments, the electronic device 220 may select the candidate arrangement with the highest evaluation in the candidate arrangement set as the update arrangement. In some embodiments, the electronic device 220 may also convert the evaluation of each candidate arrangement into a probability of selecting the corresponding candidate arrangement according to the evaluation level of each candidate arrangement, and extract a candidate arrangement as an updated arrangement based on the converted probability. The higher the probability corresponding to a candidate arrangement is, the greater the possibility that the candidate arrangement is extracted. By considering the historical layout data in the above manner in the process of exploring candidate layouts, the solution according to the present disclosure can have better exploration capabilities, and increase the possibility of finding candidate layouts with better evaluation results, thereby improving layout quality. It should be understood that the update arrangement may also be selected in any other suitable manner, such as based on a depth-first search or a heuristic search. This disclosure does not limit this.

Referring back to FIG. 7 , at block 706 the electronic device 220 updates the current arrangement with the updated arrangement. Exemplarily, if it is determined that the candidate arrangement corresponding to the node 320-3 is used as the updated arrangement, the current arrangement may be updated as the candidate arrangement corresponding to the node 320-3.

In block 708 , the electronic device 220 determines whether there is at least one first circuit unit 340 among the plurality of first circuit units 340 that is not included in the current arrangement. In other words, the electronic device 220 judges whether the arrangement of all the first circuit units 340 has been completed. If it is determined that at least one first circuit unit 340 of the plurality of first circuit units 340 is not included in the current arrangement, the method 700 proceeds to block 710 . In block 710 , the electronic device 220 sets a next first circuit unit 340 among the plurality of first circuit units 340 as a unit to be arranged based on a predetermined arrangement order. Exemplarily, if the current arrangement is the candidate arrangement corresponding to the node 320-3, according to the predetermined arrangement sequence based on the area as described above in conjunction with FIG. The circuit unit 340-3 is set as a unit to be arranged. Then, the method 700 returns to block 704, and the electronic device 220 continues to iteratively determine the updated arrangement of chips in the manner described above.

If at block 708 it is determined that all of the plurality of first circuit units 340 are included in the current arrangement, then the method 700 proceeds to block 712 . At block 712, the electronic device 220 determines the current arrangement of chips as an optimal candidate placement. Exemplarily, if the current arrangement is the arrangement corresponding to the node 330-3, the electronic device 220 determines that all three first circuit units 340-1, 340-2 and 340-3 have been included in the current arrangement. Therefore, the electronic device 220 may determine the arrangement corresponding to the node 330-3 as an optimized candidate arrangement. In a manner similar to that described with reference to FIG. 6 , the electronic device 220 can add the optimized candidate layout and its arrangement process data to the reference tree structure 810-2 to construct an optimized tree structure 810-3.

It can be seen from the above description in conjunction with FIGS. 2 to 8 that the method for laying out a chip according to the present disclosure can use a tree structure to organize and record historical arrangements associated with previously visited candidate layouts during the layout process. Data, by considering historical layout data in the subsequent process of exploring other candidate layouts, the method can have better exploration capabilities, and can find layout schemes with better evaluation results, thereby improving the layout quality.

Example implementations of the method according to the present disclosure have been described in detail above with reference to FIGS. 2 to 8 , and implementations of corresponding devices will be described below.

FIG. 9 shows a block diagram of an example apparatus 900 for laying out chips according to some embodiments of the present disclosure. The chip includes a plurality of first circuit units. The apparatus 900 can be used, for example, to implement electronic equipment as shown in FIG. 2 . As shown in FIG. 9 , the apparatus 900 may include an evaluation result determining module 902, which is configured to determine multiple candidate layouts of the multiple first circuit units in the chip based on the netlist data. an evaluation result, wherein the netlist data at least indicates a plurality of first circuit units and connection relationships thereof, the placement process data of the plurality of first circuit units in each of the plurality of candidate layouts is organized in a tree structure, and The plurality of candidate layouts correspond to leaf nodes of the tree structure. In addition, the apparatus 900 may further include a target layout selection module 904, configured to select a target layout from multiple candidate layouts based on multiple evaluation results.

In some embodiments, the plurality of candidate layouts may include an initial candidate layout and at least one optimized candidate layout. The evaluation result determination module 902 may include an initial evaluation result determination module for determining the initial evaluation result based on the predetermined arrangement order of the plurality of first circuit units and data indicating the connection relationship of the plurality of first circuit units in the netlist data. , determining an initial evaluation result associated with an initial candidate layout, wherein the predetermined arrangement order indicates an order in which the plurality of first circuit units are arranged according to a predetermined strategy. The evaluation result determination module 902 may further include an initial tree structure construction module configured to construct an initial tree structure based on the initial candidate layout and the arrangement process data associated with the initial candidate layout. In addition, the evaluation result determination module 902 may also include an optimization evaluation result determination module, which is used to determine at least one optimization candidate layout and at least one optimization candidate layout based on the netlist data, the initial candidate layout and the initial tree structure. At least one optimization evaluation result associated respectively.

In some embodiments, the optimization evaluation result determination module may include a reference tree structure setting module, configured to set the initial tree structure as the reference tree structure. The optimization evaluation result determination module can also include a reference tree structure update module, which is used to iteratively perform the following at least once: based on a predetermined arrangement order and a reference tree structure, determine an optimal candidate layout; based on a plurality of first circuit units indicated in the netlist data to determine the optimization evaluation result associated with an optimization candidate layout; determine whether the layout termination condition is satisfied; and if it is determined that the layout termination condition is not satisfied, based on the reference tree structure, an optimization candidate layout and an optimization The layout process data associated with the candidate layouts is used to build an optimized tree structure to update the reference tree structure.

In some embodiments, the reference tree structure update module is further used to: set one of the plurality of first circuit units as a unit to be arranged based on a predetermined arrangement sequence; iteratively perform the following at least once: based on the reference tree structure, the current layout of the chip and the unit to be arranged, and determine the updated layout of the chip, wherein the updated layout includes the layout of the first circuit unit that has been previously arranged in the unit to be arranged and a plurality of first circuit units; using the updated layout to update the current arrangement; determine whether there is at least one first circuit unit in the plurality of first circuit units that is not included in the current arrangement; and if it is determined that at least one first circuit unit in the plurality of first circuit units is not included in In the current arrangement, based on a predetermined arrangement order, setting the next first circuit unit among the plurality of first circuit units as the unit to be arranged; and determining the current arrangement of the chip as an optimized candidate layout.

In some embodiments, the reference tree structure update module is further used to: determine a candidate arrangement set based on the current arrangement, the candidate arrangement set includes at least one of the following items: a first candidate arrangement corresponding to a child node of the current arrangement, and by adding a second candidate arrangement obtained by the unit to be arranged to the current arrangement, wherein the second candidate arrangement is different from the first candidate arrangement; based on the reference tree structure, determining an evaluation set associated with the candidate arrangement set; and based on the evaluation set, selecting from the candidate arrangement Focus on selecting the update layout.

In some embodiments, the reference tree structure update module is further configured to: calculate a first mean value of evaluation results of candidate layouts associated with the first candidate layout; determine a first weight based on the number of times the first candidate layout and the current layout are visited value; obtain a probability set associated with the set of candidate arrangements; and determine the evaluation set associated with the first candidate arrangement based on the first mean value, the first weighted value, and the first probability associated with the first candidate arrangement in the probability set A first evaluation, wherein the candidate layouts associated with the first candidate arrangement include candidate layouts corresponding to leaf nodes of the first candidate arrangement.

In some embodiments, the reference tree structure update module is further used to: calculate the second mean value of the evaluation results of the candidate layouts corresponding to all the leaf nodes of the reference tree structure; weighted value; obtaining a probability set associated with the set of candidate arrangements; and based on a second mean value, a second weighted value, and a second probability associated with the second candidate arrangement in the probability set, determine the probability set associated with the second candidate arrangement in the evaluation set Union's second evaluation.

In some embodiments, the layout termination condition includes at least one of the following: the number of multiple candidate layouts reaches a predetermined number threshold; and the duration of iterations reaches a predetermined time threshold.

In some embodiments, the chip may further include at least one second circuit unit. The netlist data may also indicate the connection relationship between the at least one second circuit unit and the plurality of first circuit units. The evaluation result determination module 902 may include a complete layout determination module, configured to determine a complete layout associated with a candidate layout based on the netlist data and a candidate layout among the multiple candidate layouts, the complete layout indicating at least a plurality of first circuit units and the arrangement and wiring of at least one second circuit unit. In addition, the evaluation result determining module 902 may further include a complete evaluation result determining module, configured to determine a complete evaluation result associated with a complete layout, so as to determine an evaluation result associated with a candidate layout among multiple evaluation results.

In some embodiments, the evaluation result is determined based on at least one of: line length, congestion, maximum delay or total delay.

The modules and/or units included in the device 900 may be implemented in various ways, including software, hardware, firmware or any combination thereof. In some embodiments, one or more units may be implemented using software and/or firmware, such as machine-executable instructions stored on a storage medium. In addition to or instead of machine-executable instructions, some or all of the units in apparatus 900 may be at least partially implemented by one or more hardware logic components. Exemplary types of hardware logic components that may be used include, by way of example and not limitation, Field Programmable Gate Arrays (FPGAs), Application Specific Integrated Circuits (ASICs), Application Specific Standard Products (ASSPs), System on Chips (SOCs), Complex Programmable Logic Devices (CPLD), and so on.

These modules and/or units shown in FIG. 9 may be implemented in part or in whole as hardware modules, software modules, firmware modules or any combination thereof. In particular, in some embodiments, the procedures, methods or processes described above may be implemented by hardware in the storage system or a host corresponding to the storage system or other computing devices independent of the storage system.

Fig. 10 shows a schematic block diagram of an example device 1000 that may be used to implement some embodiments of the present disclosure. The device 1000 may be used to implement an electronic device. As shown in FIG. 10 , device 1000 includes a central processing unit (CPU) 1001 that can execute instructions according to computer program instructions stored in read only memory (ROM) 1002 or loaded from storage unit 1008 into random access memory (RAM) 1003. computer program instructions to perform various appropriate actions and processes. In the RAM 1003, various programs and data necessary for the operation of the device 1000 can also be stored. The CPU 1001, ROM 1002, and RAM 1003 are connected to each other via a bus 1004. An input/output (I/O) interface 1005 is also connected to the bus 1004 .

Multiple components in the device 1000 are connected to the I/O interface 1005, including: an input unit 1006, such as a keyboard, a mouse, etc.; an output unit 1007, such as various types of displays, speakers, etc.; a storage unit 1008, such as a magnetic disk, an optical disk, etc. ; and a communication unit 1009, such as a network card, a modem, a wireless communication transceiver, and the like. The communication unit 1009 allows the device 1000 to exchange information/data with other devices through a computer network such as the Internet and/or various telecommunication networks.

The processing unit 1001 executes various methods and processes described above, such as the method 400 . For example, in some embodiments, method 400 may be implemented as a computer software program tangibly embodied on a machine-readable medium, such as storage unit 1008 . In some embodiments, part or all of the computer program may be loaded and/or installed on the device 1000 via the ROM 1002 and/or the communication unit 1009. When a computer program is loaded into RAM 1003 and executed by CPU 1001, one or more steps of method 400 described above may be performed. Alternatively, in other embodiments, the CPU 1001 may be configured to execute the method 400 in any other suitable manner (for example, by means of firmware).

The functions described herein above may be performed at least in part by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: field programmable gate array (FPGA), application specific integrated circuit (ASIC), application specific standard product (ASSP), system on a chip (SOC), load programmable logic device (CPLD), etc.

Program codes for implementing the methods of the present disclosure may be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general-purpose computer, a special purpose computer, or other programmable data processing devices, so that the program codes, when executed by the processor or controller, make the functions/functions specified in the flow diagrams and/or block diagrams Action is implemented. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media would include one or more wire-based electrical connections, portable computer discs, hard drives, random access memory (RAM), read only memory (ROM), erasable programmable read only memory (EPROM or flash memory), optical fiber, compact disk read only memory (CD-ROM), optical storage, magnetic storage, or any suitable combination of the foregoing.

In addition, while operations are depicted in a particular order, this should be understood to require that such operations be performed in the particular order shown, or in sequential order, or that all illustrated operations should be performed to achieve desirable results. Under certain circumstances, multitasking and parallel processing may be advantageous. Likewise, while the above discussion contains several specific implementation details, these should not be construed as limitations on the scope of the disclosure. Certain features that are described in the context of separate embodiments can also be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable subcombination.

Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are merely example forms of implementing the claims.

Claims

A method for laying out a chip, characterized in that the method comprises:

Based on the netlist data of the chip, determine a plurality of evaluation results respectively associated with a plurality of candidate layouts of the plurality of first circuit units in the chip in the chip, wherein among the plurality of evaluation results Each evaluation result indicates the layout quality of the corresponding candidate layout, the netlist data at least indicates the plurality of first circuit units and connection relationships thereof, and a plurality of each candidate layout in the plurality of candidate layouts The layout process data of the first circuit units is organized in a tree structure, and the plurality of candidate layouts correspond to leaf nodes of the tree structure; and

Based on the plurality of evaluation results, a target layout is selected from the plurality of candidate layouts.
The method according to claim 1, wherein the multiple candidate layouts include an initial candidate layout and at least one optimized candidate layout, and determining the multiple evaluation results comprises:

determining an initial evaluation result associated with the initial candidate layout based on a predetermined arrangement sequence of the plurality of first circuit units and data indicating a connection relationship of the plurality of first circuit units in the netlist data, wherein the predetermined arrangement order indicates the order in which the plurality of first circuit units are arranged according to a predetermined strategy;

building an initial tree structure based on the initial candidate layout and placement process data associated with the initial candidate layout; and

Based on the netlist data, the initial candidate placement, and the initial tree structure, the at least one optimized candidate placement and at least one optimization evaluation result respectively associated with the at least one optimized candidate placement are determined.
The method according to claim 2, wherein determining the at least one optimized candidate layout and the at least one optimized evaluation result comprises:

setting said initial tree structure as a reference tree structure; and

Iteratively do at least one of the following:

determining an optimal candidate layout based on the predetermined arrangement order and the reference tree structure;

determining an optimization evaluation result associated with the one optimization candidate layout based on the data indicating the connection relationship of the plurality of first circuit units in the netlist data;

determining whether a layout termination condition is satisfied; and

If it is determined that a layout termination condition is not met, an optimized tree structure is constructed to update the reference tree structure based on the reference tree structure, the one optimized candidate layout and placement process data associated with the one optimized candidate layout.
The method according to claim 3, wherein determining the one optimized candidate layout comprises:

Based on the predetermined arrangement sequence, setting one first circuit unit among the plurality of first circuit units as a unit to be arranged;

Iteratively do at least one of the following:

determining an updated arrangement of the chip based on the reference tree structure, the current arrangement of the chip, and the units to be arranged, wherein the updated arrangement includes the unit to be arranged and the plurality of first circuit units , the arrangement manner of the first circuit unit that has been arranged previously;

updating the current arrangement with the updated arrangement;

determining whether at least one first circuit unit among the plurality of first circuit units is not included in the current arrangement; and

If it is determined that at least one first circuit unit of the plurality of first circuit units is not included in the current arrangement, based on the predetermined arrangement sequence, the next first circuit unit of the plurality of first circuit units is The circuit unit is set as the unit to be arranged; and

The current arrangement of the chip is determined as the one optimized candidate arrangement.
The method of claim 4, wherein determining the update arrangement comprises:

Based on the current arrangement, a candidate arrangement set is determined, the candidate arrangement set including at least one of: a first candidate arrangement corresponding to a child node of the current arrangement, and by adding the to-be-arranged arrangement to the current arrangement a second candidate arrangement obtained by the arrangement unit, wherein the second candidate arrangement is different from the first candidate arrangement;

determining a set of evaluations associated with the set of candidate arrangements based on the reference tree structure; and

Based on the set of evaluations, the updated arrangement is selected from the set of candidate arrangements.
The method according to claim 5, wherein determining the evaluation set associated with the candidate arrangement set comprises:

calculating a first mean of evaluation results of candidate placements associated with the first candidate placement;

determining a first weighted value based on the number of times the first candidate arrangement and the current arrangement are accessed;

obtaining a set of probabilities associated with the set of candidate arrangements; and

Based on the first mean value, the first weighted value, and the first probability associated with the first candidate arrangement in the probability set, the first candidate arrangement associated with the first candidate arrangement in the evaluation set is determined. evaluating, wherein the candidate layouts associated with the first candidate arrangement include candidate layouts corresponding to leaf nodes of the first candidate arrangement.
The method according to claim 5, wherein determining the evaluation set associated with the candidate arrangement set comprises:

calculating a second mean value of evaluation results of candidate layouts corresponding to all leaf nodes of the reference tree structure;

determining a second weighted value based on the number of times the node corresponding to the current arrangement is visited;

obtaining a set of probabilities associated with the set of candidate arrangements; and

Based on the second mean value, the second weighted value, and a second probability associated with the second candidate arrangement in the set of probabilities, determining a first in the evaluation set associated with the second candidate arrangement Two evaluations.
The method according to claim 3, wherein the layout termination condition includes at least one of the following:

the number of the plurality of candidate layouts reaches a predetermined number threshold; or

The duration of the iteration reaches a predetermined time threshold.
The method according to claim 1, wherein the chip further comprises at least one second circuit unit, and the netlist data also indicates the at least one second circuit unit and the plurality of first circuit units The connection relationship, determining the plurality of evaluation results includes:

Based on the netlist data and a candidate layout of the plurality of candidate layouts, determining a complete layout associated with the one candidate layout, the complete layout indicating at least the plurality of first circuit cells and the at least arrangement and wiring of a second circuit unit; and

A complete evaluation result associated with the complete layout is determined to determine an evaluation result associated with the one candidate layout of the plurality of evaluation results.
The method according to any one of claims 1-9, wherein the evaluation result is determined based on at least one of the following: line length, congestion, maximum delay or total delay.
An electronic device for laying out a chip, characterized in that the electronic device comprises:

an evaluation result determining module, configured to determine a plurality of evaluation results respectively associated with a plurality of candidate layouts of the plurality of first circuit units in the chip in the chip based on the netlist data of the chip, Wherein each of the plurality of evaluation results indicates the layout quality of the corresponding candidate layout, the netlist data at least indicates the plurality of first circuit units and their connection relationships, and the plurality of candidate layouts The arrangement process data of the plurality of first circuit units in each candidate layout in is organized in a tree structure, and the plurality of candidate layouts correspond to leaf nodes of the tree structure; and

A target layout selection module, configured to select a target layout from the plurality of candidate layouts based on the plurality of evaluation results.
The electronic device according to claim 11, wherein the multiple candidate layouts include an initial candidate layout and at least one optimized candidate layout, and the evaluation result determination module includes:

an initial evaluation result determination module, configured to determine the initial candidates based on the predetermined arrangement sequence of the plurality of first circuit units and the data indicating the connection relationship of the plurality of first circuit units in the netlist data initial evaluation results associated with layout, wherein the predetermined arrangement order indicates an order in which the plurality of first circuit units are arranged according to a predetermined strategy;

an initial tree structure building module for building an initial tree structure based on the initial candidate layout and placement process data associated with the initial candidate layout; and

An optimization evaluation result determination module, configured to determine the at least one optimized candidate layout and at least one of the at least one optimized candidate layouts respectively associated with the at least one optimized candidate layout based on the netlist data, the initial candidate layout, and the initial tree structure Optimize evaluation results.
The electronic device according to claim 12, wherein the optimization evaluation result determining module comprises:

a reference tree structure setting module, configured to set the initial tree structure as a reference tree structure; and

A reference tree structure update module for iteratively performing at least one of the following:

determining an optimal candidate layout based on the predetermined arrangement order and the reference tree structure;

determining an optimization evaluation result associated with the one optimization candidate layout based on the data indicating the connection relationship of the plurality of first circuit units in the netlist data;

determining whether a layout termination condition is satisfied; and

If it is determined that a layout termination condition is not met, an optimized tree structure is constructed to update the reference tree structure based on the reference tree structure, the one optimized candidate layout and placement process data associated with the one optimized candidate layout.
The electronic device according to claim 13, wherein the reference tree structure updating module is further used for:

Based on the predetermined arrangement sequence, setting one first circuit unit among the plurality of first circuit units as a unit to be arranged;

Iteratively do at least one of the following:

determining an updated arrangement of the chip based on the reference tree structure, the current arrangement of the chip, and the units to be arranged, wherein the updated arrangement includes the unit to be arranged and the plurality of first circuit units , the arrangement manner of the first circuit unit that has been arranged previously;

updating the current arrangement with the updated arrangement;

determining whether at least one first circuit unit among the plurality of first circuit units is not included in the current arrangement; and

If it is determined that at least one first circuit unit of the plurality of first circuit units is not included in the current arrangement, based on the predetermined arrangement sequence, the next first circuit unit of the plurality of first circuit units is The circuit unit is set as the unit to be arranged; and

The current arrangement of the chip is determined as the one optimized candidate arrangement.
The electronic device according to claim 14, wherein the reference tree structure updating module is further used for:

Based on the current arrangement, a candidate arrangement set is determined, the candidate arrangement set including at least one of: a first candidate arrangement corresponding to a child node of the current arrangement, and by adding the to-be-arranged arrangement to the current arrangement a second candidate arrangement obtained by the arrangement unit, wherein the second candidate arrangement is different from the first candidate arrangement;

determining a set of evaluations associated with the set of candidate arrangements based on the reference tree structure; and

Based on the set of evaluations, the updated arrangement is selected from the set of candidate arrangements.
The electronic device according to claim 15, wherein the reference tree structure updating module is further used for:

calculating a first mean of evaluation results of candidate placements associated with the first candidate placement;

determining a first weighted value based on the number of times the first candidate arrangement and the current arrangement are accessed;

obtaining a set of probabilities associated with the set of candidate arrangements; and

Based on the first mean value, the first weighted value, and the first probability associated with the first candidate arrangement in the probability set, the first candidate arrangement associated with the first candidate arrangement in the evaluation set is determined. evaluating, wherein the candidate layouts associated with the first candidate arrangement include candidate layouts corresponding to leaf nodes of the first candidate arrangement.
The electronic device according to claim 15, wherein the reference tree structure updating module is further used for:

calculating a second mean value of evaluation results of candidate layouts corresponding to all leaf nodes of the reference tree structure;

determining a second weighted value based on the number of times the node corresponding to the current arrangement is visited;

obtaining a set of probabilities associated with the set of candidate arrangements; and

Based on the second mean value, the second weighted value, and a second probability associated with the second candidate arrangement in the set of probabilities, determining a first in the evaluation set associated with the second candidate arrangement Two evaluations.
The electronic device according to claim 13, wherein the layout termination condition includes at least one of the following:

the number of the plurality of candidate layouts reaches a predetermined number threshold; or

The duration of the iteration reaches a predetermined time threshold.
The electronic device according to claim 11, wherein the chip further includes at least one second circuit unit, and the netlist data also indicates that the at least one second circuit unit and the plurality of first circuit units connection relationship, the evaluation result determination module includes:

a complete layout determining module, configured to determine a complete layout associated with the one candidate layout based on the netlist data and one candidate layout among the plurality of candidate layouts, the complete layout indicating at least the plurality of first arrangement and wiring of a circuit unit and said at least one second circuit unit; and

A complete evaluation result determining module, configured to determine a complete evaluation result associated with the complete layout, so as to determine an evaluation result associated with the one candidate layout among the plurality of evaluation results.
The electronic device according to any one of claims 11-19, wherein the evaluation result is determined based on at least one of the following: line length, congestion, maximum delay or total delay.
An electronic device for laying out chips, comprising:

at least one computing unit;

at least one memory coupled to the at least one computing unit and storing instructions for execution by the at least one computing unit that, when executed by the at least one computing unit, cause the The device performs the method according to any one of claims 1-10.
A computer-readable storage medium, characterized in that the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1 to 10 is implemented.
A computer program product, characterized in that the computer program product includes computer-executable instructions, and when the computer-executable instructions are executed by a processor, the computer implements the method according to any one of claims 1 to 10. method.