CN101369294A - Plane layout planning method for SoC layout - Google Patents

Abstract

The invention provides a plane layout programming method of SoC layout based on notation and simulated annealing algorithm of B-tree. The method of the invention realizes constraint of different types of mixed module layout in SoC plane layout, aiming at connection relation, power consumption satisfaction, power network construct in practical layout, the SoC mixed layout requirement is realized. According to the layout of SoC constraint in the invention, compared with the traditional method that function punishment items are added in simulated annealing, operating time is saved and area utilance is increased.

Description

The plane layout planning method of SoC layout

Technical field

The invention belongs to the integrated circuit CAD technical field, be specifically related to geometrical constraint implementation method in a kind of SoC allocation plan.

Background technology

Development of integrated circuits is brought new problem to field of computer aided design.At first, the quick increase of chip internal line is not that very important line factor becomes restriction chip performance and chip design convergent deciding factor gradually before making.Secondly, the reduction of integrated circuit operating voltage makes the antijamming capability variation of signal, and therefore, it is more and more important that problems of Signal Integrity also becomes.And along with SOC (system on a chip) (SoC) becomes the trend of VLSI (very large scale integrated circuit) development and the main flow of following integrated circuit, traditional eda tool needs constantly to improve to adapt to the integrated circuit (IC) design needs that become increasingly complex.

Along with developing rapidly of SoC, just integrated increasing macroblock in the chip, determining of these macroblock positions is the emphasis of allocation plan.Their area occupied are big, and the line of influence is many, and the wiring delay of chip integral body and the percent of pass that connects up are all had very big influence.Especially when Number of Storage Units constantly increases, the quality of macroblock and standard block mixed layout will directly have influence on the final power consumption of chip, performance index such as speed, based on this problem, the present invention will propose the mixed layout of SoC plane layout targetedly.

List of references:

【1】Richard?Auletta，“Expert?system?perimeter?block?placement?floorplanning”，Proc.DesignAutomation?and?Test?in?Europe?conference?and?Exhibition，Vol.3，p.140-143(2004).

【2】Yuejian?Wu?and?Andre?Ivanov，“Low?Power?SoC?Memory?BIST”，Proc.The?21st?IEEEInternational?Symposium?on?Defect?and?Fault-Tolerance?in?VLSI?Systems，p.197-205(2006).

[3] Ceng Hong.The physical Design research [master thesis] of VLSI (very large scale integrated circuit) under the deep-submicron.Shanghai: Fudan University, 2005

【4】Carl?Sechen?and?Alberto?Sangiovanni-Vincentelli，“TimberWolf3.2：A?New?Standard?CellPlacement?and?Global?Routing?Package”，23rd?Design?Automation?Conference，p.432-439(1986).

【5】Yun-Chih?Chang，Yao-Wen?Chang，et?al.，“B ^*-trees：a?new?representation?for?non-slicingfloorplans”，Proc.37th?Design?Automation?Conference，p.458-463(2000).

【6】J.-M.Lin，H.-E.Yi?and?Y.-W.Chang，“Module?placement?with?boundary?constraints?usingB ^*-trees”，Proc.IEEE?Circuits，Devices?and?Systems，Vol.149，p.251-256(2002).

【7】Tung-Chieh?Chen?and?Yao-Wen?Chang，“Modern?floorplanning?based?on?B ^*-tree?and?fastsimulated?annealing”，IEEE?Transactions?on?Computer-Aided?Design?of?Integrated?Circuits?andSystems，p.637-650(2006).

【8】S.Kirkpatric，C.Gelatt?and?M.Vecchi，“Optimization?by?simulated?annealing”，Science，Vol.220，p.671-680(1983).

Summary of the invention

The objective of the invention is to realize the SoC placement algorithm of a kind of standard block and macroblock mixed layout,, and adopt simulated annealing to realize the SoC plane figure that meets the demands by the basic operation of corresponding macroblock.

For achieving the above object, technical scheme of the present invention is: a kind of plane layout planning method of SoC layout, take all standard blocks are abstracted into layout optimization basic operation algorithm behind the macroblock Ms, and the steps include:

A. the initial layout structure of a permission of random configuration;

B. at the initial layout that obtains, to B ^*In the basic operation process of-tree objective function is optimized, guarantees that simultaneously the Butut in the optimizing process all allows.

Described to B ^*The basic operation of-tree is divided into two kinds:

A. only optimize the B that carries out at irrelevance P ^*-tree operation;

B. only at the area-optimized B that carries out ^*-tree operation.

Described at the area-optimized B that carries out ^*-tree operation realizes the area optimization by rotation, insertion and deletion action.

Described the B that optimization is carried out at irrelevance P ^*-tree operation, by rotation, insertion and deletion action realize the SoC constraint, compare its insertion operation with a kind and have following Different Strategies:

A. when standard cell block Ms deflection chip left margin, if Ms is a left side, then at B ^*Insert the father node of a node among the-tree as it; If Ms is right son, then at B ^*Find a such module in the-tree rightmost branch, it is the most approaching that this module need satisfy the left side that is positioned at Ms and x coordinate and Ms module, inserts the left side of a node as this module then;

B. when standard cell block Ms deflection chip right margin, insert the left side of a node as Ms;

C. when standard cell block Ms deflection chip lower boundary, if Ms is right son, then at B ^*Insert the father node of a node among the-tree as it; If Ms is a left side, then at B ^*Find a such module in the-tree leftmost branch, it is the most approaching that this module need satisfy the top that is positioned at Ms and y coordinate and Ms module, inserts the right son of a node as this module then;

D. when standard cell block Ms deflection chip coboundary, insert the right son of a node as Ms.

Adopt the plane layout planning method of SoC layout of the present invention, have the following advantages:

(1) along with the increase of complexity, the SoC chipset has suffered increasing storage unit (ROM, RAM etc.), these storage unit not only power consumption have drawing of data line and address wire greatly but also all, add the surrounding and also have BIST (Built-In SelfTest) circuit, increased the quantity of line more, use the inventive method that their welts are placed, not only help satisfying their power consumption demand but also help passing through of backhaul connection, improved back end design convergent speed.

(2) standard block generally is to place for one group one group in the mode of lateral rows, and directly it is powered by horizontal power strip, if they are placed on the area of vacating in the middle of the chip, the wiring that not only helps macroblock is passed through, and more the design of the electric power network of rear end has brought convenience.

Description of drawings

Fig. 1 is the plane layout planning method basic operation algorithm block diagram of SoC layout of the present invention;

Fig. 2 is the plane layout planning method B of SoC layout of the present invention ^*-tree level is represented synoptic diagram;

Fig. 3 is the synoptic diagram that concerns that the plane layout planning method of SoC layout of the present invention increases the destination node father node;

Fig. 4 is that layout standard testing use-case ami33 considers that SoC retrains resultant test layout result figure;

Fig. 5 is that layout standard testing use-case ami49 considers that SoC retrains resultant test layout result figure.

Embodiment

Traditional macroblock allocation plan (BBL) problem needs input to comprise area for one group, net table link information, and the sequence of modules of various constraint conditions is satisfying realization final layout area minimum under the situation of all constraint conditions, the target that line is the shortest then.

The macroblock allocation plan problem of belt restraining can be briefly described as follows:

The input be generally a set B of forming by macroblock=M1, M2 ..., Mn}, wherein each module Mi comprises following three kinds of information:

(1) module geological information: corresponding to the length (hi) of i module, wide (wi), area (ai), judge whether the variable module that is divided into die piece (the module length and width immobilize), soft mode piece (module area is constant, and length breadth ratio can be adjusted within the specific limits) or other non-rectangles according to module length breadth ratio (τ i);

(2) module gauze information: corresponding to each module connection end sequence P1, P2 ... Pm}, and the relative position of each port in module, and with the link information of other modules;

(3) module constraint and relevant information: such as geometrical constraint (constraint etc. is concentrated in boundary constraint) and characteristic constraint (power dissipation density, voltage drop demand etc.).

Output requires the corresponding total area (A of layout result _Total) minimum, (W) is the shortest for line length, satisfies predetermined constraint conditions simultaneously.

For allocation plan, include two types module in the SoC chip: standard block (standardcells) and macroblock (IP block).In the SoC layout, the deviser generally takes the method for designing of stratification, and the experience way is: macroblock along chip welt placement all around, is placed standard block [1] so that vacate the middle most of area of chip.The benefit of doing like this is:

(1) along with the increase of complexity, the SoC chipset has suffered increasing storage unit (ROM, RAM etc.) [2], these storage unit not only power consumption have drawing of data line and address wire greatly but also all, add the surrounding and also have BIST (Built-In SelfTest) circuit, increased the quantity of line more, if their welt is placed, not only help satisfying their power consumption demand but also help passing through of backhaul connection, improved back end design convergent speed [3].

(2) standard block generally is one group one group [4] of placing of mode with lateral rows, and directly it is powered by horizontal power strip, if they are placed on the area of vacating in the middle of the chip, the wiring that not only helps macroblock is passed through, and more the design of the power grid of rear end has brought convenience.

Based on above SoC method of allocation plan, all standard blocks are abstracted into a macroblock, this macroblock and standard block have onesize area and line relation, thereby a kind of like this SoC layering placement are become the BBL layout of SoC constraint in general sense.

The definition of SoC location problem: for one group of given macroblock set B=M1, and M2 ..., Mn}, comprising the abstract standard cell block Ms that comes out, constraint requirements Ms in final layout must be surrounded by other macroblocks, and will be in the central authorities of chip as much as possible.

In order accurately to describe the position relation of Ms in entire chip, we have introduced the notion of a bias ratio P, are defined as:

(x _c-x _s)/2x _c+(y _c-y _s)/2y _c

(x wherein _s, y _s) coordinate of expression Ms module centers point, (x _c, y _c) coordinate of chip center's point behind the expression Butut.

Like this, the final optimization pass target of SoC constrained layout becomes: making total area (A _Total) minimum, line length (W) makes P trend towards zero in the time of the shortest.

At the B that analyzes layout structure ^*Can find during-tree representation, can change B by simple insertion operation ^*The coordinate of the module of child node representative among the-tree: at horizontal B ^*Among-the tree, the left filial generation table of node but the lower module of never visiting adjacent with this node module, the right son of node is corresponding to being positioned at this node module top and x coordinate module [5] identical with it.By B ^*The definition of-tree, we can by to Ms module father node or the insertion of child node operate x or the y coordinate that changes it, thereby make it be placed on chip central authorities, reach the constraint of SoC layout.For example we are to horizontal B among Fig. 2 ^*The n of-tree ₉Node is done and is inserted father node n ₁₂Operation, as shown in Figure 3, module m in the corresponding layout ₉The x coordinate increased w ₁₂, i.e. module m ₁₂Wide.

Based on this point, we have proposed at B ^*Operate the algorithm of realizing the SoC layout by insertion among the-tree to Ms father or child node.

The present invention propose based on B ^*The SoC placement algorithm of-tree as shown in Figure 1, basic thought is the initial layout structure of a permission of random configuration at first, in the basic operation of layout search, keep satisfying the layout structure of SoC constraint then with certain probability, restriction may cause the operation of constraint violation, this probability and layout satisfy the SoC constraint degree---irrelevance p is relevant.Can effectively control the transfer process that the SoC layout is represented so on the one hand, need in objective function, not increase penalty term on the other hand, the convergence reduction of avoiding so causing.Specifically, experimental procedure was mainly for two steps:

(1) the initialization layout of a permission of random configuration.Layout is known as and is allowed, and the meaning is meant that the Ms module can not satisfy the condition of boundary constraint [6].

(2) at the initial layout that obtains, to B ^*In the operating process of-tree objective function is optimized, guarantees that simultaneously the Butut in the optimizing process all allows.

In order to reach the final optimization pass target of SoC constrained layout, we are again with B ^*The basic operation of-tree is divided into two kinds:

(1) only at the area-optimized B that carries out ^*-tree operation.

(2) only optimize the B that carries out at irrelevance P ^*-tree operation.

Analyze B ^*The relation of the design feature of-tree and father and son's node, at above-mentioned at the area-optimized B that carries out ^*We realize the area optimization by rotation, insertion and deletion action in-the tree operation; And only optimize the B that carries out at irrelevance P ^*In-tree the operation, we have adopted different insertion operation strategies according to different situations:

(1) when Ms module deflection chip left margin, if Ms is a left side, then at B ^*Insert the father node of a node among the-tree as it; If Ms is right son, then at B ^*Find a such module in the-tree rightmost branch [6], it is the most approaching that this module need satisfy the left side that is positioned at Ms and x coordinate and Ms module, inserts the left side of a node as this module then.

(2) when Ms module deflection chip right margin, insert the left side of a node as Ms.

(3) when Ms module deflection chip lower boundary, if Ms is right son, then at B ^*Insert the father node of a node among the-tree as it; If Ms is a left side, then at B ^*Find a such module in the-tree leftmost branch, it is the most approaching that this module need satisfy the top that is positioned at Ms and y coordinate and Ms module, inserts the right son of a node as this module then.

(4) when Ms module deflection chip coboundary, insert the right son of a node as Ms.

The relative area Optimizing operation, the destination node that inserts in the irrelevance P Optimizing operation no longer is at random, but has one to select targetedly, therefore implements complicated a lot.But the selection majority of this target is a condition to be selected and judgement, does not relate to complex calculation, and therefore the time that increases in integral layout seldom (is seen experimental result).Under the situation that guarantees the permission Butut, guaranteed the realization of SoC constraint (P levels off to zero) when optimizing the area line length.

May cause the incomplete consideration in search volume at expression and performance constraint, we have defined new operative algorithm, guarantee that any two kinds allow can realize transforming mutually through very few basic operation between the layout, therefore can't reduce the search volume that allows layout, layout result shows that also this method has realized constrained layout preferably.The false code of algorithm is as follows:

Construct?an?initial?B ^*-tree；

Calculate?P；

Random?n；

Do

{

If(rand(0，!))

Basic?operation?for?B ^*-tree?except?insertion；

else

{

If(P<n)

do?operation?(1)；

else

do?operatiom(2)；

calculate?P；

}

}

While(run)

In above-mentioned algorithm, area-optimized operation and irrelevance P Optimizing operation are come enforcement of the judgment with certain probability, and this probability is relevant with irrelevance P, and when P was big more, the probability of carrying out irrelevance P Optimizing operation was also big more.Also promptly, when the Ms module when the distance of chip center is far away more, to B ^*The operation of-tree is to place it in the central authorities of chip for the coordinate by change Ms, thereby realizes the constraint of SoC.When P diminished gradually, the probability of area-optimized operation increased, and the Action Target of this moment mainly is for area-optimized.

Concrete layout implementation method of the present invention and step are as follows:

(1) reads layout standard testing use-case, store area, length and width, type, line and the constraint information of each module.

(2) the requirement structure according to the SoC constraint allows initial layout, and its method is: will remove standard cell block Ms other macroblock in addition and constitute a B at random ^*-tree is inserted in B with it arbitrarily as a node then on standard cell block can not satisfy the basis of boundary condition ^*Among-the tree;

(3) basic operation of the realization SoC constraint that proposes according to this paper adopts simulated annealing that area overall situation factor is optimized [8], and each module length breadth ratio is constant in optimizing process.Wherein in the simulated annealing, initial annealing temperature is 0.9, and ending annealing temperature is 0.6, and each temperature iterative search number of times is 180*N (wherein N is the test case number of modules), stops further search when search no longer restrains or reached final temperature;

(4) output relevant information and write down the result obtains the final optimization pass layout result.

Test findings:

The present invention adopts the ami33 of MCNC general in the placement algorithm in the world and ami49 as test case in the test.Consider the area and the link information that have only provided macroblock among ami33 and the aim49, feasibility for convenience of check algorithm, we have selected wherein bigger module and have replaced standard cell block, because this simplification may cause and original link information and inconsistent, thereby gauze information is left in the basket in the test of this paper, and only considers the realization of area and SoC constraint.But this does not influence the validation verification that we consider this realization layout method.We verify the 4th module among the aim33 and the 14 module among the aim49 in the test as standard cell block.

Placement algorithm of the present invention is to pass through C ⁺⁺Programming realizes that test condition is 3.4GHz Core4 Intel PC, internal memory 1G.

Test findings is shown in table one, table two, accompanying drawing 4 and accompanying drawing 5, can know and see, the layout of the SoC constraint that the present invention proposes is compared more quick effectively with tradition increases the function penalty term in simulated annealing way, not only saved operation time but also improved area utilization.

The test result of table one: Ami49 relatively

	Area (mm 2)	Working time (s)	Blank rate (%)	Bias ratio P (%)
					Only consider area-constrained non-SoC layout	37.38	20.85	5.2
Add area and bias ratio P penalty term realization SoC layout in the simulated annealing	39.15	21.65	9.5	1.7
					The SoC layout that this algorithm is realized	37.83	24.85	6.3	3.1

The test result of table two: Ami33 relatively

	Area (mm 2)	Working time (s))	Blank rate (%))	Bias ratio P (%)
					Only consider area-constrained non-SoC layout	1.20	13.36	3.5
Add area and bias ratio P penalty term realization SoC layout in the simulated annealing	1.23	16.53	6.2	0.3
					The SoC layout that this algorithm is realized	1.21	19.68	4.3	1.4

Claims (3)

1. the plane layout planning method of a SoC layout is characterized in that: it takes standard blocks all in the chip is abstracted into layout optimization basic operation algorithm behind the macroblock Ms, the steps include:

A. the initial layout structure of a permission of random configuration;

B. at the initial layout that obtains, to B ^*In the basic operation process of-tree objective function is optimized, guarantees that simultaneously the Butut in the optimizing process all allows.

2. the plane layout planning method of SoC layout as claimed in claim 1 is characterized in that: described to B ^*Insertion in the basic operation of-tree is divided into two kinds:

A. only optimize the B that carries out at irrelevance P ^*-tree inserts operation;

B. only at the area-optimized B that carries out ^*-tree inserts operation.

3. the plane layout planning method of SoC layout as claimed in claim 2 is characterized in that: optimize the B*-tree that carries out at irrelevance P for described and insert operation, have following insertion strategy:

A. when standard cell block Ms deflection chip left margin, if Ms is a left side, then at B ^*Insert the father node of a node among the-tree as it; If Ms is right son, then at B ^*Find a such module in the-tree rightmost branch, it is the most approaching that this module need satisfy the left side that is positioned at Ms and x coordinate and Ms module, inserts the left side of a node as this module then;

B. when standard cell block Ms deflection chip right margin, insert the left side of a node as Ms;

C. when standard cell block Ms deflection chip lower boundary, if Ms is right son, then at B ^*Insert the father node of a node among the-tree as it; If Ms is a left side, then at B ^*Find a such module in the-tree leftmost branch, it is the most approaching that this module need satisfy the top that is positioned at Ms and y coordinate and Ms module, inserts the right son of a node as this module then;

D. when standard cell block Ms deflection chip coboundary, insert the right son of a node as Ms.

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