CN105718702B - A kind of method in the library Def and the conversion of the library 3D integrated circuit bookshelf - Google Patents
A kind of method in the library Def and the conversion of the library 3D integrated circuit bookshelf Download PDFInfo
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- CN105718702B CN105718702B CN201610131658.5A CN201610131658A CN105718702B CN 105718702 B CN105718702 B CN 105718702B CN 201610131658 A CN201610131658 A CN 201610131658A CN 105718702 B CN105718702 B CN 105718702B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
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- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The invention discloses a kind of methods in library Def and the conversion of the library 3D integrated circuit bookshelf, are used to circuit layout carrying out subarea processing, are then used as single circuit memory stack operation；Gauze extracts and Flattening Module classifies cross-layer and logical layer line net and makees to be inserted into variable processing, and generates .nets file；Unit coordinate informations all in standard block coordinate file .place are extracted and generate .pl file by the extraction module of standard block coordinate；Standard cell size extraction module is by unit titles all in .lef file, dimension information, and the standard block title in port information and .v after example is extracted, and generates .nodes file；TSV is inserted into module, for the gauze of circuit diagram cross-layer to be converted to TSV, and is inserted into circuit layout.The library single layer integrated circuit Def is converted to the library 3D integrated circuit bookshelf by the present invention, so as to make developer under conditions of possessing single layer eda tool, carries out the test and exploitation of 3D integrated circuit.
Description
Technical field
Present invention relates in general to the design of 3D integrated circuit and manufactures, and it is integrated that more particularly, the present invention relate to 3D
Circuit layout is routed benchmark test circuit studies, belongs to circuit design field.
Background technique
In today of integrated circuit industry rapid development, with the continuous increase of traditional 2D digital integrated electronic circuit scale, spy
The appearance of other VLSI, SOC and 3D integrated circuit, the function of integrated circuit are become stronger day by day, and the complexity of internal structure is not yet
It is disconnected to improve.One single chip can integrate the level of several hundred million a transistors.More specifically, retouching as Moore's Law content
It states, technological level now has reached nanoscale.Then 3D integrated circuit (Three-Dimensional IC) become in order to
Improve one of the most promising technology that circuit performance reduces interconnection length and reduce chip power-consumption simultaneously.
With the fast development of semiconductor technology and design automation tool, the complexity of chip constantly rises, and 3D is integrated
Circuit needs the characteristics of providing more convenient and fast the Automation Design.It is more and more to design in order to shorten the Time To Market of chip
Person can also select using eda tool Computer Aided Design chip.Currently, all greatly developing 3D integrated circuit both at home and abroad, however 3D core
Piece is made up of multiple layers, and due to function, heat dissipation, energy consumption, the various problems such as cross-layer wiring, will also be had different built-in
Placement strategy.These problems can be solved by eda tool autoplacement only, could effectively shorten design time.
But the eda tool of 3D integrated circuit is still not mature enough at present, or even the Benchmarks of forming can be with not yet
The placement-and-routing of offer 3D integrated circuit and some functional tests, this causes certain resistance for the development of 3D integrated circuit
Hinder, so a set of Benchmarks of research 3D integrated circuit becomes the key for pushing the development of 3D integrated circuit technique.
And the present invention provides a kind of method, and the Def library file that traditional single layer eda tool is applied is converted to the integrated electricity of 3D
The library bookshelf on road, so as to carry out the test and exploitation of 3D integrated circuit, mention significantly under conditions of existing eda tool
High 3D IC design efficiency.
Summary of the invention
The invention aims to be directed to current 3D integrated circuit testing reference circuit immature development, and propose will be single
The library layer IC design Def is converted to a kind of method in the library 3D integrated circuit bookshelf, will be applicable to research 3D collection
At the design of the Benchmarks and 3D integrated circuit eda tool of circuit.
To achieve the above object, traditional Def library file is converted to the integrated electricity of 3D by algorithm for design and system by the present invention
The road library bookshelf, can operate cross-layer gauze, and the method for realizing insertion TSV, and the following are the tools for realizing the method for the present invention
Body step:
S1. modules are divided the system by function, be divided into circuit layout hierarchical block, gauze extract with Flattening Module,
Extraction module, standard cell size extraction module, the TSV of standard block coordinate are inserted into module.
S2.1. system inputs the circuit layout for needing to convert first, and all standard block coordinate informations of circuit layout are obtained
It takes, and calculates, obtain midpoint coordinates.
S2.2. standard block coordinate information is traversed again, compares with midpoint coordinates, domain is divided into several regions, into
Line label processing, is used as layered identification.
S3. it is extracted with gauze and Flattening Module carries out gauze flattening to the circuit block of point good layer and arranges, cross-layer is connected
The gauze name deposit array connect, and mark, mark variable is then added between cross-layer circuit, is used as cross-layer gauze and connects,
Arranging output is .nets file.
S4. in the extraction module of standard block coordinate, traverse the original standard block of domain coordinate information, and according to point
The circuit diagram of good layer compares, and the circuit number of plies has been marked behind standard block, and arranging output is .pl file.
S5. using the .lef file for having the information such as standard cell size, port and port attribute in the library DEF as defeated
Enter, positioned using regular expression, quickly by the size of the standard block in circuit, port information attribute is positioned rapidly, and will
It is .nodes file that it, which arranges output,.
S6. the name of cross-layer gauze will be put in S3 in order, and the gauze closed on is positioned, and successively according to standard around
The coordinate of unit is positioned, and is eventually formed TSV and is inserted into, and by the coordinate of the TSV of insertion, dimension information, is separately recorded in
.nodes, in .nets and .pl file.
Using single circuit domain as input, extracted and Flattening Module, standard list by circuit layout hierarchical block, gauze
The extraction module of first coordinate, standard cell size extraction module, TSV insertion module are successively converted to 3D multilayer circuit structure, and
Ultimately form the 3D circuit layout being of practical significance.
3D bookshelf library file after converting can be read in single layer EDA placement-and-routing tool, and realize layering
Layout operation has Practical significance.
A kind of method in the library Def and the conversion of the library 3D integrated circuit bookshelf, uses that steps are as follows,
A, circuit layout is divided into different regions respectively, so that single circuit is divided into four independent circuits figures,
And make stacking processing；
B, gauze is flattened, circuit layout primary and secondary module connecting node is flattened, after so that it is done circuit segmentation again, still
It so can be with actual standard unit that gauze is connected；
C, classification processing is carried out to cross-layer gauze and same layer gauze, and institute's cross-layer label is done to cross-layer gauze, be inserted into ttsv
Variable does layout for insertion TSV and prepares；
D, respectively by standard cell size, the information interceptions such as coordinate simultaneously are made to arrange output；
E, finally according to the positioning of ttsv, distributed intelligence with standard block around calculates the insertion position TSV, insertion
TSV。
The method of the partitioning circuitry are as follows: all standard block coordinates of circuit are compared, calculating is most worth, and confirms rectangle
The coordinate at several angles of circuit layout.Rectangle midpoint coordinates is confirmed according to this four coordinates, and more circuit layout is divided at midpoint
Area.
The algorithm of the gauze flattening is, by the port of the standard block, module that are connected on every gauze, direction
(input, output, inout) is all extracted and is marked, and then erases module name, is flattening gauze by the processing of level gauze, has
Conducive to the extraction of gauze.
In the bookshelf file format of all outputs, joined in .nodes file after eda tool example unit name with
Institute's connecting line user name joined gauze example assumed name in .nets file, and also joined port and the institute of gauze institute connection unit
In the information of the module of circuit.
The coordinate information that ttsv location variable needs to refer to three standard blocks near upper and lower level is calculated, by calculating, and
It obtains TSV and is actually inserted into coordinate, to realize that TSV is inserted into.
The information for needing to calculate upper layer and lower layer standard block simultaneously needs to sit last time after finding suitable three coordinates
After mark projection, a virtual triangle is connected.And the position for being actually inserted into the point of the line of three points intersection as TSV
Point.
The present invention can obtain following effect:
It is 3D multilayered structure in the bookshelf format that the present invention is converted into, it can be the integrated electricity of traditional single layer
Road is converted into 3D multilayer bookshel structure, and is used to study the test benchmark circuit of 3D integrated circuit.
Detailed description of the invention
Fig. 1 is the schematic diagram of system modules.
Fig. 2 is the flow chart of circuit layout hierarchical block of the present invention work.
Fig. 3 is the schematic diagram that circuit layout hierarchical block carries out circuit layering.
Fig. 4 is that gauze extracts and Flattening Module work flow diagram.
Fig. 5 is final result schematic diagram of the present invention.
Specific embodiment
Below with reference to attached drawing, the invention will be further described.
Fig. 1 is the schematic diagram of present system module, is followed successively by circuit layout hierarchical block, line according to processing sequence is executed
Net extracts and Flattening Module, the extraction module of standard block coordinate, and standard cell size extraction module and TSV are inserted into module.
Fig. 2 is the flow chart of the work of circuit layout hierarchical block, first inputs the library Def .v netlist, obtains coordinate value, is calculated
Midpoint coordinates.And the coordinate of standard block is traversed as reference according to the coordinate at midpoint, by comparing, circuit layout is divided into
Tetra- parts L1, L2, L3, L4.
Fig. 3 is after passing through circuit layout hierarchical block, to carry out the schematic diagram of circuit layering.
After Fig. 4 is circuit layout subregion, the gauze connected originally is arranged and is classified, by cross-layer gauze with for
Same layer gauze first separates, and then arranges cross-layer gauze, and the initial layers label and termination that online online mark is crossed over
The label of layer, and variable ttsv is all inserted on the layer of each leap, basis is done to be inserted into practical TSV in next step.
Fig. 5 is the schematic diagram of the done achievement of the present invention, and the left side is the planar circuit schematic diagram in the library Def, and the right is 3D's
The library bookshelf schematic diagram.
Claims (9)
1. a kind of method in library Def and the conversion of the library 3D integrated circuit bookshelf, it is characterised in that: this method specific steps are such as
Under,
S1. the library Def and the library 3D integrated circuit bookshelf are divided into modules by function, be divided into circuit layout hierarchical block,
Gauze, which is extracted, is inserted into module with Flattening Module, the extraction module of standard block coordinate, standard cell size extraction module, TSV；
The library S2.1.Def and the library 3D integrated circuit bookshelf input the circuit layout for needing to convert first, by circuit layout institute
There is the acquisition of standard block coordinate information, and calculate, obtains midpoint coordinates；
S2.2. standard block coordinate information is traversed again, compares with midpoint coordinates, domain is divided into several regions, is marked
Number processing, be used as layered identification；
S3. it is extracted with gauze and Flattening Module carries out gauze flattening to the circuit layout of point good layer and arranges, by parallel link
Gauze name is stored in array, and marks, and mark variable is then added between cross-layer circuit, is used as cross-layer gauze and connects, arranges
Output is .nets file；
S4. in the extraction module of standard block coordinate, the coordinate information of the original standard block of domain is traversed, and according to a point good layer
Circuit layout compare, the circuit number of plies has been marked behind standard block, and arrange output be .pl file；
S5. it using the .lef file for having standard cell size, port and port attribute information in the library DEF as input, utilizes
Regular expression positioning, quickly by the size of the standard block in circuit, port information attribute is positioned rapidly, and is arranged defeated
It is out .nodes file；
S6. the name of cross-layer gauze will be put in S3 in order, and the gauze closed on is positioned, and successively according to standard block around
Coordinate positioned, eventually form TSV and be inserted into, and by the coordinate of the TSV of insertion, dimension information, be separately recorded in
.nodes, in .nets and .pl file.
2. the method in a kind of library Def according to claim 1 and the conversion of the library 3D integrated circuit bookshelf, feature exist
In: using single circuit domain as input, is extracted by circuit layout hierarchical block, gauze and sat with Flattening Module, standard block
Target extraction module, standard cell size extraction module, TSV insertion module are successively converted to 3D multilayer circuit structure, and final
Form the 3D circuit layout being of practical significance.
3. the method in a kind of library Def according to claim 1 and the conversion of the library 3D integrated circuit bookshelf, feature exist
In: the 3D bookshelf library file after converting can be read in single layer EDA placement-and-routing tool, and realize that hierarchical layout grasps
Make.
4. the method in a kind of library Def according to claim 1 and the conversion of the library 3D integrated circuit bookshelf, feature exist
In: the used step refinement of this method is as follows,
A, circuit layout is divided into different regions respectively, so that single circuit is divided into four independent circuits figures, and is made
Stacking processing；
B, gauze is flattened, circuit layout primary and secondary module connecting node is flattened, after so that it is done circuit segmentation again, still may be used
The actual standard unit connected with gauze；
C, classification processing is carried out to cross-layer gauze and same layer gauze, and institute's cross-layer label is done to cross-layer gauze, be inserted into ttsv variable,
Layout is done for insertion TSV to prepare；
D, respectively by standard cell size, coordinate information intercepts and makees to arrange output；
E, finally according to the positioning of ttsv, distributed intelligence with standard block around calculates the insertion position TSV, is inserted into TSV.
5. the method in a kind of library Def according to claim 4 and the conversion of the library 3D integrated circuit bookshelf, feature exist
In: the method for the partitioning circuitry are as follows: all standard block coordinates of circuit are compared, calculating is most worth, and confirms rectangular circuit
The coordinate at several angles of domain；Rectangle midpoint coordinateies are confirmed according to this four coordinates, and according to midpoint by circuit layout subregion.
6. the method in a kind of library Def according to claim 4 and the conversion of the library 3D integrated circuit bookshelf, feature exist
In: the algorithm of the gauze flattening is, by the port of the standard block, module that are connected on every gauze, direction input, side
It all extracts and marks to output, direction inout, then erase module name, be flattening gauze by the processing of level gauze, favorably
In the extraction of gauze.
7. the method in a kind of library Def according to claim 4 and the conversion of the library 3D integrated circuit bookshelf, feature exist
In: in the bookshelf file format of all outputs, it joined unit name and company of institute after eda tool example in .nodes file
Wiring user name joined gauze example assumed name in .nets file, and also joined port and the place electricity of gauze institute connection unit
The information of the module on road.
8. the method in a kind of library Def according to claim 4 and the conversion of the library 3D integrated circuit bookshelf, feature exist
In: calculating ttsv location variable needs to refer to the coordinate information of three standard blocks near upper and lower level, by calculating, and obtains
TSV is actually inserted into coordinate, to realize that TSV is inserted into.
9. the method in a kind of library Def according to claim 4 and the conversion of the library 3D integrated circuit bookshelf, feature exist
In: the information of upper layer and lower layer standard block is needed while being calculated, after finding three coordinates, needs to connect after coordinate projection
One virtual triangle；And the location point for being actually inserted into the point of the line of three points intersection as TSV.
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| CN106650136B (en) * | 2016-12-29 | 2020-06-02 | 北京华大九天软件有限公司 | Method for checking standard unit function consistency of time sequence library and netlist library |
| CN115392160B (en) * | 2022-06-10 | 2024-04-09 | 无锡芯光互连技术研究院有限公司 | Format conversion method for circuit diagram description file |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103548131A (en) * | 2011-05-05 | 2014-01-29 | 国际商业机器公司 | 3-D integration using multi stage vias |
| CN104576637A (en) * | 2013-10-17 | 2015-04-29 | 台湾积体电路制造股份有限公司 | 3D Integrated Circuit and Methods of Forming Same |
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| US7843064B2 (en) * | 2007-12-21 | 2010-11-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and process for the formation of TSVs |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103548131A (en) * | 2011-05-05 | 2014-01-29 | 国际商业机器公司 | 3-D integration using multi stage vias |
| CN104576637A (en) * | 2013-10-17 | 2015-04-29 | 台湾积体电路制造股份有限公司 | 3D Integrated Circuit and Methods of Forming Same |
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