CN105718702A - Method for converting Def library and 3D integrated circuit bookshelf library - Google Patents
Method for converting Def library and 3D integrated circuit bookshelf library Download PDFInfo
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- CN105718702A CN105718702A CN201610131658.5A CN201610131658A CN105718702A CN 105718702 A CN105718702 A CN 105718702A CN 201610131658 A CN201610131658 A CN 201610131658A CN 105718702 A CN105718702 A CN 105718702A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
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Abstract
The invention discloses a method for converting a Def library and a 3D integrated circuit bookshelf library. The method comprises the following steps: performing partitioned processing on a circuit layout, and then enabling the circuit layout to perform memory stacking operation as a single-layer circuit; classifying cross layers and communicated-layer nets by use of a net extraction and expansion module, performing insert variable treatment, and generating a .nets file; extracting all unit coordinate information in a standard unit coordinate file .place by use of a standard unit coordinate extraction module, and generating a .pl file; extracting all unit names, size information, port information and standard unit names subjected to .v universal instantiation in a .lef file by use of a standard unit size extraction unit, and generating a .nodes file; and converting a net of circuit layout cross layers into TSV by use of a TSV insert module, and inserting the TSV into the circuit layout. According to the method, the single-layer integrated circuit Def library is converted into the 3D integrated circuit bookshelf library, so that a developer can perform 3D integrated circuit test and development under a condition of having a single-layer EDA tool.
Description
Technical field
Present invention relates in general to the design of 3D integrated circuit and manufacture, more particularly, the present invention relate to 3D integrated circuit layout wiring benchmark test circuit studies, belong to circuit design field.
Background technology
In today that integrated circuit industry develops rapidly, along with the continuous increase of tradition 2D digital integrated electronic circuit scale, the appearance of special VLSI, SOC and 3D integrated circuit, the function of integrated circuit is become stronger day by day, and the complexity of its internal structure also improves constantly.One single chip can the level of integrated several hundred million transistors.More specifically, as the description of Moore's Law content, technological level now has reached nanoscale.Then 3D integrated circuit (Three-DimensionalIC) just becomes raising circuit performance and reduces one of interconnection length the most promising technology reducing chip power-consumption simultaneously.
Along with the fast development of semiconductor technology and design automation tool, the complexity of chip constantly rises, and 3D integrated circuit needs to provide the feature of the Automation Design more easily.In order to shorten the Time To Market of chip, increasing designer also can select to use eda tool Aided Design chip.At present, all greatly develop 3D integrated circuit both at home and abroad, but 3D chip is being made up of multilamellar, and due to various problems such as function, heat radiation, energy consumption, cross-layer wirings, also will have different built-in placement strategies.Only these problems all can be solved by eda tool autoplacement, could effectively shorten the design time.
But, the eda tool of current 3D integrated circuit is still not mature enough, placement-and-routing and some functional tests of 3D integrated circuit even can be provided but without the Benchmarks shaped, this causes certain obstruction for the development of 3D integrated circuit, so a set of Benchmarks of research 3D integrated circuit becomes the key promoting the development of 3D integrated circuit technique.
And the present invention provides a kind of method, the Def library file of traditional monolayer eda tool application is converted to the bookshelf storehouse of 3D integrated circuit, it is thus possible to when existing eda tool, carry out test and the exploitation of 3D integrated circuit, it is greatly improved 3D IC design efficiency.
Summary of the invention
The invention aims to for current 3D integrated circuit testing reference circuit immature development, and a kind of method that monolayer IC design Def storehouse is converted to 3D integrated circuit bookshelf storehouse proposed, its design that will be applicable to study Benchmarks and the 3D integrated circuit eda tool of 3D integrated circuit.
For achieving the above object, the present invention passes through algorithm for design and system, and tradition Def library file is converted to 3D integrated circuit bookshelf storehouse, operable for cross-layer gauze, and realizes the method inserting TSV, below for realizing the concrete steps of the inventive method:
S1. divide the system into modules by function, be divided into circuit layout hierarchical block, gauze to extract and insert module with Flattening Module, the extraction module of standard block coordinate, standard cell size extraction module, TSV.
S2.1. first system inputs the circuit layout needing conversion, is obtained by all for circuit layout standard block coordinate informations, and calculates, draws middle point coordinates.
S2.2. again travel through standard block coordinate information, compare with middle point coordinates, domain is divided into some regions, carries out label process, as layered identification.
S3. extract with gauze and with Flattening Module, the circuit block of point good layer is carried out gauze flattening and arranges, the gauze name of parallel link is stored in array, and marks, between cross-layer circuit, then add mark variable, connect as cross-layer gauze, arrange and be output as .nets file.
S4. in the extraction module of standard block coordinate, the coordinate information of the traversal original standard block of domain, and contrast according to the circuit diagram dividing good layer, after standard block, mark the circuit number of plies, and arrangement has been output as .pl file.
S5. using the .lef file that has the information such as standard cell size, port and port attribute in DEF storehouse as input, regular expression is utilized to position, quickly by the size of the standard block in circuit, port information attribute positions rapidly, and is arranged and be output as .nodes file.
S6. S3 will put the name of cross-layer gauze in order, and positioned by the gauze closed on, and successively coordinate according to standard block around positions, and eventually forms TSV and inserts, and by the coordinate of TSV inserted, dimension information, be separately recorded in .nodes .nets and .pl file.
Using monolayer circuit layout as input, extracted by circuit layout hierarchical block, gauze and be converted to 3D multilayer circuit structure successively with Flattening Module, the extraction module of standard block coordinate, standard cell size extraction module, TSV insertion module, and ultimately form the 3D circuit layout being of practical significance.
3Dbookshelf library file after being changed can read in monolayer EDA placement-and-routing instrument, and realizes hierarchical layout's operation, has Practical significance.
A kind of method that Def storehouse is changed with 3D integrated circuit bookshelf storehouse, its adopted step is as follows,
A, respectively circuit layout being divided into different regions, thus monolayer circuit being divided into four independent circuits figure, and doing stacking process；
B, gauze is flattened, circuit layout primary and secondary module connecting joint point is flattened so that it is after doing circuit segmentation again, still can the actual standard unit that connects of gauze；
C, carry out classification process to cross-layer gauze with layer line net, and cross-layer gauze is done institute's cross-layer label, insert ttsv variable, do layout prepare for inserting TSV；
D, respectively by standard cell size, the information interception such as coordinate also is made to arrange output；
E, the final location according to ttsv, with the distributed intelligence of standard block around, calculating TSV on position, insertion TSV.
The method of described partitioning circuitry is: is compared by all for circuit standard block coordinates, calculates and be worth most, confirms the coordinate at several angles of rectangular circuit domain.Confirm point coordinates in rectangles according to these four coordinates, and more midpoint by circuit layout subregion.
The algorithm that described gauze flattens is, by the port of the standard block connected on every gauze, module, direction (input, output, inout) all extracts and marks, and is then erased by module name, level gauze is processed as flattening gauze, is conducive to the extraction of gauze.
In the bookshelf file format of all outputs, .nodes, file adds unit name and institute's connecting line user name after eda instrument example, .nets, file adds gauze example assumed name, and also adds the information of the port of the connected unit of gauze and the module of place circuit.
Calculate ttsv location variable and need to refer to the coordinate information of three standard blocks near levels, by calculating, and obtaining TSV and be actually inserted into coordinate, inserting thus realizing TSV.
Need to calculate the information of upper and lower two-layer standard block, after finding suitable three coordinate, it is necessary to by after last time coordinate projection, connect a virtual triangle simultaneously.And the point intersected by the line of three points is as the TSV location point being actually inserted into.
The present invention can obtain following effect:
The bookshelf form converted in the present invention is 3D multiple structure, it is possible to traditional monolayer integrated circuit is converted into 3D multilamellar bookshel structure, and is used for studying the test benchmark circuit of 3D integrated circuit.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of system modules.
Fig. 2 is the flow chart of circuit layout hierarchical block of the present invention work.
Fig. 3 is the schematic diagram that circuit layout hierarchical block carries out circuit layering.
Fig. 4 is that gauze extracts and Flattening Module workflow diagram.
Fig. 5 is final result schematic diagram of the present invention.
Detailed description of the invention
Below with reference to accompanying drawing, the invention will be further described.
Fig. 1 is the schematic diagram of present system module, is followed successively by circuit layout hierarchical block according to performing processing sequence, and gauze extracts and Flattening Module, the extraction module of standard block coordinate, and standard cell size extraction module and TSV insert module.
Fig. 2 is the flow chart of the work of circuit layout hierarchical block, and first input Def storehouse .v netlist, obtains coordinate figure, point coordinates in calculating.And according to the coordinate at midpoint as reference, the coordinate of traversal standard block, by comparing, circuit layout is divided into tetra-parts of L1, L2, L3, L4.
Fig. 3 is by, after circuit layout hierarchical block, carrying out the schematic diagram of circuit layering.
After Fig. 4 is circuit layout subregion, undertaken arranging by the gauze originally connected and classify, by cross-layer gauze with for first to separate with layer line net, then cross-layer gauze is arranged, and mark the label of initial layers label and the termination layer crossed over online on the net, and on the layer of each leap, it is all inserted into variable ttsv, insert actual TSV for next step and do basis.
Fig. 5 is the schematic diagram of the done achievement of the present invention, and the left side is the planar circuit schematic diagram in Def storehouse, and the right is the bookshelf storehouse schematic diagram of 3D.
Claims (9)
1. the method that a Def storehouse is changed with 3D integrated circuit bookshelf storehouse, it is characterised in that: the method comprises the following steps that,
S1. divide the system into modules by function, be divided into circuit layout hierarchical block, gauze to extract and insert module with Flattening Module, the extraction module of standard block coordinate, standard cell size extraction module, TSV；
S2.1. first system inputs the circuit layout needing conversion, is obtained by all for circuit layout standard block coordinate informations, and calculates, draws middle point coordinates；
S2.2. again travel through standard block coordinate information, compare with middle point coordinates, domain is divided into some regions, carries out label process, as layered identification；
S3. extract with gauze and with Flattening Module, the circuit block of point good layer is carried out gauze flattening and arranges, the gauze name of parallel link is stored in array, and marks, between cross-layer circuit, then add mark variable, connect as cross-layer gauze, arrange and be output as .nets file；
S4. in the extraction module of standard block coordinate, the coordinate information of the traversal original standard block of domain, and contrast according to the circuit diagram dividing good layer, after standard block, mark the circuit number of plies, and arrangement has been output as .pl file；
S5. using the .lef file that has the information such as standard cell size, port and port attribute in DEF storehouse as input, regular expression is utilized to position, quickly by the size of the standard block in circuit, port information attribute positions rapidly, and is arranged and be output as .nodes file；
S6. S3 will put the name of cross-layer gauze in order, and positioned by the gauze closed on, and successively coordinate according to standard block around positions, and eventually forms TSV and inserts, and by the coordinate of TSV inserted, dimension information, be separately recorded in .nodes .nets and .pl file.
2. the method that a kind of Def storehouse according to claim 1 is changed with 3D integrated circuit bookshelf storehouse, it is characterized in that: using monolayer circuit layout as input, extracted by circuit layout hierarchical block, gauze and be converted to 3D multilayer circuit structure successively with Flattening Module, the extraction module of standard block coordinate, standard cell size extraction module, TSV insertion module, and ultimately form the 3D circuit layout being of practical significance.
3. the method for a kind of Def storehouse according to claim 1 and 3D integrated circuit bookshelf storehouse conversion, it is characterised in that: the 3Dbookshelf library file after change can reading in monolayer EDA placement-and-routing instrument, and realize hierarchical layout and operate.
4. the method that a kind of Def storehouse according to claim 1 is changed with 3D integrated circuit bookshelf storehouse, it is characterised in that: the refinement of this method adopted step is as follows,
A, respectively circuit layout being divided into different regions, thus monolayer circuit being divided into four independent circuits figure, and doing stacking process；
B, gauze is flattened, circuit layout primary and secondary module connecting joint point is flattened so that it is after doing circuit segmentation again, still can the actual standard unit that connects of gauze；
C, carry out classification process to cross-layer gauze with layer line net, and cross-layer gauze is done institute's cross-layer label, insert ttsv variable, do layout prepare for inserting TSV；
D, respectively by standard cell size, the information interception such as coordinate also is made to arrange output；
E, the final location according to ttsv, with the distributed intelligence of standard block around, calculating TSV on position, insertion TSV.
5. the method that a kind of Def storehouse according to claim 4 is changed with 3D integrated circuit bookshelf storehouse, it is characterized in that: the method for described partitioning circuitry is: all for circuit standard block coordinates are compared, calculate and be worth most, confirm the coordinate at several angles of rectangular circuit domain；Confirm point coordinates in rectangles according to these four coordinates, and more midpoint by circuit layout subregion.
6. the method that a kind of Def storehouse according to claim 4 is changed with 3D integrated circuit bookshelf storehouse, it is characterized in that: the algorithm that described gauze flattens is, port by the standard block connected on every gauze, module, (input, output, inout) all extracts and marks in direction, then module name is erased, level gauze is processed as flattening gauze, is conducive to the extraction of gauze.
7. the method that a kind of Def storehouse according to claim 4 is changed with 3D integrated circuit bookshelf storehouse, it is characterized in that: in the bookshelf file format of all outputs, .nodes, file adds unit name and institute's connecting line user name after eda instrument example, .nets, file adds gauze example assumed name, and also adds the information of the port of the connected unit of gauze and the module of place circuit.
8. the method that a kind of Def storehouse according to claim 4 is changed with 3D integrated circuit bookshelf storehouse, it is characterized in that: calculate ttsv location variable and need to refer to the coordinate information of three standard blocks near levels, by calculating, and obtaining TSV and be actually inserted into coordinate, inserting thus realizing TSV.
9. the method that a kind of Def storehouse according to claim 4 is changed with 3D integrated circuit bookshelf storehouse, it is characterized in that: need to calculate the information of upper and lower two-layer standard block simultaneously, after finding suitable three coordinate, it is necessary to by after last time coordinate projection, connect a virtual triangle；And the point intersected by the line of three points is as the TSV location point being actually inserted into.
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| CN201610131658.5A CN105718702B (en) | 2016-03-08 | 2016-03-08 | A kind of method in the library Def and the conversion of the library 3D integrated circuit bookshelf |
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| CN201610131658.5A CN105718702B (en) | 2016-03-08 | 2016-03-08 | A kind of method in the library Def and the conversion of the library 3D integrated circuit bookshelf |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106650136A (en) * | 2016-12-29 | 2017-05-10 | 北京华大九天软件有限公司 | Method for detecting functional consistency of standard units of timing library and netlist library |
| CN115392160A (en) * | 2022-06-10 | 2022-11-25 | 无锡芯光互连技术研究院有限公司 | Format conversion method of circuit diagram description file |
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| US20090160058A1 (en) * | 2007-12-21 | 2009-06-25 | Chen-Cheng Kuo | Structure and process for the formation of TSVs |
| CN103548131A (en) * | 2011-05-05 | 2014-01-29 | 国际商业机器公司 | 3-D integration using multi stage vias |
| CN104576637A (en) * | 2013-10-17 | 2015-04-29 | 台湾积体电路制造股份有限公司 | 3D Integrated Circuit and Methods of Forming Same |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090160058A1 (en) * | 2007-12-21 | 2009-06-25 | Chen-Cheng Kuo | Structure and process for the formation of TSVs |
| CN103548131A (en) * | 2011-05-05 | 2014-01-29 | 国际商业机器公司 | 3-D integration using multi stage vias |
| CN104576637A (en) * | 2013-10-17 | 2015-04-29 | 台湾积体电路制造股份有限公司 | 3D Integrated Circuit and Methods of Forming Same |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106650136A (en) * | 2016-12-29 | 2017-05-10 | 北京华大九天软件有限公司 | Method for detecting functional consistency of standard units of timing library and netlist library |
| CN106650136B (en) * | 2016-12-29 | 2020-06-02 | 北京华大九天软件有限公司 | Method for checking standard unit function consistency of time sequence library and netlist library |
| CN115392160A (en) * | 2022-06-10 | 2022-11-25 | 无锡芯光互连技术研究院有限公司 | Format conversion method of circuit diagram description file |
| CN115392160B (en) * | 2022-06-10 | 2024-04-09 | 无锡芯光互连技术研究院有限公司 | Format conversion method for circuit diagram description file |
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