CN117113923B - Method, device and storage medium for optimizing generation of bonding pad coordinate file - Google Patents
Method, device and storage medium for optimizing generation of bonding pad coordinate file Download PDFInfo
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- CN117113923B CN117113923B CN202311391427.4A CN202311391427A CN117113923B CN 117113923 B CN117113923 B CN 117113923B CN 202311391427 A CN202311391427 A CN 202311391427A CN 117113923 B CN117113923 B CN 117113923B
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- 238000000034 method Methods 0.000 title claims abstract description 31
- 238000003860 storage Methods 0.000 title claims abstract description 18
- 238000004806 packaging method and process Methods 0.000 claims abstract description 42
- 238000013439 planning Methods 0.000 claims abstract description 17
- 238000013507 mapping Methods 0.000 claims abstract description 7
- 238000012854 evaluation process Methods 0.000 claims abstract description 6
- 238000006243 chemical reaction Methods 0.000 claims abstract description 5
- 230000004927 fusion Effects 0.000 claims abstract description 5
- 238000005457 optimization Methods 0.000 claims description 15
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- 230000006870 function Effects 0.000 claims description 4
- 230000002068 genetic effect Effects 0.000 claims description 3
- 238000012545 processing Methods 0.000 claims description 3
- 238000002922 simulated annealing Methods 0.000 claims description 3
- 239000002245 particle Substances 0.000 claims description 2
- 238000012986 modification Methods 0.000 abstract description 4
- 230000004048 modification Effects 0.000 abstract description 4
- 239000005022 packaging material Substances 0.000 abstract description 2
- 238000013461 design Methods 0.000 description 14
- 238000005516 engineering process Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
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- 230000003993 interaction Effects 0.000 description 2
- 238000003672 processing method Methods 0.000 description 2
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- 238000004364 calculation method Methods 0.000 description 1
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- 238000011156 evaluation Methods 0.000 description 1
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- 239000000203 mixture Substances 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
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- 239000011295 pitch Substances 0.000 description 1
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- 238000004088 simulation Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
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- 230000007723 transport mechanism Effects 0.000 description 1
- 238000012384 transportation and delivery Methods 0.000 description 1
- 238000011179 visual inspection Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
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- G06N3/004—Artificial life, i.e. computing arrangements simulating life
- G06N3/006—Artificial life, i.e. computing arrangements simulating life based on simulated virtual individual or collective life forms, e.g. social simulations or particle swarm optimisation [PSO]
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- G06N3/00—Computing arrangements based on biological models
- G06N3/12—Computing arrangements based on biological models using genetic models
- G06N3/126—Evolutionary algorithms, e.g. genetic algorithms or genetic programming
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/30—Computing systems specially adapted for manufacturing
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Abstract
The invention provides a method, a device and a storage medium for generating an optimized pad coordinate file, wherein the method for generating the optimized pad coordinate file comprises the following steps: layout planning, packaging pin planning, packaging coordinate conversion, preset bonding pad fusion, coordinate mapping and rotation, and coordinate file generation; the preset bonding pads are integrated into the packaging evaluation process, so that a packaging factory can evaluate the packaging mode in advance, determine the packaging mode, reduce the modification period of the rear end for packaging, accelerate the market time of chips, determine the packaging in advance, introduce packaging materials in advance, and reduce the packaging time.
Description
Technical Field
The present invention relates to the field of chip design technologies, and in particular, to a method, an apparatus, and a storage medium for optimizing generation of a pad coordinate file.
Background
The PR stage and the packaging stage of the chip are indispensable and are also closely related, wherein PR design can perform tight data interaction with a packaging factory, and according to the existing interaction form of PR and a packaging file, the coordinate extraction of packaging is performed on gds by an EDA tool before the final stage of chip design is performed, so that the coordinate extraction is delivered to the packaging factory.
The packaging coordinate file provided at the stage has the problems of mismatching packaging, signal interference, insufficient thermal management and the like because the packaging feasibility evaluation is not carried out at the earlier stage, but the project is difficult to finish modification, and the progress of the project is seriously influenced.
Therefore, there is a need to devise a method of optimizing pad coordinate file generation to solve the above-described problems.
Disclosure of Invention
The invention provides a method, a device and a storage medium for optimizing generation of a bonding pad coordinate file, which are used for solving the technical problems in the background technology.
In order to solve the problems, the invention provides the following technical scheme:
in one aspect, an embodiment of the present invention includes a method for optimizing generation of a pad coordinate file, including the steps of:
s1, layout planning: performing layout planning according to the functions and requirements of the chip, and determining the position relation, layout, pin positions and the like of each module in the chip;
s2, packaging pin planning: planning the pin layout of the package according to the layout plan, and determining the positions, sequences and distribution of pins in the package;
s3, packaging coordinate conversion: converting the chip module and pin positions designed in the layout planning into a packaging coordinate system, wherein the conversion comprises converting the relative positions and pin layout information into specific coordinates, and using a reference point or an origin as a reference;
s4, fusion of preset bonding pads: the method comprises the steps of integrating a mode of presetting a bonding pad into a packaging evaluation process;
s5, coordinate mapping and rotation: according to the layout requirement of the package and the coordinate system setting, coordinate mapping and rotation are carried out to ensure that the package coordinates are consistent with the position and direction of the actual package;
s6, generating a coordinate file: and generating a bonding pad coordinate file according to the converted packaging coordinate information, wherein the bonding pad coordinate file comprises specific position and layout information of each bonding pad.
Further, the method further comprises the step of optimizing the generated coordinate file of the bonding pad after the coordinate file is generated so as to improve the density of the bonding pad layout, reduce the line length or minimize the layout conflict.
Further, the optimization processing method comprises any one or more of simulated annealing, genetic algorithm, ant colony algorithm, particle swarm optimization or combined optimization method.
Further, the optimization processing method further comprises the step of carrying out layout adjustment and optimization on the generated pad coordinate file for a plurality of times in an iterative optimization mode until the required optimal layout is achieved.
Furthermore, the preset bonding pad fusion refers to that the preset bonding pad is introduced as an auxiliary tool in the packaging evaluation process to help to optimize the packaging layout, the pin layout is optimized through the position and the connection mode of the preset bonding pad, the packaging performance and reliability are improved, and the preset bonding pad is used for calibration and verification.
Further, the calibrating and verifying steps include:
d1, calibrating the positions and the layout of the bonding pads;
d2, verifying the connectivity and the connection quality of the bonding pads;
d3, checking the package size and shape;
and D4, performing physical verification, such as measuring the positions of the bonding pads and visually checking.
In another aspect, an embodiment of the present invention includes an apparatus for optimizing generation of a pad coordinate file, including:
at least one processor;
at least one memory for storing at least one program;
the at least one program, when executed by the at least one processor, causes the at least one processor to implement a method of optimizing pad coordinate file generation.
In another aspect, embodiments of the present invention include a computer-readable storage medium having stored thereon a processor-executable program that, when executed by a processor, is configured to implement a method of optimizing pad coordinate file generation.
Compared with the prior art, the invention has at least the following beneficial effects:
the method for generating the optimized bonding pad coordinate file of the invention blends the preset bonding pad into the packaging evaluation process, so that a packaging factory evaluates the packaging mode in advance, determines the packaging mode, reduces the modification period of the rear end for packaging, quickens the time of putting the chip into the market, determines the packaging in advance, and can introduce packaging materials in advance, thereby reducing the packaging time.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of steps of a method of optimizing pad coordinate file generation in accordance with an embodiment of the present invention;
FIG. 2 is a flowchart of the steps of calibration and verification of an embodiment of the present invention;
fig. 3 is a schematic structural diagram of an apparatus for optimizing generation of a pad coordinate file according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention. It is to be understood that the drawings are designed solely for the purposes of illustration and not as a definition of the limits of the invention.
Referring to figure 1 of the drawings in which,
s1, in a layout planning stage, determining the position relation, layout and pin positions of all modules in the chip according to the functions and requirements of the chip. Specialized Electronic Design Automation (EDA) tools may be used to assist in layout planning.
S2, planning the pin layout of the package according to the layout plan. The location, order, and distribution of pins in the package are determined in consideration of the number, type, and function of the pins. EDA tools may be used to facilitate pin layout planning.
S3, converting the chip module and pin positions designed in the layout planning into a packaging coordinate system. The relative position and pin layout information are converted to specific coordinates using a reference point or origin as a fiducial. This step may be implemented using a coordinate transformation algorithm.
S4, introducing a preset bonding pad as an auxiliary tool to optimize the package layout. The preset bonding pad is an auxiliary bonding pad which is placed in advance, and the pin layout is optimized through the position and the connection mode, so that the performance and the reliability of the package are improved. The preset pads may be introduced at appropriate locations according to the requirements of the pin layout and optimization goals.
In this embodiment, the introduction manner of the preset pad is: creating a component library or a component library of preset bonding pads in a design tool, wherein the component library or the component library comprises options of different sizes, shapes and connection modes of the preset bonding pads; defining rules and constraints of the preset pads in the design tool to ensure their correct use and consistency of layout; the design specifications and requirements of the preset pads are obtained in cooperation with the manufacturer for a particular package type or manufacturing process.
Specifically, in the layout stage, the pre-pad auxiliary layout pins are used. According to the position and the connection mode of the preset bonding pads, the distribution of pins is optimized, so that signal integrity is improved, noise interference is reduced, and the like.
In the wiring stage, wiring guidance is performed using the preset pad as a reference point. And guiding the paths of the signal wires according to the positions and the connection modes of the preset pads so as to ensure the accuracy and the reliability of wiring.
In the calibration and verification stage, D1, calibration of pad positions and layout is performed using preset pads. And checking whether the position of the bonding pad in the design is accurate or not through comparison with the preset bonding pad, and timely adjusting and correcting.
And S5, performing coordinate mapping and rotation according to the layout requirements of the package and the coordinate system setting. Ensuring that the package coordinates are consistent with the location and orientation of the actual package. The coordinate mapping and rotation may be implemented using linear algebra and geometric calculation methods, as desired.
And S6, generating a bonding pad coordinate file according to the converted packaging coordinate information. The file includes specific location and layout information for each pad. The coordinate information may be exported to a standard file format, such as a CSV or TXT (text) file.
Further comprises: and carrying out optimization processing on the generated bonding pad coordinate file. In this embodiment, a genetic algorithm, simulated annealing algorithm, or other optimization algorithm is employed for layout optimization. And adjusting and optimizing the generated pad coordinate file for a plurality of times in an iterative optimization mode until the optimal layout is achieved.
As shown in fig. 2, in the calibration and verification step, further includes:
d2, verifying pad connectivity and connection quality: using a design tool or a circuit simulation tool to verify the connectivity and connection quality of the bonding pads; ensure that the pads are properly connected to the corresponding pins or signal lines and that the connection has good electrical characteristics.
D3, checking the package size and the appearance, and checking whether the package size and the appearance in the design are consistent with the actual requirements; the outline of the package is inspected for suitability for PCB layout and assembly processes, avoiding interference with other components or mechanical structures.
D4, performing physical verification: measuring whether the positions, the pitches and the sizes of the bonding pads are consistent with the design by using precision measurement equipment; visual inspection ensures that the location, layout and connectivity of the pads are as expected.
And carrying out necessary adjustment and correction on the layout according to the calibration and verification results. The pad coordinate file may be regenerated and optimized as needed to further improve layout quality.
And finally generating an optimized pad coordinate file for pad layout in the electronic chip packaging process.
The specific steps described above may be adapted and extended according to actual design requirements and manufacturing environment requirements. Close collaboration with manufacturers, manufacturing engineers, and related design teams is important during the calibration and verification stages to ensure design accuracy and manufacturability.
As shown in fig. 3, an embodiment of the present invention further provides an apparatus 100 for optimizing generation of a pad coordinate file, which specifically includes:
at least one processor 110;
at least one memory 120 for storing at least one program;
the at least one program, when executed by the at least one processor 110, causes the at least one processor to implement the method as described in fig. 1.
The memory 120, as a non-transitory computer readable storage medium, may be used to store non-transitory software programs and non-transitory computer executable programs. Memory 120 may include high-speed random access memory and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid state storage device. In some implementations, memory 120 may optionally include remote memory located remotely from processor 110, which may be connected to processor 110 via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
It will be appreciated that the device structure shown in fig. 3 is not limiting of the device 100 and may include more or fewer components than shown, or may be combined with certain components, or a different arrangement of components.
The embodiment of the present invention also provides a computer-readable storage medium storing a processor-executable program for implementing the method shown in fig. 1 when executed by a processor.
It is to be understood that all or some of the steps, systems, and methods disclosed above may be implemented in software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as known to those skilled in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Furthermore, as is well known to those of ordinary skill in the art, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media.
The foregoing description of the preferred embodiment of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.
Claims (7)
1. A method of optimizing generation of a bond pad coordinate file, comprising the steps of:
s1, layout planning: performing layout planning according to the functions and requirements of the chip, and determining the position relation, layout and pin positions of each module in the chip;
s2, packaging pin planning: planning the pin layout of the package according to the layout plan, and determining the positions, sequences and distribution of pins in the package;
s3, packaging coordinate conversion: converting the chip module and pin positions designed in the layout planning into a packaging coordinate system, wherein the conversion comprises converting the relative positions and pin layout information into specific coordinates, and using a reference point or an origin as a reference;
s4, fusion of preset bonding pads: the method comprises the steps of integrating a preset bonding pad mode into a packaging evaluation process;
s5, coordinate mapping and rotation: according to the layout requirement of the package and the coordinate system setting, coordinate mapping and rotation are carried out to ensure that the package coordinates are consistent with the position and direction of the actual package;
s6, generating a coordinate file: generating a bonding pad coordinate file according to the converted packaging coordinate information, wherein the bonding pad coordinate file comprises specific position and layout information of each bonding pad;
the preset bonding pad fusion is to introduce a preset bonding pad as an auxiliary tool in the packaging evaluation process to help to optimize the packaging layout, optimize the pin layout through the position and the connection mode of the preset bonding pad, and improve the packaging performance and reliability, and comprises the steps of using the preset bonding pad to assist, guide and correct in the layout stage, the wiring stage and the calibration and verification stage.
2. The method of optimizing pad coordinate file generation according to claim 1, further comprising optimizing the generated pad coordinate file after the coordinate file generation to increase a density of the pad layout, reduce a line length, or minimize a layout conflict.
3. The method of optimizing pad coordinate file generation according to claim 2, wherein the method of optimizing processing includes any one or more of a simulated annealing, a genetic algorithm, an ant colony algorithm, a particle swarm optimization, or a combination optimization method.
4. A method of optimizing pad coordinate file generation according to claim 3, wherein the method of optimizing further comprises performing layout adjustment and optimization on the generated pad coordinate file a plurality of times by means of iterative optimization until a desired optimal layout is reached.
5. The method of optimizing pad coordinate file generation of claim 1, wherein the calibrating and verifying step comprises:
d1, calibrating the positions and the layout of the bonding pads;
d2, verifying the connectivity and the connection quality of the bonding pads;
d3, checking the package size and shape;
and D4, performing physical verification, such as measuring the positions of the bonding pads and visually checking.
6. An apparatus for optimizing generation of a pad coordinate file, comprising:
at least one processor;
at least one memory for storing at least one program;
the at least one program, when executed by the at least one processor, causes the at least one processor to implement the method of any of claims 1-5.
7. Computer readable storage medium, characterized in that it has stored thereon a processor executable program for implementing the method according to any of claims 1-5 when being executed by a processor.
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| JPH09321081A (en) * | 1996-05-31 | 1997-12-12 | Toshiba Corp | Bonding property verification system |
| JP2000172733A (en) * | 1998-12-03 | 2000-06-23 | Sony Corp | Method for deciding arrangement position of bonding pad |
| US6357036B1 (en) * | 1998-10-02 | 2002-03-12 | Cirrus Logic, Inc. | Computerized method and apparatus for designing wire bond diagrams and locating bond pads for a semiconductor device |
| CN101369294A (en) * | 2008-10-16 | 2009-02-18 | 复旦大学 | Plane layout planning method for SoC layout |
| CN103902779A (en) * | 2014-04-04 | 2014-07-02 | 无锡市同步电子科技有限公司 | Screen printing identifying method for pins of device packaging libraries |
| CN114970441A (en) * | 2022-06-06 | 2022-08-30 | 江苏泰治科技股份有限公司 | Automatic wiring method for IC chip packaging |
| CN116484800A (en) * | 2023-04-23 | 2023-07-25 | 上海弘快科技有限公司 | Chip packaging design method |
-
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- 2023-10-25 CN CN202311391427.4A patent/CN117113923B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09321081A (en) * | 1996-05-31 | 1997-12-12 | Toshiba Corp | Bonding property verification system |
| US6357036B1 (en) * | 1998-10-02 | 2002-03-12 | Cirrus Logic, Inc. | Computerized method and apparatus for designing wire bond diagrams and locating bond pads for a semiconductor device |
| JP2000172733A (en) * | 1998-12-03 | 2000-06-23 | Sony Corp | Method for deciding arrangement position of bonding pad |
| CN101369294A (en) * | 2008-10-16 | 2009-02-18 | 复旦大学 | Plane layout planning method for SoC layout |
| CN103902779A (en) * | 2014-04-04 | 2014-07-02 | 无锡市同步电子科技有限公司 | Screen printing identifying method for pins of device packaging libraries |
| CN114970441A (en) * | 2022-06-06 | 2022-08-30 | 江苏泰治科技股份有限公司 | Automatic wiring method for IC chip packaging |
| CN116484800A (en) * | 2023-04-23 | 2023-07-25 | 上海弘快科技有限公司 | Chip packaging design method |
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