CN113887163A - Method for inserting redundant through hole - Google Patents
Method for inserting redundant through hole Download PDFInfo
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- CN113887163A CN113887163A CN202111127466.4A CN202111127466A CN113887163A CN 113887163 A CN113887163 A CN 113887163A CN 202111127466 A CN202111127466 A CN 202111127466A CN 113887163 A CN113887163 A CN 113887163A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
Abstract
The application provides a method for inserting a redundant through hole into a chip layout, which comprises the following steps: providing a computer simulation layout of a chip to be processed, wherein the layout is provided with a plurality of through holes; inserting a plurality of redundant through holes around the plurality of through holes in the layout; checking the layout after the plurality of redundant through holes are inserted into the layout, and distinguishing qualified redundant through holes and defective redundant through holes; correcting at least a portion of the defective redundant vias; and forming a final simulation layout of the chip based on the corrected layout. According to the method for inserting the redundant through holes into the chip layout, the inserted partial defect redundant through holes are corrected, the number of the inserted redundant through holes can be increased on the chip layout under the condition that related rules and electric connection are not violated, and the influence of through hole failure on the chip yield is further reduced.
Description
Technical Field
The present application relates to the field of semiconductor design and manufacturing, and more particularly, to a method for inserting an integrated circuit into a redundant via.
Background
With the development of semiconductor technology, the feature size of an integrated circuit is smaller and smaller, the number of transistors on a chip is gradually increased, and the interconnection of components on the chip does not exist on a single layer, so that the integrated circuit needs to be designed to realize the interconnection of all the components.
In the design process of the integrated circuit, interconnection lines among all layers are mainly connected through holes and are used for connecting two adjacent metal layers, the interconnection lines are communication media between every two circuit layout layers and play an important role in the design of an integrated circuit chip. Due to the influence of factors such as process defects, electromigration and thermal stress introduced in the manufacturing process, the through holes may completely fail and partially fail, which may affect circuit delay, cause circuit reliability problems, and may also cause complete failure of chip design functions. In order to improve the reliability of the integrated circuit, a main solution is to insert some redundant through holes beside the through holes under the condition of not violating the design rules, and when one of the through holes cannot work normally, the other through hole can play a role so as to ensure the accurate connection between the layout layers. The redundant through holes provide the opportunity for the adjacent metal layers to be connected again, and the influence on the yield of the chip due to the failure of the through holes is reduced. How to insert more through holes in a limited space is a problem to be solved, and the influence of the through hole failure on the chip yield is reduced.
Disclosure of Invention
The present application provides a method of inserting redundant vias in a layout of a chip that at least partially addresses the above-identified problems of the prior art.
According to an aspect of the present application, there is provided a method for inserting a redundant via in a layout of a chip, the method may include: providing a computer simulation layout of a chip to be processed, wherein the layout is provided with a plurality of through holes; inserting a plurality of redundant through holes around the plurality of through holes in the layout; checking the layout after the plurality of redundant through holes are inserted into the layout, and distinguishing qualified redundant through holes and defective redundant through holes; modifying at least a portion of the defective redundant vias; and forming a final simulation layout of the chip based on the corrected layout.
In an embodiment of the present application, forming the final simulated layout of the chip based on the corrected layout may further include: inserting the corrected defect redundant through hole into the layout and checking the layout; and forming a final simulation layout of the chip in response to the layout passing inspection.
In an embodiment of the present application, the step of inserting a plurality of redundant vias around a plurality of vias in the layout may include: and confirming a position capable of being inserted into a redundant through hole around the through hole, and inserting the redundant through hole into the position, wherein the redundant through hole and the through hole are separated by a preset distance.
In one embodiment of the present application, the inserted plurality of redundant vias are checked, and the check may include at least one of a DRC check, a LVS check and an ANT check.
In one embodiment of the present application, after the step of distinguishing between the qualified redundant via and the defective redundant via, the method may further include: defective redundant vias that are not correctable are deleted.
In one embodiment of the present application, the repairing at least a portion of the defective redundant vias may include: and adding metal layers at two ends of the redundant through hole.
Another aspect of the application provides a method of manufacturing a layout, which may include: forming a simulation layout of a chip to be processed by using the method in any one of the methods; and processing the actual physical layout of the chip according to the layout of the simulation layout.
Yet another aspect of the present application provides a simulation system for inserting redundant vias in a layout of a chip, the simulation system may include: the chip processing device comprises a layout providing module, a chip processing module and a chip processing module, wherein the layout providing module is configured to provide a computer simulation layout of a chip to be processed, and the layout is provided with a plurality of through holes; a redundant via insertion module configured to insert a plurality of redundant vias around a plurality of vias in the layout; the detection module is configured to check the layout after the plurality of redundant through holes are inserted into the layout, and the layout is divided into qualified redundant through holes and defective redundant through holes; a repair module configured to repair at least a portion of the defective redundant vias; and the simulation layout generation module is configured to form a final simulation layout of the chip based on the corrected layout.
In an embodiment of the present application, the simulated layout generation module may be further configured to: inserting the corrected defect redundant through hole into the layout and checking the layout; and forming a final simulated layout of the chip by inspection in response to the layout.
In one embodiment of the present application, the redundant via insertion module is further configurable to: and confirming the position capable of being inserted into the redundant through hole around the through hole, inserting the redundant through hole into the position, and keeping a preset distance between the through hole and the redundant through hole.
In one embodiment of the present application, the detection module is further configurable to: checking the inserted plurality of redundant vias, the checking including at least one of a DRC check, a LVS check and an ANT check.
In one embodiment of the present application, the correction module is further configurable to: defective redundant vias that are not correctable are deleted.
A further aspect of the application provides a readable storage medium having stored thereon a computer program for causing the computer to perform the method of any one of the above.
Yet another aspect of the present application provides an electronic device, which may include: a memory for storing computer executable code; and a processor for executing the computer executable code to implement the method of any of the above.
According to the method for inserting the redundant through holes into the layout of the chip, the redundant through holes are inserted into the periphery of the through holes in the layout, when the through holes in the layout fail due to some reasons, the peripheral redundant through holes can replace the through holes to electrically connect the adjacent metal layers, the yield of the chip layout is improved to a certain extent, and the influence on the yield of the chip due to the failure of the through holes is reduced. According to the method and the device, the inserted partial defect redundant through holes are corrected, so that the number of the inserted redundant through holes can be increased on a chip layout under the condition that related rules and electric connection are not violated, and the influence of through hole failure on the chip yield is further reduced.
Drawings
Other features, objects, and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, with reference to the accompanying drawings. Wherein:
FIG. 1 is a flowchart of a method for inserting redundant vias into a layout of a chip according to an embodiment of the present application;
FIG. 2 is a schematic diagram after a redundant via is inserted into a layout of a chip according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a simulation system for inserting redundant vias into a chip layout according to an embodiment of the present application; and
fig. 4 is a schematic block diagram of an electronic device according to an embodiment of the application.
Detailed Description
For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that the detailed description is merely illustrative of exemplary embodiments of the present application and does not limit the scope of the present application in any way. Like reference numerals refer to like elements throughout the specification. The expression "and/or" includes any and all combinations of one or more of the associated listed items.
In the drawings, the size, dimension, and shape of elements have been slightly adjusted for convenience of explanation. The figures are purely diagrammatic and not drawn to scale. As used herein, the terms "approximately", "about" and the like are used as table-approximating terms and not as table-degree terms, and are intended to account for inherent deviations in measured or calculated values that would be recognized by one of ordinary skill in the art. In addition, in the present application, the order in which the processes of the respective steps are described does not necessarily indicate an order in which the processes occur in actual operation, unless explicitly defined otherwise or can be inferred from the context.
It will be further understood that terms such as "comprising," "including," "having," "including," and/or "containing," when used in this specification, are open-ended and not closed-ended, and specify the presence of stated features, elements, and/or components, but do not preclude the presence or addition of one or more other features, elements, components, and/or groups thereof. Furthermore, when a statement such as "at least one of" appears after a list of listed features, it modifies that entire list of features rather than just individual elements in the list. Furthermore, when describing embodiments of the present application, the use of "may" mean "one or more embodiments of the present application. Also, the term "exemplary" is intended to refer to an example or illustration.
Unless otherwise defined, all terms (including engineering and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
In addition, the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
Fig. 1 is a flowchart of a method 1000 for inserting a redundant via in a layout of a chip according to an embodiment of the present application. As shown in fig. 1, the present application provides a method 1000 for inserting redundant vias in a layout of a die, which may include:
step S110: providing a computer simulation layout of a chip to be processed, wherein the layout is provided with a plurality of through holes;
step S120: inserting a plurality of redundant through holes around the plurality of through holes in the layout;
step S130: checking the layout after the plurality of redundant through holes are inserted, and distinguishing qualified redundant through holes and defective redundant through holes;
step S140: correcting at least a portion of the defective redundant vias;
step S150: and forming a final simulation layout of the chip based on the corrected layout.
In the embodiment of the application, the defect type of the defect redundant through hole which does not meet the inspection rule is judged, and a part of correctable defect redundant through holes are corrected, so that the number of redundant through holes inserted into a chip layout can be increased to a certain extent, and the yield of chips is improved.
In step S110, a computer simulation layout of the chip to be processed is provided by the computer simulation system. With the increasing number of transistors on a chip, the chip may be distributed on each layer, and the layers may be electrically connected by vias, so that the design layout of the chip needs to include a plurality of vias.
However, the integrated circuit manufacturing process is complex, which easily causes the failure of the through hole and further causes the circuit failure. Via failures can mainly include three types: defect failure, electromigration failure, and thermal stress failure. The defect failure is mainly caused by that dust particles in the processing process or dust particles in photoetching cause the circuit of at least one layer in the layout to be missing, so that the open circuit or the short circuit of the layout is caused; the electromigration failure is caused by that under the action of an electric field, the movement of electric ions causes the formation of holes or bulges on the layout, so that a circuit is disconnected, and the disconnection of the layout is caused; the thermal stress failure is mainly caused by the fact that under the action of high-temperature thermal stress, a metal wire in a layout is likely to cause a cavity in a carrier gas, a through hole is used as a connecting part between metal layers, and the physical characteristics and the position of the through hole determine that the through hole is more likely to cause the thermal stress failure.
Next, in step S120, in order to reduce the influence of the via failure on the circuit, a plurality of redundant vias are inserted around the plurality of vias in the layout according to a certain rule, and the circuit connection does not violate the design rule of the layout and does not affect the whole circuit after the plurality of redundant vias are inserted.
Firstly, confirming the position of a through hole in a layout, then confirming the position capable of being inserted into a redundant through hole around the through hole, and inserting the redundant through hole into the position, wherein a preset distance is arranged between the redundant through hole and the through hole.
Step S120 will be further described with reference to fig. 2. Fig. 2 is a schematic diagram after a redundant via is inserted into a layout of a chip according to an embodiment of the present application. As shown in fig. 2, the layers of the chip layout include many vias (via) for electrical connection. For example, the layout of the chip includes a first layout layer 10 and a second layout layer 20, the first layout layer 10 includes a first metal layer 11, the second layout layer 20 includes a second metal layer 21, the first metal layer 11 and the second metal layer 21 are located at two ends of a through hole 121 and can cover two ends of the through hole, the first layout layer 10 and the second layout layer 20 are connected by the through hole 121, wherein the first metal layer 11 and the second metal layer 21 can be used for horizontal wiring, such as a power line and a ground line, and can also be used for vertical wiring, such as an I/O port of a signal source.
A position where a redundant through hole can be inserted is confirmed around the through hole 121, and the redundant through hole is inserted with a predetermined distance from the through hole 121. Such as redundant vias 122 and 123 in fig. 3. The positions of the redundant via 122 and the redundant via 123 are determined to be positions where the redundant via can be inserted, by satisfying a predetermined distance from the via 121. The redundant via 122 is located between the first metal layer 11 and the second metal layer 21, and connects the first metal layer 11 and the second metal layer 21. One end of the redundant via 123 is connected to the first metal layer 11 and the other end has no connectable metal layer.
However, as will be appreciated by those skilled in the art, the number of layout layers included in a chip, the number of metal layers included in each layer of the layout, vias between layers of the layout, and the number of insertable redundant vias are exemplary illustrations and the application is not limited thereto.
In the embodiment of the present application, due to the interaction between the via 121 of the layout and the redundant via 122 around the via, the electrical connection between the first layout layer 10 and the second layout layer 20 is ensured, and the reliability of the whole layout is further ensured.
In step S130, the layout into which the plurality of redundant vias are inserted is checked to distinguish between a qualified redundant via and a defective redundant via. The inspection of the layout after the insertion of the plurality of redundant vias may include Design Rule Check (DRC), layout versus layout schema (LVS), and ANT (antenna effect). Generally speaking, it is necessary to perform DRC check on the layout to which the redundant through holes are added, that is, to perform geometric space check on the layout to which the redundant through holes are added, and to confirm that the layout to which the redundant through holes are added meets the design rule, so as to ensure that the circuit can be implemented by a specific processing technology. After the layout after the redundant through holes are added passes through DRC check, errors may exist. These errors are not due to violating design rules, and may be caused by inconsistency with an actual circuit diagram, so that the layout after the redundant through holes are added needs to be subjected to LVS inspection, and the layout after the redundant through holes are added is compared with a schematic diagram of a circuit to inspect whether the connection of the circuit is matched with a MOS transistor, and the like. And finally, ANT inspection is required to be carried out on the layout after the redundant through holes are added. Because the layout comprises a plurality of metal layers, the exposed metal layers can collect dissociative charges to cause potential rise, the voltage between the layers is larger, and the chip can be damaged, so that whether the metal area (comprising the metal layers and the through holes) of each layer connected with the grid region meets the standard or not needs to be detected.
Then, in step S140, the inserted redundant via is divided into a qualified redundant via, i.e., a redundant via that passes the layout inspection, and a defective redundant via, i.e., a redundant via that does not pass the layout inspection, and the reason for the defective redundant via is further determined, so that the defective redundant via is divided into a correctable redundant via and a non-correctable redundant via. The uncorrectable redundant via can be directly deleted, and the correctable redundant via can be corrected by a technician, for example, the redundant via 123 shown in fig. 3, where the position of the redundant via 123 corresponds to the position of the inserted redundant via, but only one end or both ends of the redundant via 123 contain a metal layer, and at this time, the error can be corrected by adding metal layers to both ends of such correctable redundant via. And inserting the corrected defective redundant through hole into the layout, and checking at least one of DRC, LVS and ANT on the layout. If the corrected defect redundant via can pass the layout inspection, the qualified redundant via and the corrected defect redundant via are inserted into the chip layout, and the final simulation layout is output (step S150).
However, as will be understood by those skilled in the art, the inspection of the layout after the redundant via is added is an exemplary illustration, and may further include layout parasitic parameter extraction (LPE), Parasitic Resistance Extraction (PRE), electrical rule inspection (ERC), and the like, and the application is not limited thereto.
According to the method for inserting the redundant through holes into the chip layout, the qualified redundant through holes and the corrected defect redundant through holes are inserted into the periphery of the through holes in the chip layout, so that the number of the inserted redundant through holes can be increased on the chip layout under the condition that related rules and electric connection are not violated, and the influence of the failure of the through holes on the chip yield is further reduced.
The method for manufacturing the layout is characterized in that a simulation layout of a chip to be processed is formed according to a method for inserting any chip redundant through hole, and an actual physical layout of the chip is processed according to the layout of the simulation layout.
Yet another aspect of the present application further provides a simulation system 300 for inserting redundant vias in a layout of a chip. Fig. 3 is a schematic diagram of a simulation system for inserting redundant vias into a layout of a chip according to an embodiment of the present disclosure, and as shown in fig. 3, the simulation system 300 may include:
a layout providing module 310 configured to provide a computer-simulated layout of a chip to be processed, the layout having a plurality of through holes; a redundant via insertion module 320 configured to insert a plurality of redundant vias around a plurality of vias in the layout; the detection module 330 is configured to check the layout into which the plurality of redundant through holes are inserted, and distinguish the layout into qualified redundant through holes and defective redundant through holes; a repair module 340 configured to repair at least a portion of the defective redundant vias; a simulated layout generation module 350 configured to form a final simulated layout of the chip based on the corrected layout.
In an embodiment of the present application, the simulated layout generation module 350 may be further configured to: inserting the corrected defect redundant through hole into the layout and checking the layout; and forming a final simulated layout of the chip by inspection in response to the layout.
In one embodiment of the present application, the redundant via insertion module 320 may be further configured to: and confirming the position capable of being inserted into the redundant through hole around the through hole, and inserting the redundant through hole at the position, wherein the through hole and the redundant through hole are separated by a preset distance.
In an embodiment of the present application, the detection module 330 may be further configured to: checking the inserted plurality of redundant vias, the checking including at least one of a DRC check, a LVS check and an ANT check.
In an embodiment of the present application, the modification module 340 may be further configured to: defective redundant vias that are not correctable are deleted.
In another aspect of the present application, an electronic device is also provided. Fig. 4 is a schematic block diagram of an electronic device according to an embodiment of the application. As shown in fig. 4, the electronic device includes a processor 10 and a memory 20. The memory 20 is used for storing computer executable codes; and a processor 10 for executing the computer executable code to implement any method of inserting redundant vias in a layout of a chip. The memory stores instructions executable by the at least one processor to cause the at least one processor to perform a method for inserting redundant vias in a layout of a chip as provided herein. The memory 20 may be a flash memory device, may be a NAND type flash memory device, and may be a 3D NAND flash memory device. The processor 10 may control operations of the memory 20, such as an insert redundant via operation, a check operation, etc., of the memory 20. Those skilled in the art understand that the control signals shown in fig. 4 represent various necessary signals other than data signals, such as various command signals, enable signals, address signals, etc., for implementing various operations such as an insert redundant via operation, a check operation, etc.
In one embodiment, the electronic device may be or be part of a semiconductor memory device, such as a Solid State Disk (SSD), in which the processor 10 and the memory 20 may be integrated accordingly. In some embodiments, the memory system may be implemented as a storage component in various computing devices, such as computers, communication devices, multimedia devices, gaming devices, and the like.
In yet another embodiment of the present application, a readable storage medium, such as a memory, storing a computer program is also provided. The non-transitory computer readable storage medium of the present application stores computer instructions for causing a computer to perform the method for inserting redundant vias in a layout for a chip provided herein.
The objects, technical solutions and advantageous effects of the present invention are further described in detail with reference to the above-described embodiments. It should be understood that the above description is only a specific embodiment of the present invention, and is not intended to limit the present invention. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.
Claims (14)
1. A method for inserting redundant through holes in a chip layout is characterized by comprising the following steps:
providing a computer simulation layout of a chip to be processed, wherein the layout is provided with a plurality of through holes;
inserting a plurality of redundant through holes around the plurality of through holes in the layout;
checking the layout after the plurality of redundant through holes are inserted into the layout, and distinguishing qualified redundant through holes and defective redundant through holes;
modifying at least a portion of the defective redundant vias; and
and forming a final simulation layout of the chip based on the corrected layout.
2. The method of claim 1, wherein forming the final simulated layout of the chip based on the modified layout further comprises:
inserting the corrected defect redundant through hole into the layout and checking the layout; and
and forming a final simulation layout of the chip in response to the layout passing inspection.
3. The method of claim 1, wherein inserting a plurality of redundant vias around a plurality of vias in the layout comprises:
and confirming a position capable of being inserted into a redundant through hole around the through hole, and inserting the redundant through hole into the position, wherein the redundant through hole and the through hole are separated by a preset distance.
4. The method of claim 1, wherein the inserted plurality of redundant vias are checked, the check comprising at least one of a DRC check, a LVS check, and an ANT check.
5. The method of any of claims 1-4, wherein after the step of distinguishing between a pass-redundant via and a defect-redundant via, the method further comprises: defective redundant vias that are not correctable are deleted.
6. The method of claim 1, wherein modifying at least a portion of the defective redundant vias comprises: and adding metal layers at two ends of the redundant through hole.
7. A method of manufacturing a layout, the method comprising:
forming a simulation layout of a chip to be processed by using the method according to any one of claims 1 to 6; and
and processing the actual physical layout of the chip according to the layout of the simulation layout.
8. A simulation system for inserting redundant vias in a layout of a chip, the simulation system comprising:
the chip processing device comprises a layout providing module, a chip processing module and a chip processing module, wherein the layout providing module is configured to provide a computer simulation layout of a chip to be processed, and the layout is provided with a plurality of through holes;
a redundant via insertion module configured to insert a plurality of redundant vias around a plurality of vias in the layout;
the detection module is configured to check the layout after the plurality of redundant through holes are inserted into the layout, and the layout is divided into qualified redundant through holes and defective redundant through holes;
a repair module configured to repair at least a portion of the defective redundant vias; and
and the simulation layout generation module is configured to form a final simulation layout of the chip based on the corrected layout.
9. The simulation system of claim 8, wherein the simulated layout generation module is further configured to:
inserting the corrected defect redundant through hole into the layout and checking the layout; and
and forming a final simulation layout of the chip by checking in response to the layout.
10. The simulation system of claim 8, wherein the redundant via insertion module is further configured to:
and confirming the position capable of being inserted into the redundant through hole around the through hole, inserting the redundant through hole into the position, and keeping a preset distance between the through hole and the redundant through hole.
11. The simulation system of claim 8, wherein the detection module is further configured to: checking the inserted plurality of redundant vias, the checking including at least one of a DRC check, a LVS check and an ANT check.
12. The simulation system of claim 8, wherein the correction module is further configured to: defective redundant vias that are not correctable are deleted.
13. A readable storage medium storing a computer program, wherein the computer instructions are for causing the computer to perform the method of any one of claims 1-6.
14. An electronic device, comprising:
a memory for storing computer executable code; and
a processor for executing the computer executable code to implement the method of any one of claims 1-6.
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| CN202111127466.4A CN113887163A (en) | 2021-09-26 | 2021-09-26 | Method for inserting redundant through hole |
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| CN202111127466.4A CN113887163A (en) | 2021-09-26 | 2021-09-26 | Method for inserting redundant through hole |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114117995A (en) * | 2022-01-24 | 2022-03-01 | 成都明夷电子科技有限公司 | Artificial intelligence algorithm-based packaged chip processing method |
| CN114818604A (en) * | 2022-06-29 | 2022-07-29 | 飞腾信息技术有限公司 | Method and device for correcting short-circuit defect on digital layout |
-
2021
- 2021-09-26 CN CN202111127466.4A patent/CN113887163A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114117995A (en) * | 2022-01-24 | 2022-03-01 | 成都明夷电子科技有限公司 | Artificial intelligence algorithm-based packaged chip processing method |
| CN114818604A (en) * | 2022-06-29 | 2022-07-29 | 飞腾信息技术有限公司 | Method and device for correcting short-circuit defect on digital layout |
| CN114818604B (en) * | 2022-06-29 | 2022-10-11 | 飞腾信息技术有限公司 | Method and device for correcting short-circuit defects on digital layout |
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