JP2011060117A - Support device for semiconductor integrated circuit design and design method of semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique of reducing cost and time for manufacturing for defect reduction. <P>SOLUTION: A group cell generating section reads a net list (D1) and an undetected node list (L2), specifies logic cells (C3 to C6) connected to an undetected node shown in the undetected node list as preferentially arranged logic cells (C3 to C6), and generates a group cell (GC1) which is an aggregate of the preferentially arranged logic cells (C3 to C6) with reference to a logic cell library for arrangement (L3). Then, a wiring processing section preferentially determines wiring of the preferentially arranged logic cells (C3 to C6) included in the group cell (GC1). <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit design support apparatus and a semiconductor integrated circuit design method, and more particularly to a layout technique in designing a semiconductor integrated circuit.

  When developing a semiconductor integrated circuit, a test process for testing whether or not the semiconductor integrated circuit operates properly is essential. In the test process, it is verified whether the development target semiconductor integrated circuit satisfies the specifications.

  In the development of a semiconductor integrated circuit, a mask pattern (layout pattern) is determined in a layout process after the logic design is completed. Thereafter, a chip is actually manufactured according to the mask pattern, and the chip is tested with an LSI tester.

  In the layout process, layout processing is executed based on circuit information on which a test (hereinafter referred to as logic verification) for a semiconductor integrated circuit for which logic design has been completed is completed. By the layout process, physical information is created as a mask pattern of the semiconductor integrated circuit.

  At the stage where the logic design is completed, there is no physical information in the circuit information. In subsequent layout processing, physical information such as the positional relationship of logic cells is given as a mask pattern for the first time. Further, the physical positional relationship such as the logic cells included in the mask pattern is determined based on the timing information of the logic operation of the integrated circuit.

  In the subsequent diffusion process, a transistor is formed on the semiconductor substrate by the mask pattern. In the layout process, the mask pattern is determined in consideration of the signal propagation delay characteristic of the transistor having a desired value in advance.

  Thus, in normal layout design, defects due to LSI characteristic timing are taken into account when designing a mask pattern. However, defects that are created in the manufacturing process, such as those caused by the attachment of fine foreign matter to the mask, are not taken into account when designing the mask pattern.

  A technique is known in which a layout of a designed mask pattern where a failure is likely to occur is detected to change the layout (see, for example, Patent Document 1). FIG. 1 is a flowchart showing the layout method described in Patent Document 1. In the flowchart of FIG. 1, the layout unit 1401 supplies the mask information 1402 to the failure list ordering unit 1403. The failure list ordering unit 1403 generates an ordered failure list 1405 by ordering the failure list 1404 based on the mask information 1402. In addition, the layout unit 1406 takes measures against locations where mask failures and actual faults of wiring are likely to occur based on the information in the ordered failure list 1405. Then, a final mask layout diagram 1407 is generated.

FIG. 2 is a circuit diagram showing a specific failure list ordering method in the conventional layout method. FIG. 3 is a mask layout diagram showing a specific failure list ordering method in the conventional layout method. If the wiring is close on the mask, a failure due to a short circuit or crosstalk is likely to occur. Therefore, as shown in FIG. 3, the wiring distance Y is calculated from the information of the arrangement coordinates of the mask layout, and the ordering is performed such that the closer the wiring is, the easier the failure occurs. For example, when viewed at five locations (first node 101 to fifth node 105) in FIG.
104 <102 <105 <101 <103
If so, it is determined that failures are likely to occur in this order.

When the mask for power supply is near the normal signal line on the mask, the signal line may be affected by the power supply to generate noise and become defective. In FIG. 3, hatched lines are power supply lines. As shown in FIG. 3, first, the power supply line is specified from the information on the arrangement coordinates of the mask layout, and the distance X between the power supply line and the signal wiring is calculated from the information on the arrangement coordinates. The ordering is performed. For example, when viewed at five locations in FIG. 2, the distance between the power supply line (diagonal line) and the signal wiring is
104 <105 <102 <101 <103
If so, it is determined that failures are likely to occur in this order.

When a signal line for supplying a clock is close to a normal signal line, the signal line is similarly affected by the power supply and may generate noise and become defective. In this case, ordering is performed in the same flow by providing the layout apparatus with information on signal lines for supplying clocks. If the signal lines using contacts on the mask are frequently changed, signal disconnection due to contact failure is likely to occur. Therefore, as shown in FIG. 3, the same wiring is searched from the information of the signal lines of the mask layout, the number of contacts is counted, and the order is set such that the failure is likely to occur as the number of contacts increases. In FIG. 3, the contacts of the wiring C are O, P, Q, and R, and the number of contacts is four. For example, when viewed at five locations in FIG.
104>101>103>102> 105
In this order, it is determined that the failure is likely to occur in this order.

If signal lines cross on the mask, wiring shorts may occur between them. In FIG. 3, the wiring A and the wiring C cross at S. Further, the wiring B and the wiring C cross at T. Therefore, in FIG. 3, the signal line cross states (upper and lower adjacent layers) and the number of crosses of the mask layout are counted, and the order is set such that the more the number of signal line crosses in the upper and lower adjacent layers is, the more likely the failure occurs. For example, when viewed at five locations in FIG.
104>101>105>102> 103
In this order, it is determined that the failure is likely to occur in this order. In the technique described in Patent Document 1 (Japanese Patent Laid-Open No. 2005-332389), a failure list is created and reflected in the layout to reduce the possibility of failure.

JP 2005-332389 A

  The technology described in Patent Document 1 is based on a mask pattern physical information in a chip of a semiconductor integrated circuit, and the results of cells and functional blocks are taken into account. This enables layout and contributes to the reduction of failures such as initial failures. As described above, in the technique described in Patent Document 1, layout processing is performed first, and a location where a failure is likely to occur is found from the physical positional relationship of the mask pattern at that time. These locations are created as a failure list, and countermeasures are again taken for the mask pattern on the layout from the failure list.

  For this reason, there is a problem that the cost of making the correction for reducing the defect becomes enormous. That is, the timing information such as the delay of each element and the setup and hold between the elements considered in the layout process is changed by correcting the mask pattern applied as a countermeasure on the layout. Therefore, it is necessary to perform timing verification again to check whether there is a problem. When a problem occurs in the timing verification, layout correction is necessary again.

  Moreover, with the technique described in Patent Document 1, it is difficult to suppress the outflow of a defective product that is produced by a manufacturing process that is caused by a fine foreign substance adhering to the mask as a defective product. As a technique for preventing such defective products from flowing into the market, a technique using a test pattern by automatic test pattern generation (ATPG) is known. The test by ATPG is executed by a tester. The tester removes defects caused by the manufacturing process by comprehensively testing the circuits in the manufactured LSI. However, as integrated circuits designed with high integration and high density are becoming larger and more complex, it has become difficult to test all circuits.

  For locations that cannot be detected by the ATPG test (hereinafter referred to as undetected locations), it is not possible to determine whether a product is non-defective or defective in the product shipment test. LSIs that do not take into account such defects will flow into the market as defective products.

  In other words, in layout design in recent years when design circuits are becoming larger and more complex, as with defects due to timing, undetected points that cannot be removed by a tester such as ATPG are considered when designing mask patterns. There is a demand for a layout method in which defects caused by the above are not created by layout processing.

  [Means for Solving the Problems] will be described below using the numbers used in [DETAILED DESCRIPTION]. These numbers are added to clarify the correspondence between the description of [Claims] and [Mode for Carrying Out the Invention]. However, these numbers should not be used to interpret the technical scope of the invention described in [Claims].

  In order to solve the above problems, a semiconductor integrated circuit design support apparatus including a storage device (1) and an EDA (electronic design automation) tool (2) is configured. The storage device (1) preferably holds a net list (D1), an undetected node list (L1), and a placement logic cell library (L3). In addition, the EDA tool (2) selects the logic cells (C3 to C6) to be preferentially processed among the plurality of logic cells (C1 to C9) included in the semiconductor integrated circuit shown in the netlist (D1). It is preferable that a group cell generation unit to be identified and a wiring processing unit for determining a wiring of the semiconductor integrated circuit are provided. Here, the group cell generation unit reads the net list (D1) and the undetected node list (L2), and connects the logic cells (C3 to C6) connected to the undetected nodes indicated in the undetected node list. ) As the priority placement logic cells (C3 to C6), and by referring to the placement logic cell library (L3), the group cell (GC1) which is a set of the priority placement logic cells (C3 to C6) is selected. Generate. The wiring processing unit preferentially determines the wiring of the priority placement logic cells (C3 to C6) included in the group cell (GC1).

  If the effect obtained by the representative one of the inventions disclosed in the present application will be briefly described, the cost time for making a defect reduction can be reduced.

FIG. 1 is a flowchart showing the layout method described in Patent Document 1. FIG. 2 is a circuit diagram showing a specific failure list ordering method in the conventional layout method. FIG. 3 is a mask layout diagram showing a specific failure list ordering method in the conventional layout method. FIG. 4 is a block diagram illustrating a hardware configuration that implements the layout tool of the present embodiment. FIG. 5 is a flowchart illustrating the operation of the layout tool of this embodiment. FIG. 6 is a flowchart illustrating in detail the operation of the layout tool of this embodiment. FIG. 7 is a circuit diagram of a logic cell for explaining the operation of this embodiment. FIG. 8 is a circuit diagram of a logic cell connected to an undetected node of this embodiment. FIG. 9 is a block diagram illustrating the configuration of the group cell of this embodiment. FIG. 10 is a circuit diagram illustrating a circuit after placement and routing. FIG. 11 is a flowchart illustrating the operation of the second embodiment. FIG. 12 is a circuit diagram illustrating the configuration of the logic cell circuit according to the second embodiment. FIG. 13 is a block diagram illustrating the configuration of a group cell according to the second embodiment. FIG. 14 is a block diagram illustrating the configuration of a group cell according to the second embodiment. FIG. 15 is a circuit diagram illustrating a circuit after the placement and routing according to the second embodiment.

[First Embodiment]
Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted. FIG. 4 is a block diagram illustrating a hardware configuration that implements the layout tool of the present embodiment. The storage device 1 stores a library creation tool, a layout tool, a library, and data. The computing device 2 reads the library creation tool, layout tool and library, data from the storage device 1 and executes the library creation tool and layout tool, and writes the library creation result and computation result data to the storage device 1. The arithmetic device 2 starts processing and selects data based on information from the input device 4. The display device 3 displays the processing contents and results of the arithmetic device 2.

  The operation of this embodiment will be described below. FIG. 5 is a flowchart illustrating the operation of the layout tool of this embodiment. Note that the layout tool of the present embodiment is preferably provided as a function of the EDA tool. Further, the processing according to the procedure shown in the flowchart is executed on hardware that realizes the layout tool of the present embodiment shown in FIG.

  The entire net list D1 of the entire semiconductor integrated circuit is used as input data, and one undetected node is extracted from the failure undetected node list L1 obtained by DFT design or the like. Then, the logic cell connected to the undetected node is extracted from the entire net list D1, and the extracted logic cell is output to the connected logic cell list L2 (step S1).

  FIG. 7 is a circuit diagram of a logic cell for explaining the operation of this embodiment. The circuit shown in FIG. 7 includes a plurality of logic cells (first logic cell C1 to ninth logic cell C9). The circuit also includes a first undetected node N1. Here, the first undetected node N1 is an undetected node obtained by DFT design or the like.

  FIG. 8 is a circuit diagram of a logic cell connected to an undetected node of this embodiment. A circuit diagram of the logic cell of FIG. 8 is obtained by extracting the logic cell connected to the first undetected node N1 from the circuit diagram of the logic cell of FIG. In step S1, a list of logic cells connected to the first undetected node N1 in FIG. 8 is a connected logic cell list L2.

  Next, a group cell is created with reference to the connected logic cell list L2 and the arrangement logic cell library L3 (step S2). The placement logic cell library L3 indicates a placement library for each logic cell. The arrangement logic cell library L3 is referred to by a layout tool executed on the hardware of FIG.

  FIG. 6 is a flowchart illustrating in detail the creation of the group cell in step S2 of FIG. The detailed operation in step S2 will be described based on the flowchart of FIG. First, referring to the connected logic cell list L2 and the placement logic cell library L3, the logic cells (from the third logic cell C3 to the sixth logic cell) connected to the first undetected node N1 in the connected logic cell list L2 are referred to. The size in which the cell C6) can be arranged is calculated as a group cell arrangement area (step S11).

  Next, with reference to the arrangement logic cell library L3, the third logic cell C3 to the sixth logic cell C6 are arranged in the group cell arrangement area obtained by the calculation. At this time, the third logic cell C3 to the sixth logic cell C6 are arranged so that the wiring length of the first undetected node N1 inside the group cell arrangement region is the shortest (step S12).

FIG. 9 is a block diagram illustrating the configuration of the group cell of this embodiment. FIG. 9 shows the third
The first group cell GC1 in which the logic cells C3 to C6 are arranged is illustrated. Next, the first group cell GC1 in which the third logic cell C3 to the sixth logic cell C6 are arranged can be handled as one logic cell. Then, the library of the first group cell GC1 is created and output as the arrangement group cell library L4 (step S13).

  Returning to FIG. 5, after the process of step S <b> 2 is completed, it is determined whether the processes of step S <b> 1 and step S <b> 2 have been performed for all undetected nodes in the undetected node list L <b> 1. If there is still unprocessed processing, steps S1 to S2 are repeated. When the process of creating a group cell for cells connected to all undetected nodes is completed, the following process is performed (step J1). Thereby, the arrangement group cell library L4 is created for each undetected node in the information of the undetected node list L1.

  Next, referring to the placement logic cell library L3 and the placement group cell library L4, placement processing of logic cells in the entire netlist is performed (step S3). Next, the wiring process corresponding to the wiring in a group cell, ie, the cell connected to each 1st undetected node N1 in each group cell is performed (step S4).

  As described above, the logic cells connected to the undetected nodes are grouped so that the wiring length of the undetected nodes is the shortest distance, and wiring between the logic cells connected to the undetected nodes is performed first. In each group cell, a wiring having the shortest wiring length between cells connected to each undetected node is realized. Next, CTS (clock tree synthesis) processing is performed (step S5). Next, a wiring process other than the wiring of the cell connected to the undetected node is performed (step S6).

  FIG. 10 is a layout diagram illustrating the layout after the placement and routing performed up to the wiring process in step S6. In FIG. 10, the logic cells from the first logic cell C1 to the ninth logic cell C9 in FIG. 10 are arranged and wired in the layout area A1. According to the flowchart of the present embodiment, the third logic cell C3 to the sixth logic cell C6 are connected to the first undetected node N1 and the third logic cell C3 to the sixth logic so that the wiring length between the logic cells connected to the first undetected node N1 is the shortest distance. A group cell in which the logic cells C6 are grouped is created, these logic cells are arranged as the first group cell GC1, and wiring between the logic cells connected to the first undetected node N1 in the first group cell GC1 first As a result, the wiring length between the logic cells connected at the first undetected node N1 is wired with the shortest length.

  As described above, in the semiconductor integrated circuit design support apparatus and the semiconductor integrated circuit design method according to the present embodiment, it is possible to reduce the cost time for making a defect reduction. The reason for this is that pre-layout processing is not required and the layout can be made with timing in a single layout process, so that the cost required for making up can be reduced as compared with the prior art.

  Further, as a second effect, it is possible to reduce the failure of the LSI due to the wiring of the undetected node by minimizing the wiring length of the undetected node. The reason for this is that, due to the long metal wiring in the LSI chip, the failure of the LSI due to the wiring increases due to the influence of electromigration. “Technical Research Report of IEICE. R, Reliability IEICE technical report.Reliability 95 (432) pp, 13-18 19951215 “The Institute of Electronics, Information and Communication Engineers”, because the influence of electromigration can be eliminated by physically shortening the wiring length.

  In addition, as a third effect, it is possible to reduce the possibility of being defective after shipment to the market. The reason is that the undetected node indicates a wiring that is not activated by the test pattern and cannot be tested by the tester. In the present invention, the wiring of the cell connected to the undetected node is minimized from the undetected node list. By reducing the probability of failure by taking measures to reduce the influence of electromigration at the manufacturing stage, the tester test may pass but become defective after market shipment. This is because it can be reduced.

  As a fourth effect, the present invention can be easily handled by the layout method. The reason is that the layout method of the present invention only adds a process for referring to the undetected node list from the DFT and a process for creating a group cell based on the process, and changes the priority of the wiring process. This is because the other processing steps before and after that are not different from the conventional layout process, and can be easily adapted to the conventional layout process.

  Further, as a fifth effect, the present invention does not cause backtracking in the layout process. The reason for this is that the layout method of the present invention only performs the conventional layout process from the process of referring to the undetected node list and the process of creating a group cell based on the list, and in this process, it is a backtracking operation. In contrast, the conventional technology requires modification of the layout and wiring for the layout result, so if it is difficult to correct it, it is necessary to perform a relocation and rewiring process. is there.

[Second Embodiment]
FIG. 11 is a flowchart illustrating the operation of the second exemplary embodiment of the present invention. The operation of the second embodiment is different from the first embodiment in the process of step S2 of the operation of the first embodiment. The overall operation flowchart of the second embodiment is the same as that of the first embodiment. Further, in the flowchart of FIG. 11, the processes with the same step numbers as those in FIG. 6 are performed in the same manner as in the first embodiment.

  FIG. 12 is a circuit diagram illustrating the configuration of the logic cell circuit according to the second embodiment. FIG. 12 illustrates a circuit in which undetected nodes of the first undetected node N1 and the second undetected node N2 exist. In the following description, the operation of the second embodiment will be described based on the circuit diagram of the logic cell of FIG. 12 and corresponding to the flowchart of FIG.

  First, similarly to the first embodiment, the process of step S1 in FIG. 5 is performed. In the operation of the second embodiment, in the first operation, one of the first undetected node N1 and the second undetected node N2 obtained from the undetected node list L1 is specified in step S1. Then, a logic cell connected to the identified undetected node is extracted. In the following description, it is assumed that the first undetected node N1 in FIG. 12 is identified and the connected logical cell list L2 indicating the logical cells connected to the first undetected node N1 is generated in the first operation. .

Next, the process of step S2 of FIG. 5 is performed. In the second embodiment, this process is executed according to the group cell creation flowchart shown in FIG.
First, referring to the connected logical cell list L2, duplication confirmation is performed to determine whether or not the logical cell connected to the first undetected node N1 is included in the placement group cell library L4 (step J2).

  If there is no overlapping of logic cells, the processing from step S11 to step S13 is performed. These processes are the same as step S11, step S12, and step S13 in the flowchart of group cell creation according to the first embodiment.

  Through this step S11, step S12, and step S13, the logic cell C3, the logic cell C5, the logic cell C6, and the logic cell C4 connected to the first undetected node N1 constitute one group cell (first group cell GC1). Created and registered in the arrangement group cell library L4.

  FIG. 13 is a block diagram illustrating the configuration of the group cell (first group cell GC1) when the processing up to step S13 described above is executed in the second embodiment. The first group cell GC1 includes a third logic cell C3, a fourth logic cell C4, a fifth logic cell C5, and a sixth logic cell C6. As shown in FIG. 13, the first group cell GC1 is connected to the second undetected node N2 that has not been processed.

  Here, the processing of the flowchart for creating the group cell in FIG. 11 is finished once, the processing of step S2 in FIG. 5 is exited, and the processing proceeds to the next processing in FIG. It is determined whether there is an undetected node that has not yet been processed. In the second embodiment, since there is a second undetected node N2 that has not yet been processed, the process proceeds to step S1 in the flowchart of FIG. 5 (step J1). With reference to the undetected node list L1, the fifth logic cell C5, the eighth logic cell C8, and the ninth logic cell C9 connected to the second undetected node N2 are extracted (step S1).

  Next, in order to perform the process of step S2 of FIG. 5 again, the process proceeds to the group cell creation flowchart shown in FIG. It is determined whether or not the logic cells extracted in step S1 overlap (step J2). Here, among the logic cells connected to the second undetected node N2, the fifth logic cell C5 is already included in the first group cell GC1 of the placement group cell library L4. Therefore, it is determined that the fifth logic cell C5 overlaps, and the process proceeds to step S21.

  Referring to the connected logic cell list L2, the placement logic cell library L3, and the placement group cell library L4, the group cell placement indicates the size of the group cell and the logic cell connected to the undetected node. The area is calculated (step S21). Here, the first group cell GC1, the eighth logic cell C8, and the ninth logic cell C9 are objects of arrangement area calculation.

  Next, the first group cell GC1, the eighth logic cell C8, and the ninth logic cell C9 are placed in the group cell arrangement area obtained by calculation with reference to the arrangement logic cell library L3 and the arrangement group cell library L4. 2. Arrangement is made so that the wiring length of the undetected node N2 is the shortest (step S22). FIG. 14 is a block diagram illustrating the configuration of a group cell according to the second embodiment. The first group cell GC1, the eighth logic cell C8, and the ninth logic cell C9 are arranged in the group cell arrangement region to constitute the second group cell GC2.

  Next, the second group cell GC2 in which the first group cell GC1, the eighth logic cell C8, and the ninth logic cell C9 are arranged can be handled as one logic cell. Then, a group cell library is created and output as an arrangement group cell library L4 (step S23).

  Here, the process of the flowchart for creating the group cell in FIG. 11 is completed again, the process of step S2 in FIG. 5 is exited, and the process proceeds to the next process in FIG. Next, it is determined whether all undetected nodes have been processed (step J1). By performing the above processing, an arrangement group cell library L4 is created for all undetected nodes in the undetected node list L1.

  When the processing for all the undetected nodes is completed, the placement process of the logic cells in the entire netlist is performed with reference to the placement logic cell library L3 and the placement group cell library L4 (step S3). A wiring process corresponding to the wiring in the group cell, that is, the cell connected to each of the first undetected node N1 and the second undetected node N2 in each group cell is performed (step S4). Next, CTS processing is performed (step S5). Next, wiring processing other than the wiring in the group cell is performed (step S6).

  FIG. 15 is a circuit diagram illustrating a circuit after the placement and routing that has been performed up to the wiring process in step S6. In FIG. 15, the logic cells of the first logic cell C1 to the ninth logic cell C9 of FIG. 12 are arranged and wired in the layout area A2, but connected to the first undetected node N1 according to the flowchart of the present invention. Group cells in which the third logic cell C3 to the sixth logic cell C6 are combined so that the wiring length between the logic cells connected to the first undetected node N1 is the shortest distance is created. The cell is a first group cell GC1.

  In addition, the eighth logic cell C8 to the ninth logic cell C9 are connected to the second undetected node N2 and the wiring length between the logic cells connected to the second undetected node N2 is the shortest distance. By creating grouped group cells, arranging these logic cells as the second group cell GC2, and wiring between the logic cells connected to the first undetected node N1 and the second undetected node N2 first The wiring length between the logic cells connected at the first undetected node N1 and the second undetected node N2 is shortest.

  Even if there are multiple undetected nodes and the circuit is connected to another undetected node via a logic cell to which the undetected node is connected, the group cell should have the shortest wiring of the undetected node. It is possible to perform processing.

  The embodiment of the present invention has been specifically described above. The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention.

DESCRIPTION OF SYMBOLS 1 ... Memory | storage device 2 ... Arithmetic unit 3 ... Display apparatus 4 ... Input device D1 ... Entire net list L1 ... Undetected node list L2 ... Connected logic cell list L3 ... Arrangement logic cell library L4 ... Arrangement group cell library C1 ... 1st logic cell C2 ... 2nd logic cell C3 ... 3rd logic cell C4 ... 4th logic cell C5 ... 5th logic cell C6 ... 6th logic cell C7 ... 7th logic cell C8 ... 8th logic cell C9 ... 1st 9 logic cell N1 ... first undetected node N2 ... second undetected node GC1 ... first group cell GC2 ... second group cell A1 ... layout region A2 ... layout region 101 ... first node 102 ... second node 103 ... first 3 node 104 ... 4th node 105 ... 5th node 1401 ... layout part 1402 ... mask information 1403 ... failure list ordering part 1404 ... failure list 1 05 ... order pickled been fault list 1406 ... layout unit 1407 ... mask layout view A ... wiring B ... wiring C ... wiring O ... contact P ... contact Q ... Contacts R ... Contacts X ... distance Y ... distance

Claims (12)

A storage device;
EDA (electronic design automation) tool,
The storage device
Netlist,
Undetected node list,
Holding the logic cell library for placement,
The EDA tool is
A group cell generation unit for specifying a logic cell to be preferentially processed among a plurality of logic cells included in the semiconductor integrated circuit shown in the net list;
A wiring processing unit for determining wiring of the semiconductor integrated circuit,
The group cell generation unit
Read the netlist and the undetected node list;
A logic cell connected to an undetected node shown in the undetected node list is identified as a priority placed logic cell;
A group cell that is a set of the priority placement logic cells is generated with reference to the placement logic cell library,
The wiring processing unit
A semiconductor integrated circuit design support apparatus that preferentially determines the wiring of the preferentially arranged logic cells included in the group cell. The semiconductor integrated circuit design support apparatus according to claim 1,
The undetected node list is
A semiconductor integrated circuit design support device that includes, as the undetected node, each of a plurality of nodes that are not subjected to a defective portion detection process when a circuit designed based on DFT (Design for Testability) technology is tested. The semiconductor integrated circuit design support apparatus according to claim 1 or 2,
The EDA tool further includes:
Including a cell placement processing unit,
The group cell generation unit
Storing the group cell in the group cell library for arrangement of the storage device;
The cell arrangement processing unit
Using the group cells read from the group cell library for placement as a unit, the placement of the group cells and logic cells is determined based on the netlist,
The wiring processing unit
A semiconductor integrated circuit design support apparatus that determines a wiring between the group cell and the logic cell after preferentially determining a wiring of the priority placement logic cell included in the group cell. The semiconductor integrated circuit design support apparatus according to any one of claims 1 to 3,
The group cell generation unit
Referring to the list of preferentially arranged logic cells and the arrangement logic cell library, the size that the preferentially arranged logic cells can be arranged is calculated as a group cell arrangement area,
A semiconductor integrated circuit design support device that refers to the placement logic cell library and generates the group cell by arranging the priority placement logic cells so that the wiring length inside the group cell placement region is minimized. The semiconductor integrated circuit design support apparatus according to claim 4,
The group cell generation unit
Referring to the list of the preferentially arranged logic cells, a determination is made as to whether or not a logic cell connected to the undetected node is included in the group cell library for placement,
As a result of the determination, when overlapping logic cells are included in the placement group cell library, the priority placement logic cell list, the placement logic cell library, and the placement group cell library are referred to. Then, a semiconductor integrated circuit design support device that calculates a size capable of arranging the group cell and the overlapping logic cell as a new group cell arrangement region. The semiconductor integrated circuit design support device according to claim 5,
The group cell generation unit
A plurality of logic cells including a logic cell having an output terminal connected to a start point of the undetected node and a logic cell having an input terminal connected to an end point of the undetected node are used as the group cell. Circuit design support device. A semiconductor integrated circuit design method executed by a semiconductor integrated circuit design support device including a storage device and an EDA (electronic design automation) tool,
(A) causing the storage device to hold a net list, an undetected node list, and a placement logic cell library in a readable state;
(B) the group cell generation function of the EDA tool specifies a logic cell to be preferentially processed among a plurality of logic cells included in the semiconductor integrated circuit indicated in the netlist;
(C) the wiring processing function of the EDA tool comprises the step of determining the wiring of the semiconductor integrated circuit;
The step (b)
Reading the netlist and the undetected node list;
Identifying a logic cell connected to an undetected node shown in the undetected node list as a preferentially arranged logic cell;
Generating a group cell that is a set of the priority placement logic cells with reference to the placement logic cell library;
The step (c) includes:
A method for designing a semiconductor integrated circuit, comprising: preferentially determining a wiring of the priority placement logic cell included in the group cell. The method for designing a semiconductor integrated circuit according to claim 7,
The undetected node list is
A method for designing a semiconductor integrated circuit, which includes, as the undetected node, each of a plurality of nodes that are not subjected to a defective portion detection process when a circuit designed based on DFT (Design for Testability) technology is tested. The method for designing a semiconductor integrated circuit according to claim 7, further comprising:
(D) the cell placement processing function of the EDA tool comprises the step of determining the placement of the group cells and logic cells not included in the group cells;
The step (b)
Storing the group cell in an arrangement group cell library of the storage device;
The step (d) includes:
Determining the arrangement of the group cells and logic cells not included in the group cells based on the netlist, with the group cells read from the arrangement group cell library as a unit;
The step (c) includes:
A method of designing a semiconductor integrated circuit, comprising: determining a wiring between the group cell and the logic cell after preferentially determining a wiring of the priority placement logic cell included in the group cell. The method for designing a semiconductor integrated circuit according to any one of claims 7 to 9,
The step (b)
Referring to the list of the preferentially arranged logic cells and the logic cell library for arrangement, and calculating a size in which the preferentially arranged logic cells can be arranged as a group cell arrangement region;
A step of generating the group cell by referring to the logic cell library for placement and arranging the priority placement logic cell so that a wiring length inside the group cell placement region is shortest. Design method. The method of designing a semiconductor integrated circuit according to claim 10,
The step (b)
Performing a determination as to whether or not a logic cell connected to the undetected node is included in the group cell library for placement with reference to the list of the priority placement logic cells;
As a result of the determination, when overlapping logic cells are included in the placement group cell library, the priority placement logic cell list, the placement logic cell library, and the placement group cell library are referred to. And calculating a size at which the group cell and the overlapping logic cell can be arranged as a new group cell arrangement region. The method of designing a semiconductor integrated circuit according to claim 11,
The step (b)
A plurality of logic cells including a logic cell having an output terminal connected to a start point of the undetected node and a logic cell having an input terminal connected to an end point of the undetected node as the group cell; A method for designing a semiconductor integrated circuit.

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