JP6051548B2 - Automatic placement and routing apparatus and automatic placement and routing method - Google Patents

Description

  The present invention relates to an automatic placement and routing apparatus and an automatic placement and routing method for arranging and wiring circuit elements in a semiconductor integrated circuit.

  In recent years, semiconductor integrated circuits have been increased in scale and required to ensure a high failure detection rate. Therefore, in semiconductor integrated circuit design, extensive testability design is performed to increase the failure detection rate.

  As a design for testability, there is a method of improving a failure detection rate by inserting a failure detection circuit. For example, Patent Document 1 describes an example in which BIST (Built-In Self Test) is used as a failure detection circuit. Patent Document 2 describes an example in which a scan circuit (scan path) is used as a failure detection circuit.

  However, even if a failure detection circuit is inserted in the design for testability, a portion that cannot be controlled or observed occurs, and a circuit element that cannot detect a failure (hereinafter referred to as an undetected failure element) may occur.

  In the conventional automatic placement and routing apparatus, timing and wiring connectivity are taken into consideration, but undetected faulty elements are not taken into consideration. Therefore, undetected faulty elements on the same wiring may be arranged and wired far away. At that time, the automatic placement and routing device may satisfy the requirements by inserting circuit elements in the undetected failure part without satisfying the design constraints such as the required timing and design rules determined by each manufacturing technology. . In that case, the inserted circuit element also becomes an undetected failure element, and the number of undetected failure elements increases, which causes a problem that the failure detection rate of the semiconductor integrated circuit decreases.

  The present invention aims to solve such problems.

  In other words, an object of the present invention is to provide an automatic placement and routing apparatus and an automatic placement and routing method in which the failure detection rate is not lowered in consideration of the undetected failure element.

In order to solve the above-described problem, the invention described in claim 1 includes circuit information acquisition means for acquiring circuit element information and wiring information in a semiconductor integrated circuit stored in the first storage device, In an automatic placement and routing apparatus comprising placement and routing means for placing and routing the circuit elements, undetected information stored in a second storage device, which is information on circuit elements that cannot be detected as faults comprising a undetected fault element information obtaining means for obtaining the failure element information, the placement and routing means, and the circuit element information and wiring information circuit information acquisition unit acquires, before Symbol undetected fault element information, on the basis , close to the wire length to satisfy the design rule is a design constraint that is predetermined wiring between circuit elements can not be more than the fault detection which is connected in the same interconnection An automatic placement and routing device, characterized by the arrangement.

  According to the first aspect of the present invention, the placement and routing unit is based on the circuit element information and the wiring information acquired by the circuit information acquisition unit, and the undetected failed element information acquired by the undetected failed element information acquisition unit. Since the circuit elements connected to the same wiring that cannot detect a fault are arranged close to each other so that the wiring length satisfies the design rule, the wiring between undetected faulty elements can be shortened. Insertion of circuit elements is unlikely to occur at the location, and an increase in undetected failure elements can be prevented so that the failure detection rate is not lowered.

1 is a configuration diagram of an automatic placement and routing apparatus according to an embodiment of the present invention. FIG. 2 is a configuration diagram showing a functional configuration of the automatic placement and routing apparatus shown in FIG. 1. It is the circuit diagram which showed the example of the logic circuit containing an undetected failure element. It is explanatory drawing which showed the example of the arrangement | positioning wiring pattern of the logic circuit diagram shown by FIG. FIG. 4 is a circuit diagram showing an example in which circuit elements are inserted to satisfy the design rule in the logic circuit shown in FIG. 3. FIG. 6 is an explanatory diagram showing an example of a placement and wiring pattern of the logic circuit diagram shown in FIG. 5. FIG. 4 is an explanatory diagram showing an example of an arrangement wiring pattern in which circuit elements are arranged close to each other in the logic circuit shown in FIG. 3. It is the block diagram which showed the functional structure of the automatic placement-and-wiring apparatus concerning other embodiment of this invention.

  Hereinafter, an embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a configuration diagram of an automatic placement and routing apparatus according to an embodiment of the present invention. FIG. 2 is a configuration diagram showing a functional configuration of the automatic placement and routing apparatus shown in FIG. FIG. 3 is a circuit diagram illustrating an example of a logic circuit including an undetected fault element. FIG. 4 is an explanatory diagram showing an example of the placement and wiring pattern of the logic circuit diagram shown in FIG. FIG. 5 is a circuit diagram showing an example in which circuit elements are inserted to satisfy the design constraints in the logic circuit shown in FIG. FIG. 6 is an explanatory diagram showing an example of the arrangement and wiring pattern of the logic circuit diagram shown in FIG. FIG. 7 is an explanatory diagram showing an example of an arrangement / wiring pattern in which circuit elements are arranged close to each other in the logic circuit shown in FIG.

  An automatic placement and routing apparatus 10 shown in FIG. 1 includes a processing device 1 that performs placement and routing of circuit elements included in a semiconductor integrated circuit, a keyboard 2 and a mouse that input various information and various commands to the processing device 1. 3 and the like, a storage device 4 for storing data and programs, and a display device 5 for displaying an input screen (for example, GUI: graphical user interface) and displaying a processing result. As is clear from FIG. 1, the automatic placement and routing apparatus 10 includes a normal computer and its peripheral devices. Note that a pointing device such as a tablet or a trackball may be used instead of the mouse 3. In addition, a semiconductor memory, a hard disk, or the like is arbitrarily used for the storage device 4, and a CRT, a liquid crystal display, or the like is arbitrarily used for the display device 5, for example.

  FIG. 2 shows a functional configuration of the automatic placement and routing apparatus 10. The automatic placement and routing apparatus 10 includes a placement unit 20, a post-placement optimization unit 21, a clock tree synthesis unit 22, a post-clock tree optimization unit 23, a wiring unit 24, and a post-route optimization unit 25. And. The processing device 1 in FIG. 1 functions as the placement unit 20, the post-placement optimization unit 21, the clock tree synthesis unit 22, the post-clock tree optimization unit 23, the wiring unit 24, and the post-wiring optimization unit 25. .

  The placement unit 20 includes information 30 necessary for placement and routing such as a cell library, a net list, a design rule, and timing constraints, that is, circuit element information and wiring information, and undetected failure information 31 that is information on circuit elements that cannot be detected. , And the floor plan is executed, the chip size, the I / O arrangement position, the hard macro arrangement position, etc. are determined and the cells are arranged. Note that information 30 necessary for placement and routing and undetected failure information 31 are stored in advance in the storage device 4, for example. That is, the storage device 4 functions as a first storage device and a second storage device, and the placement unit 20 functions as a circuit information acquisition unit, an undetected fault element information acquisition unit, and a placement and routing unit. The information 30 necessary for the placement and routing and the undetected failure information 31 may be stored in different storage devices.

  The design rule is a restriction on the layout and wiring design of circuit elements such as the minimum dimensions of elements, the distance between elements, the wiring width and the distance between wirings, and the timing constraint is between the flip-flops of the circuit. This is a restriction of allowable delay time such as a data transfer delay time (operation frequency). The design rules and timing constraints correspond to the design constraints in the claims.

Undetected failure information 31, type and unique name and connection information of the circuit elements has become undetected fault elements like included (undetected fault element information), with this information, for example (not shown) other devices The result of failure simulation may be used. Of course, the automatic placement and routing apparatus 10 may have a failure simulation function, read a netlist or the like, perform a failure simulation, and generate undetected failure information 31 from the result.

  The post-placement optimization unit 21 optimizes the cell placement performed by the placement unit 20.

  The clock tree synthesizing unit 22 recognizes the clock signal and the flip-flop in the netlist, and synthesizes a clock tree for connecting the clock signal and each flip-flop.

  The post-clock tree optimizing unit 23 optimizes the arrangement of clock drivers and the like based on the clock tree synthesized by the clock tree synthesizing unit 22.

  The wiring unit 24 connects each circuit element optimized by the optimization unit 21 after placement and the optimization unit 23 after clock tree by wiring. That is, the wiring unit 24 functions as a placement and routing unit.

  The optimization unit after the wiring optimizes the wiring performed by the wiring unit 24 based on the design rule and the design constraint of the timing constraint so as to satisfy them.

  That is, the layout data 32 is finally output by sequentially performing processing from the placement unit 20 to the post-wiring optimization unit 25. The layout data 32 is output to the storage device 4, for example. Accordingly, FIG. 2 shows a functional configuration and a processing flow.

  Next, the placement and routing of undetected faulty elements in the automatic placement and routing apparatus 10 having the above-described configuration will be described with reference to FIGS.

  FIG. 3 is a circuit diagram showing an example of a logic circuit that becomes an undetected failure element. In the circuit diagram of FIG. 3, it is assumed that the output of another circuit element is connected to one input I1 of the 2-input AND element c11. The other input I2 of the 2-input AND element c11 is connected to the low level (binary number “0”) n12.

  The output O of the 2-input AND element c11 is connected to the inputs I of the driver elements c12 and c13. Assume that the outputs O of the driver elements c12 and c13 are connected to different circuit elements.

  In the logic circuit of FIG. 3, since the low level n12 is connected to the other input I2 of the 2-input AND element c11, the wiring n11 to which the output O of the 2-input AND element c11 is connected is always at the Low level. . Therefore, since the driver elements c12 and c13 connected to the wiring n11 do not transition to the Hi level, it is not possible to detect a failure as to whether or not they can transition to the Hi level, and these three circuit elements become undetected failure elements. .

  An example in which the logic circuit of FIG. 3 is arranged and wired is shown in FIG. The wiring n11 may be wired to a length that does not satisfy the design constraints because the elements are arranged apart from each other.

  Therefore, a circuit element may be inserted to satisfy the design constraint. FIG. 5 shows a logic circuit diagram in which circuit elements are inserted, and FIG. 6 shows a layout wiring diagram. This is a circuit element in which the driver elements c22 and c23 of FIGS. 5 and 6 are inserted. The driver element c22 has an input I connected to the wiring n11 and an output O connected to the wiring n22. The input I of the driver c12 is connected to the wiring n22. That is, the driver element c22 is inserted between the 2-input AND element c11 and the driver element c12.

  The driver element c23 has an input I connected to the wiring n11 and an output O connected to the wiring n23. The input I of the driver element c12 is connected to the wiring n23. That is, the driver element c23 is inserted between the 2-input AND element c11 and the driver element c13.

  The inputs and outputs of the driver elements c22 and c23 shown in FIG. 5 and FIG. 6 are inserted and connected to the undetected failure portion, so that the failure cannot be detected and the undetected failure element. As a result, the number of undetected failure elements increases and the failure detection rate deteriorates.

  Therefore, in the present embodiment, the undetected faulty elements are placed and wired close to each other. Specifically, in the placement unit 20 or the like, based on the undetected failure information 31, the undetected failure element and the wiring to which the undetected failure element is connected are recognized, and the wiring length that satisfies the design constraint As such, related undetected faulty elements are placed close to each other and wired. FIG. 7 shows an example in which related undetected failure elements are arranged and wired close to each other in the arrangement and wiring example of FIG. That is, based on the circuit element information and the wiring information and the undetected failed element information acquired by the undetected failed element information acquisition unit, a plurality of circuit elements connected by the same wiring that cannot detect the failure satisfy the design constraints. It arranges so that it may become near so that it may become wiring length.

  According to the present embodiment, the placement unit 20 uses the acquired information 30 necessary for placement and routing and the undetected failure information 31 to allow the wiring between circuit elements that cannot detect a failure to satisfy the design constraints. Since they are arranged close to each other, the wiring between undetected faulty elements can be shortened, circuit elements are less likely to be inserted at the relevant locations, and an increase in undetected faulty elements is prevented. The failure detection rate can be prevented from being lowered.

  That is, in consideration of undetected failure information in addition to information conventionally considered at the time of placement and routing, such as design constraints, it is possible to perform processing in consideration of the failure detection rate at the time of placement and routing.

  For example, there may be a case where an undetected failure element cannot be placed close to each other as described above for convenience of placement of other circuit elements. In this case, as shown in FIG. 5 and FIG. 6, there is a possibility that an undetected failure element is inserted and the failure detection rate is lowered. In that case, an appropriate element may be added or changed (circuit change) so that an undetected failure element can be detected as a failure, and placement and routing may be performed. That is, the automatic placement and routing apparatus 10 includes circuit changing means. The circuit changing unit may be provided as a single functional block, or the placement unit 20 may also serve as the circuit changing unit. When the circuit is changed, a changed netlist is generated.

  As an example of the circuit change described above, in FIG. 3, for example, the value (Low level) of the input I2 of the 2-input AND element c11 can be set directly from the external terminal. In this way, since the value can be directly input from the external terminal, the Hi level can be given to the input I2 only during the test, and the failure can be detected. Alternatively, the two-input AND element c11 may be deleted and the Low level may be directly input to the driver elements c12 and c13. In this case, the driver elements c12 and c13 remain undetected fault elements, but the 2-input AND circuit c11 is deleted, so that no circuit elements are inserted and the fault detection rate does not decrease.

  Further, when performing automatic placement and routing, the processing from the placement unit 20 to the optimization unit 25 after wiring shown in FIG. 2 is often repeated. At that time, if automatic placement and routing is performed in consideration of design constraints, logic elements may be inserted so as to satisfy the requirements of placement and routing. By inserting this element, the undetected failure information 31 may be different from that originally obtained. Therefore, for example, as shown in FIG. 8, after the optimization unit 25 after wiring, the undetected failure element redetection unit 26 performs redetection of the undetected failure element, and when the update is necessary, the undetected failure element is detected. The information update unit 27 may update the undetected failure information 31.

  Further, not limited to the example of FIG. 8, for example, the information generated in the placement unit 21 is output to the undetected failed element redetection unit 26, and when the update is necessary, the undetected failed element information update unit 27 detects the undetected failed element. It is also possible to update the information related to the information and output it to the optimization unit 21 after placement. That is, the processing results in the placement unit 21 to the optimization unit 25 after wiring are output to the undetected failed element re-detection unit 26, respectively, and when the update is necessary, the undetected failed element information update unit 27 performs the undetected failed element. It is also possible to update the information on the information and output it to the next processing unit (process).

  By doing so, it is possible to perform processing corresponding to a circuit change or the like in the placement and routing in consideration of undetected faulty element information. That is, the undetected failed element redetection unit 26 functions as an undetected failed element detection unit, and the undetected failed element information update unit 27 functions as an undetected failed element information update unit.

  The automatic placement and routing apparatus 10 may be configured as a program that can be read and operated by a computer. In this case, the processing apparatus 1 such as the placement unit 20, the post-placement optimization unit 21, the clock tree synthesis unit 22, the post-clock tree optimization unit 23, the wiring unit 24, and the post-wiring optimization unit 25 shown in FIG. The functioning part is configured as a program. That is, the placement unit 20 functions as a circuit information acquisition step, an undetected faulty element information acquisition step, and a placement and routing step, and the wiring unit 24 functions as a placement and routing step.

  The present invention is not limited to the above embodiment. That is, various modifications can be made without departing from the scope of the present invention.

1 processing device 4 storage device (first storage device, second storage device)
10 automatic placement and routing device 20 placement unit (circuit information acquisition means, placement and routing means, undetected fault element information acquisition means, circuit change means)
21 Optimization Unit after Placement 24 Wiring Unit (Placement and Routing Means)
25 Optimization section after wiring (undetected faulty element detection means)
27 Undetected faulty element information update unit (undetected faulty element information update means)
30 Information required for placement and routing (circuit element information and wiring information)
31 Undetected failure information (information about circuit elements that cannot be detected)
32 Layout data

JP 2007-328852 A JP 2001-83213 A

Claims (4)

An automatic placement and routing apparatus comprising: circuit information obtaining means for obtaining circuit element information and wiring information in a semiconductor integrated circuit stored in the first storage device; and placement and routing means for placing and wiring the circuit elements. In
An undetected fault element information acquisition means for acquiring undetected fault element information that is information of a circuit element that cannot be detected as a fault among the circuit elements stored in the second storage device;
The placement and routing means, and the circuit element information and wiring information circuit information acquisition unit acquires, before SL and undetected fault element information, based on, can not be a plurality of the fault detection which is connected in the same interconnection circuit elements automatic placement and routing device, characterized in that the arranged close so that the wiring length to satisfy the design rule is a design constraint that is predetermined wiring between. If the placement and routing means cannot place the circuit element that cannot detect the failure so as to be close to the wiring length that satisfies the design rule , the circuit element information and the circuit element information including the circuit element that cannot detect the failure are changed. 2. The automatic placement and routing apparatus according to claim 1, further comprising circuit changing means for changing the wiring information. Undetected fault element detection means for detecting the circuit element that cannot be detected again based on the circuit element information and wiring information changed by the circuit change means;
Based on a circuit element that is detected by the undetected faulty element detection unit and cannot detect a fault, the undetected faulty element information update unit that updates the undetected faulty element information;
The automatic placement and routing apparatus according to claim 2, further comprising: In an automatic placement and routing method for placing and wiring circuit elements in a semiconductor integrated circuit by an automatic placement and routing apparatus,
A circuit information acquisition step for acquiring the circuit element information and wiring information stored in the first storage device;
An undetected fault element information acquisition step for acquiring undetected fault element information , which is information of a circuit element that cannot be detected as a fault among the circuit elements, stored in a second storage device;
Based on the circuit element information and wiring information acquired in the circuit information acquisition step and the undetected fault element information acquired in the undetected fault element information acquisition step, wiring between the plurality of circuit elements that cannot detect the fault A placement and routing step that places the wires close to each other so that the wiring length satisfies a design rule that is a predetermined design constraint;
The automatic placement and routing apparatus sequentially executes the automatic placement and routing apparatus.

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