JP2011164921A - Device for designing semiconductor integrated circuit, and method for designing the semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the discharge of a failure caused by a wiring length and the number of vias. <P>SOLUTION: A layout is executed on the basis of first circuit information representing the connection of a circuit including a plurality of cells and a plurality of signal lines (S21), the circuit information is made to be second circuit information, and the wiring length of each of the plurality of signal lines and the number of the vias being the number of via holes through which each of the plurality of signal lines passes are extracted from the execution result of the layout (S22). Failure simulation is executed on the second circuit information, and failure-undetected points being nodes in which a failure cannot be detected are extracted (S23). Weighting is applied to each of the failure-undetected points by using the wiring length and the number of vias (S24). A failure-undetected point in which a calculation value representing a weighting result exceeds a set value is selected among the failure-undetected points, and a test point is inserted into the failure-undetected point (S25). <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit design apparatus and a semiconductor integrated circuit design method for inserting a test point at a corresponding location of a semiconductor integrated circuit.

  Japanese Laid-Open Patent Publication No. 2000-250946 discloses a design apparatus that performs a failure simulation on a semiconductor integrated circuit and inserts a test point into a signal line that is a corresponding portion as a conventional semiconductor integrated circuit design apparatus.

  FIG. 1 shows the configuration of a conventional semiconductor integrated circuit design apparatus. The design apparatus includes a computer 101, an input device 104, and an output device 105.

  The computer 101 includes a processing unit 102 and a storage unit 103. The storage unit 103 stores a computer program to be executed by the computer 1. The processing unit 2 reads and executes a computer program from the storage unit 103 at the time of startup or the like.

  The processing unit 102 includes a test point insertion processing unit 110. The test point insertion processing unit 110 includes a failure simulation processing unit 11. The failure simulation processing unit 11 generates a plurality of test patterns randomly and executes a failure simulation.

  FIG. 2 is a flowchart showing the operation of a conventional semiconductor integrated circuit design apparatus (conventional semiconductor integrated circuit design method).

  The test point insertion processing unit 110 inputs circuit information 6 (net list), which is circuit information indicating the connection of the semiconductor integrated circuit, and stores it in the storage unit 103. The semiconductor integrated circuit represented by the circuit information 6 includes a plurality of cells (a plurality of elements) and a plurality of signal lines, and the circuit information 6 represents a connection between the plurality of cells and the plurality of signal lines (step S1). ).

  Here, the designer gives the computer 1 design conditions including the number of patterns and the target failure detection rate by operating the input device 4. The failure simulation processing unit 11 of the test point insertion processing unit 110 randomly generates a plurality of test patterns based on the number of patterns included in the design condition, and applies the circuit information 6 based on the plurality of test patterns. A failure simulation is executed (step S2).

  The test point insertion processing unit 110 checks whether or not the failure detection rate obtained by executing the failure simulation has reached the target failure detection rate included in the design condition (step S3).

  Here, when the failure detection rate does not reach the target failure detection rate (step S3-NO), the test point insertion processing unit 110 detects failure among the plurality of signal lines of the semiconductor integrated circuit represented by the circuit information 6. When a signal line whose failure has been prevented by simulation is a failure prevention signal line group, a failure that associates information representing each of the failure prevention signal line groups with the number of times the failure has been blocked by the failure simulation (failure prevention information) Generate a blocking information list. The test point insertion processing unit 110 has a predetermined number of signal lines from the failure prevention signal line group represented by the failure prevention information list in order from the highest number of times the failure has been blocked, or the number of times the failure has been blocked is predetermined. A signal line exceeding the number of times is extracted as an insertion candidate signal line, and a test point candidate list representing it is generated (step S6).

  The test point insertion processing unit 110 checks whether there is a signal line that has not been evaluated for test point insertion in the insertion candidate signal lines represented by the test point candidate list (step S7).

  When there is a signal line that has not been evaluated for test point insertion among the insertion candidate signal lines (step S7—YES), the test point insertion processing unit 110 selects one of the insertion candidate signal lines. An insertion candidate signal line is selected as an insertion target signal line (step S8).

  The test point insertion processing unit 110 virtually inserts a test point into the insertion target signal line of the semiconductor integrated circuit represented by the circuit information 6 (step S9).

  The failure simulation processor 11 of the test point insertion processor 110 executes a failure simulation on the circuit information 6 (step S10).

  The test point insertion processing unit 110 checks whether or not the failure detection rate obtained by executing the failure simulation has reached the target failure detection rate (step S11).

  When the failure detection rate has not reached the target failure detection rate (step S11—NO), the test point insertion processing unit 110 executes step S7 again.

  On the other hand, when the failure detection rate reaches the target failure detection rate (step S11—YES), the test point insertion processing unit 110 generates a test point insertion list representing the insertion target signal line (step S12). At this time, the test point insertion processing unit 110 excludes information indicating the insertion target signal line from the insertion candidate signal lines represented by the test point candidate list, and executes Step S7 again.

  When there is no signal line that has not been evaluated for test point insertion among the insertion candidate signal lines (NO in step S7), the test point insertion processing unit 110 executes step S3 again.

  Here, when the failure detection rate reaches the target failure detection rate (step S3-YES), the test point insertion processing unit 110 inserts the test point among the insertion candidate signal lines of the semiconductor integrated circuit represented by the circuit information 6. A test point is inserted into the insertion target signal line represented by the list (step S4).

  The test point insertion processing unit 110 outputs circuit information (a plurality of cells, a plurality of signal lines, and a test point) after inserting a test point to the circuit information 6 as second circuit information 7 (net list). 5 (step S5).

JP 2000-250946 A

  However, the conventional semiconductor integrated circuit design apparatus does not consider the influence on the failure rate due to the wiring length, which is the length of the wiring generated after layout, and the number of vias, which is the number of via holes through which the wiring passes. For example, when the layout is executed for the second circuit information 7 (a plurality of cells of the semiconductor integrated circuit, a plurality of signal lines, test points), the number of signal lines or vias whose wiring length is longer than the reference In some cases, test points are not arranged on signal lines having more than the reference. For this reason, a failure due to the wiring length or the number of vias cannot be detected, and the probability of occurrence of a defect (defect outflow rate) may be larger than the theoretical value.

  In the following, means for solving the problems will be described using the reference numerals used in the embodiments for carrying out the invention in parentheses. This symbol is added to clarify the correspondence between the description of the claims and the description of the mode for carrying out the invention, and the technical scope of the invention described in the claims. Must not be used to interpret

  The semiconductor integrated circuit design apparatus of the present invention includes a layout processing unit (21), a wiring information processing unit (22), a failure simulation processing unit (23), a weighting processing unit (24), and a test point insertion unit (25). It has. The layout processing unit (21) includes a plurality of cells and a plurality of signal lines based on the first circuit information (7) which is circuit information representing connection of a semiconductor integrated circuit including a plurality of cells and a plurality of signal lines. A layout for determining the arrangement is executed (S21). The wiring information processing unit (22) generates the second circuit information (8) that is the circuit information after the layout is executed on the first circuit information (7), and from the layout execution result, The wiring length of each signal line and the number of vias that are the number of via holes through which each of the plurality of signal lines passes are extracted (S22). The failure simulation processing unit (23) executes a failure simulation on the second circuit information (8), and extracts a failure undetected point that is a node where failure cannot be detected (S23). The weighting processing unit (24) weights each of the failure undetected points using the wiring length and the number of vias, the failure undetected points, the signal lines connected to the failure undetected points, A first weighting result list (32) for associating the calculated value representing the result is generated (S24). The test point insertion unit (25) selects, as a first selected failure undetected point, a failure undetected point whose calculated value exceeds the set value from the failure undetected points represented by the first weighting result list (32). Then, a first insertion process for inserting a test point with respect to the first selected failure undetected point is executed (S25).

  As described above, according to the semiconductor integrated circuit design apparatus of the present invention, in consideration of the layout, the test point is inserted into the first selected failure undetected point having a long wiring length and a large number of vias. For this reason, it is possible to reduce the outflow of defects due to the wiring length and the number of vias.

FIG. 1 shows the configuration of a conventional design system. FIG. 2 is a flowchart showing test point insertion processing (step S101) as the operation of the conventional design system (conventional semiconductor integrated circuit design method). FIG. 3 shows the configuration of the design system according to the first embodiment of the present invention. FIG. 4 is a flowchart showing the operation of the design system according to the first embodiment of the present invention (the method for designing a semiconductor integrated circuit according to the first embodiment of the present invention). FIG. 5 is a flowchart showing the first test point insertion process (step S101) of FIG. FIG. 6 is a flowchart showing the second test point insertion process (step S102) of FIG. FIG. 7 shows the layout result information list 21. FIG. 8A is a diagram for explaining the wiring length and the number of vias. FIG. 8B is a diagram for explaining the wiring length and the number of vias, and is a cross-sectional view of the chip wiring layer cut vertically. FIG. 9 shows the first weighting result list 32. FIG. 10A is a diagram for explaining step S30. FIG. 10B is a diagram for explaining step S30. FIG. 11 is a flowchart showing a test point insertion process (step S102) as the operation of the design system according to the second embodiment of the present invention (the method for designing a semiconductor integrated circuit according to the second embodiment of the present invention).

  Exemplary embodiments of a semiconductor integrated circuit designing apparatus according to the present invention will be explained below in detail with reference to the accompanying drawings.

(First embodiment)
FIG. 3 shows the configuration of the semiconductor integrated circuit design apparatus according to the first embodiment of the present invention. The design apparatus includes a computer 1, an input device 4, and an output device 5. The output device 5 includes a display device, a printing device, and an electronic data output device. The computer 1 includes a processing unit 2 and a storage unit 3. The processing unit 2 includes a test point insertion processing unit 110 (hereinafter referred to as a first test point insertion processing unit 110) and a test point insertion processing unit 20 (hereinafter referred to as a second test point insertion processing unit 20). It has.

  The second test point insertion processing unit 20 includes a layout processing unit 21, a wiring information processing unit 22, a failure simulation processing unit 23, a weighting processing unit 24, and a test point insertion unit 25.

  FIG. 4 is a flowchart showing the operation of the semiconductor integrated circuit design apparatus according to the first embodiment of the present invention (semiconductor integrated circuit design method according to the first embodiment of the present invention).

  The first test point insertion processing unit 110 executes a first test point insertion process (step S101).

  FIG. 5 is a flowchart showing the first test point insertion process (step S101) of FIG.

  As described above, the failure simulation processing unit 11 of the first test point insertion processing unit 110 responds to the circuit information 6 that is circuit information representing connection of a semiconductor integrated circuit including a plurality of cells and a plurality of signal lines. A failure simulation is executed (steps S1 and S2). When the failure detection rate obtained by executing the failure simulation does not reach the target failure detection rate, the first test point insertion processing unit 110 selects a corresponding signal line (insertion candidate signal line) from the plurality of signal lines. ) Is inserted into the test information (hereinafter referred to as the first test point) (steps S3, S6 to S12, S4), and the circuit information after the first test point is inserted into the circuit information 6 ( Circuit information 7 that is a plurality of cells, a plurality of signal lines, and a first test point) is output (step S5).

  Since the first test point insertion process is the same as the operation of the conventional semiconductor integrated circuit design apparatus (conventional semiconductor integrated circuit design method), the details thereof are omitted. However, when the designer gives the design conditions to the computer 1 by operating the input device 4, the design conditions include the number of patterns, the target failure detection rate, etc., as well as the set wiring length and the set VIA (via) as reference values. Include a number.

  After the first test point insertion process (step S101) is executed, the second test point insertion processing unit 20 executes the second test point insertion process (step S102).

  FIG. 6 is a flowchart showing the second test point insertion process (step S102) of FIG.

  The layout processing unit 21 executes a layout for determining the arrangement of a plurality of cells and a plurality of signal lines based on the circuit information 7, and generates an execution result of the layout (step S21).

  The wiring information processing unit 22 performs processing described later (step S22).

  The wiring information processing unit 22 generates circuit information 8 (net list) that is circuit information after layout is performed on the circuit information 7. Since the layout processing unit 21 may automatically add a buffer, an inverter, and the like to the circuit as necessary in order to maintain the predetermined performance during the execution of the layout described above, the circuit information 8 is different from the circuit information 7. There is a case.

  Further, the wiring information processing unit 22 extracts the wiring length of each of the plurality of signal lines and the number of vias that are the number of via holes through which each of the plurality of signal lines passes from the layout execution result, and FIG. Is generated and stored in the storage unit 3. The layout result list 31 associates information representing each of the plurality of signal lines, information representing the wiring length of each of the plurality of signal lines, and information representing the number of vias of each of the plurality of signal lines.

  For example, as illustrated in FIG. 8A, the output terminal of the cell 41 and the input terminal of the cell 42 among the plurality of cells are connected to the signal line 40 among the plurality of signal lines. As shown in FIG. 8B, the wiring length of the signal line 40 indicates a total value of the lengths of the plurality of wiring layers, and the number of vias of the signal line 40 is the number of via holes provided between the plurality of wiring layers. Shows the number.

  The wiring information processing unit 22 outputs the circuit information 8 and the layout result list 31 to the storage unit 3. Here, the wiring information processing unit 22 is divided into the first and second wiring information processing units 22 so as not to put a load on the processing. The process of generating the information 8 is executed, and the second wiring information processing unit 22 determines the wiring length of each of the plurality of signal lines and the number of vias generated in each of the plurality of signal lines from the layout execution result. The number of vias may be extracted.

  The failure simulation processing unit 23 generates a test pattern by ATPG (Automatic test pattern generation) or the like based on the circuit information 8 and the design condition, and executes a failure simulation on the circuit information 8 based on the test pattern. At this time, the failure simulation processing unit 23 obtains a failure undetected point and a failure detection rate which are nodes (signals or nets) that cannot detect a failure of the semiconductor integrated circuit represented by the circuit information 8 as a result of executing the failure simulation ( Step S23).

Here, the failure detection rate is a numerical value indicating how much of the failures in the circuit can be detected,
(Number of failures detected ÷ Number of failures defined) × 100 (%)
And so on. Here, the failure detection number is the total number of failures that can be detected by the prepared test pattern, and the failure definition number indicates the total number of possible failures. In order to determine the number of fault definitions, it is necessary to determine a fault model, and a stuck-at fault model is often used.

  Note that the failure detection rate calculation method does not necessarily need to be based on the above calculation method, and may be based on an arbitrary calculation method.

The weighting processing unit 24 weights each of the failure undetected points among the plurality of signal lines represented by the layout result list 31 by using the wiring length and the number of vias, as shown in FIG. One weighting result list 32 is generated and stored in the storage unit 3. For example, when the wiring length and the number of vias are A and B, respectively, and the weighting coefficients are KA and KB, the calculated value C representing the weighting result is:
C = A × KA + B × KB
Is calculated by The first weighting result list 32 associates the net name of each failure undetected point, its wiring length, the number of vias, and information representing the calculated value (step S24).

  The test point insertion unit 25 selects, as a first selected failure undetected point, a failure undetected point whose calculated value exceeds a predetermined set value from the failure undetected points represented by the first weighting result list 32. In this case, the wiring length of the signal line connected to the first selected failure non-detection point is longer than the set wiring length, or the number of vias of the signal line is larger than the set via number. The test point insertion unit 25 executes a first insertion process for inserting a test point (referred to as a second test point) with respect to the first selected failure undetected point (step S25).

  The failure simulation processing unit 23 performs a failure simulation on the circuit information 9 that is the circuit information after the first insertion processing is executed, and obtains a failure undetected point and a failure detection rate (step S26). At this time, the failure simulation processing unit 23 checks whether or not the failure detection rate obtained by executing the failure simulation has reached the target failure detection rate (step S27).

  If the failure detection rate is less than the target failure detection rate (NO in step S27), the weighting processing unit 24 uses the wiring length, the number of vias, A second weighting list that associates the calculated values with each other is generated. The test point insertion unit 25 selects a predetermined number of failure undetected points in descending order from the highest calculated value from the failure undetected points represented by the second weighted result list as the second selected failure undetected points. To do. The test point insertion unit 25 executes a second insertion process for inserting a test point (referred to as a third test point) with respect to the second selected failure undetected point (step S28).

  The failure simulation processing unit 23 executes a failure simulation on the circuit information 10 that is the circuit information after the second insertion processing is executed (step S26). At this time, the failure simulation processing unit 23 checks whether or not the failure detection rate obtained by executing the failure simulation has reached the target failure detection rate (step S27).

  If the failure detection rate has not reached the target failure detection rate (step S27-NO), step S28 is executed again.

  On the other hand, when the failure detection rate is equal to or higher than the target failure detection rate (YES in step S27), the test point insertion unit 25 does not insert a new test point, and is the next step S29. Migrate to

  The wiring information processing unit 22 outputs the circuit information 9 and 10 (net list) after the first and second insertion processes are completed and the list of nodes into which the test points are inserted to the storage unit 3, and the storage unit 3 It is stored (step S29).

  In the case where the layout is executed after the second test point insertion process (step S102) is executed, the cell position and wiring are set as step S30 so as not to move the existing cells and signal lines whose circuits are not changed as much as possible. It is desirable to implement with ECO (Engineering Change Order) which keeps information.

  When the test point insertion unit 25 inserts a test point in the signal line between the output terminal of one of the plurality of cells and the input terminal of the other cell in steps S25 and S28. The test point is provided not near the output terminal of one cell but near the input terminal of another cell. Thereby, it is possible to effectively detect a failure due to a wiring having a long wiring length or a large number of vias.

  For example, as shown in FIG. 10A, the cells 61 and 62 are connected to the signal line 50, and the inverter circuits 63 to 65 have their inputs connected to the signal lines 50 to 52, respectively, and their outputs connected to the signal lines 51 to 51, respectively. It is assumed that the correction target test point is provided in the vicinity of the output terminal of the cell 61. In this case, the effect of reducing the outflow of defects due to the wiring length and the number of vias is reduced. Therefore, as shown in FIG. 10B, the test point insertion unit 25 corrects to the failure undetected signal line 53 instead of the signal line 50 so that the correction target test point is provided in the vicinity of the input terminal of the cell 62. Insert the target test point.

  As described above, the test point insertion unit 25 includes a plurality of stages of inverter circuits 63 to 65 on the signal line between one cell 61 and another cell 62, and the output terminal of one cell 61 When the correction target test point is inserted into the first signal line 50 between the first-stage inverter circuit 63 among the inverter circuits 63 to 65 of the stage, the first signal line 50 in steps S25 and S28. Instead, the test point to be corrected is inserted into the second signal line 53 between the inverter circuit 65 at the last stage among the plurality of stages of inverter circuits 63 to 65 and the input terminal of the other one cell 62. .

  The designer can obtain information required by the designer from the output device 5 from the circuit information 9 and 10 and the layout information stored in the storage unit 3. In this case, the designer gives the processing unit 2 an output instruction for outputting information required by the designer in a predetermined format. In response to the output instruction, the wiring information processing unit 22 reads information required by the designer from the storage unit 3 and outputs the information to the output device 5 in a predetermined format.

  As described above, according to the semiconductor integrated circuit design apparatus of the first embodiment of the present invention, it is possible to reduce the outflow of defects due to the wiring length and the number of vias.

  The reason is that when the layout is executed for the circuit information 7 (a plurality of cells of the semiconductor integrated circuit, a plurality of signal lines, a first test point), a signal line whose wiring length is longer than the reference, or A cell such as a buffer or an inverter may be generated on a signal line having a larger number of vias than a reference. In this case, the probability of occurrence of a defect (defective outflow rate) becomes larger than the theoretical value.

  Therefore, in the semiconductor integrated circuit design apparatus according to the first embodiment of the present invention, when the second test point insertion processing unit 20 executes the above-described second test point insertion processing (step S102), after layout. A test point (second and third test points) is inserted into a failure undetected point where the calculated value weighted by the wiring length and the number of vias is greater than a predetermined value for each of the failure undetected points. For this reason, it is possible to effectively detect a failure due to the wiring length or the number of vias.

  In the semiconductor integrated circuit design apparatus according to the first embodiment of the present invention, the first test point insertion processing unit 110 and the second test point insertion processing unit 20 may be provided in separate apparatuses.

(Second Embodiment)
FIG. 11 is a flowchart showing a test point insertion process (step S102) as the operation of the design system according to the second embodiment of the present invention (the method for designing a semiconductor integrated circuit according to the second embodiment of the present invention).

  In the first embodiment, after performing the first test point insertion process (step S101) for performing the test point insertion process based on the net list, the test points are inserted based on the wiring length and the number of vias after layout. Although the second test point insertion process (step S102) to be performed is performed, in the second embodiment, the first test point insertion process (step S101) is not performed.

  In the second embodiment, only the first test point insertion process (step S101) is deleted from the first embodiment, and a detailed description of the flowchart is omitted.

  In the second embodiment, as in the second test point insertion process (step S102) of the first embodiment, test points are inserted into wirings having a long wiring length or a large number of vias. Also, the outflow of defects due to the wiring length and the number of vias can be reduced.

(Third embodiment)
In the semiconductor integrated circuit design apparatus according to the first and second embodiments, the weighting processing unit 24 weights each failure undetected point based on the wiring length and the number of vias, and then the test point insertion unit 25. Thus, the test point is inserted at the failure undetected point exceeding the predetermined set value. However, as the third embodiment, the weighting unit 24 does not perform weighting and the wiring length is equal to or greater than the predetermined set value. Processing may be performed in which test points are added to all of the failure undetected points, and further, test points are added to all of the failure undetected points that pass through the number of vias greater than or equal to a predetermined value.

  Also in the third embodiment, since test points are inserted into wirings having a long wiring length or a large number of vias, it is possible to reduce outflow of defects due to the wiring length or the number of vias.

1 computer,
2 processing section,
3 storage unit,
4 input devices,
5 output device,
6 Circuit information,
7 Circuit information,
8 Circuit information,
9 Circuit information,
10 Circuit information,
11 Failure simulation processing unit,
20 test point insertion processing unit (second test point insertion processing unit),
21 layout processing unit,
22 Wiring information processing unit,
23 Fault simulation processing unit,
24 weighting processing unit,
25 Test point insertion part,
31 Layout result list,
32 first weighting result list,
40 signal lines,
41, 42 cells,
50-53 signal line,
61, 62 cells,
63-65 inverter circuit,
101 computer,
102 processing unit,
103 storage unit,
104 input devices,
105 output device,
110 Test point insertion processing unit (first test point insertion processing unit)

Claims (13)

A layout that executes a layout for determining the arrangement of the plurality of cells and the plurality of signal lines based on first circuit information that is circuit information representing connection of a semiconductor integrated circuit including a plurality of cells and a plurality of signal lines. A processing unit;
Generating second circuit information which is circuit information after executing the layout on the first circuit information; and, from the execution result of the layout, wiring lengths of the plurality of signal lines, A wiring information processing unit that extracts the number of vias that is the number of via holes that each of the plurality of signal lines passes through;
A fault simulation processing unit that executes fault simulation on the second circuit information and extracts a fault undetected point that is a node that cannot detect a fault;
Each of the failure undetected points is weighted using the wiring length and the number of vias, and the failure undetected points, the signal lines connected to the failure undetected points, and the weighting results are obtained. A weighting processing unit that generates a first weighting result list that associates the calculated values to be represented;
A failure undetected point whose calculated value exceeds a set value is selected as a first selected failure undetected point from the failure undetected points represented by the first weighted result list, and the first selected failure undetected point is selected. A design apparatus for a semiconductor integrated circuit, comprising: a test point insertion unit that executes a first insertion process for inserting a test point with respect to a detection point. The failure simulation processing unit performs detection of a failure undetected point and calculation of a failure detection rate with respect to the third circuit information which is circuit information after the first insertion processing is executed,
When the failure detection rate obtained by executing the failure simulation is less than the predetermined failure detection rate,
The weighting processing unit generates a second weighting result list associating each failure undetected point corresponding to the third circuit information with a calculated value representing the weighting result,
The test point insertion unit selects a predetermined number of failure undetected points in descending order from the highest calculated value from among the failure undetected points represented by the second weighted result list. 2. The semiconductor integrated circuit design device according to claim 1, wherein a second insertion process is performed in which the test point is selected as a point and the test point is inserted into the second selected failure undetected point. The failure simulation processing unit performs detection of a failure undetected point and calculation of a failure detection rate for the circuit information after the first insertion processing or the second insertion processing is executed,
When the failure detection rate obtained by executing the failure simulation is equal to or higher than a predetermined failure detection rate,
The test point insertion unit does not add a new test point,
The semiconductor integrated circuit design device according to claim 2, wherein the wiring information processing unit outputs circuit information after the first insertion process or the second insertion process is executed as fourth circuit information. The test point insertion unit inserts the test point in the vicinity of an output terminal of each node when the test point is inserted into the first selected failure undetected point or the second selected failure undetected point. Item 3. The apparatus for designing a semiconductor integrated circuit according to Item 1 or 2. When the wiring length and the number of vias are A and B, respectively, and the weighting coefficients are KA and KB, the calculated value C representing the weighting result is:
C = A × KA + B × KB
The semiconductor integrated circuit design apparatus according to claim 1, which is calculated by: Inserting the test point before the layout is executed and based on the circuit information representing the connection of the semiconductor integrated circuit so that the failure detection rate of the semiconductor integrated circuit becomes a predetermined value or more Further comprising a processing unit;
6. The circuit information according to claim 1, wherein the first circuit information is circuit information representing connection of the semiconductor integrated circuit after inserting the test point with respect to circuit information before execution of the layout. Semiconductor integrated circuit design equipment. Executing a layout for determining an arrangement of the plurality of cells and the plurality of signal lines based on first circuit information which is circuit information representing connection of a semiconductor integrated circuit including a plurality of cells and a plurality of signal lines. When,
Generating second circuit information that is circuit information after the layout is performed on the first circuit information;
Extracting the wiring length of each of the plurality of signal lines and the number of vias that are the number of via holes through which each of the plurality of signal lines passes from the execution result of the layout;
Performing a fault simulation on the second circuit information to extract a fault undetected point that is a node where a fault cannot be detected;
Each of the failure undetected points is weighted using the wiring length and the number of vias, and the failure undetected points, the signal lines connected to the failure undetected points, and the weighting results are obtained. Generating a first weighting result list for associating the calculated value to be represented;
Selecting a failure undetected point whose calculated value exceeds a set value from the failure undetected points represented by the first weighted result list as a first selected failure undetected point;
Performing a first insertion process of inserting a test point to the first selected failure undetected point. Detecting a failure undetected point and calculating a failure detection rate with respect to the third circuit information, which is circuit information after the first insertion processing is executed;
When the failure detection rate obtained by executing the failure simulation is less than the predetermined failure detection rate,
Generating a second weighting result list associating each failure undetected point corresponding to the third circuit information with a calculated value representing the weighting result;
From the failure undetected points represented by the second weighting result list, a predetermined number of failure undetected points in descending order from the highest calculated value are selected as second selected failure undetected points; The method of designing a semiconductor integrated circuit according to claim 7, further comprising a step of executing a second insertion process of inserting the test point into two selected failure undetected points. A step of detecting a failure undetected point and calculating a failure detection rate for circuit information after the first insertion processing or the second insertion processing is performed;
When the failure detection rate obtained by executing the failure simulation is equal to or higher than a predetermined failure detection rate, the first insertion process or the second insertion process is executed without adding a new test point. The method for designing a semiconductor integrated circuit according to claim 8, further comprising: outputting the circuit information as the fourth circuit information. The step of inserting the test point in the vicinity of the output terminal of each node when the test point is inserted at the first selected failure undetected point or the second selected failure undetected point. Or a method for designing a semiconductor integrated circuit as described in 8 above. When the wiring length and the number of vias are A and B, respectively, and the weighting coefficients are KA and KB, the calculated value C representing the weighting result is:
C = A × KA + B × KB
The method for designing a semiconductor integrated circuit according to claim 7, calculated by: Inserting the test point before the layout is executed and based on circuit information representing connection of the semiconductor integrated circuit so that a failure detection rate of the semiconductor integrated circuit becomes a predetermined value or more Further comprising
12. The circuit information according to claim 7, wherein the first circuit information is circuit information representing connection of the semiconductor integrated circuit after inserting the test point with respect to circuit information before execution of the layout. A method for designing a semiconductor integrated circuit. A first test point insertion processing unit for adding a test point based on first circuit information as circuit connection information so that a failure detection rate of the circuit is equal to or higher than a predetermined value; Based on the second circuit information which is the connection information of the circuit after adding the test point, the layout for determining the arrangement of the elements and wirings included in the second circuit information is executed, and the circuit after the layout is executed A second test point insertion processing unit for adding a test point based on third circuit information which is connection information of the semiconductor integrated circuit,
The second test point insertion processing unit executing a layout for determining an arrangement of elements and wirings included in the second circuit information based on the second circuit information;
The second test point insertion processing unit generates the third circuit information which is connection information of the circuit after the layout execution;
The second test point insertion processing unit extracts, from the layout result, a wiring length that is the length of the wiring and a via number that is the number of via holes that the wiring passes;
The second test point insertion processing unit performs a fault simulation on the third circuit information, and extracts a fault undetected point that is a node that cannot detect a fault;
The second test point insertion processing unit weights the failure undetected point using the wiring length and the number of vias, and calculates the failure undetected point and the weighted result. Generating a weighted result list for associating
The second test point insertion processing unit selects, as a first selected failure undetected point, a failure undetected point whose calculated value exceeds a set value from the failure undetected points represented by the weighting result list. Steps,
A method for designing a semiconductor integrated circuit, wherein the second test point insertion processing unit executes a first insertion process of inserting a test point circuit into the first selected failure undetected point.

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