CN111859843B

CN111859843B - Method and device for detecting circuit fault

Info

Publication number: CN111859843B
Application number: CN201910299160.3A
Authority: CN
Inventors: 罗翊修; 陈勇仁; 罗幼岚; 高淑怡
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2019-04-15
Filing date: 2019-04-15
Publication date: 2024-02-06
Anticipated expiration: 2039-04-15
Also published as: CN111859843A

Abstract

The present disclosure relates to a method for detecting circuit faults and a device thereof, wherein the method is used for designing time of a transmission hierarchy of a buffer, and the method comprises the following steps: obtaining each signal point of each buffer from a circuit model based on the RTL design time; generating an attribute list according to each signal point of each buffer, wherein the attribute list comprises an attribute to be verified of each signal point; performing a normal verification operation according to the circuit model and the attribute list to determine whether the attribute of each signal point in the attribute list is true in the circuit model; and generating a circuit fault reason according to the signal points with the unsatisfied attributes.

Description

Method and device for detecting circuit fault

Technical Field

The present invention relates to a method and related apparatus for detecting circuit faults, and more particularly, to a method and related apparatus for detecting digital integrated circuit faults based on a regular method for designing time at a transmission level of a buffer.

Background

Integrated circuits (integrated circuit, ICs) are typically logically designed through a buffer transfer hierarchy (Register Transfer Level, RTL), i.e., the integrated circuits are described in a hardware description language such as Verilog-HDL. After the RTL design time is completed, a quite complicated test flow is needed, and the circuit can be finalized. If an RTL design error is found during circuit design, and a circuit fault (Malfunction) is caused, the RTL design must be modified back and the test flow must be re-performed, or the circuit must be read and directly modified with high difficulty (generally called ECO, engineering Change Order), but in either way, resources are greatly wasted (re-design time and capital waste).

At present, the manner of ensuring the correctness of RTL design is mainly based on simulation (simulation) and grammar detection (line check). In short, simulation detection is to firstly infer the behavior of a circuit under a specific scene, then use software to process RTL design, obtain the actual circuit behavior of the scene, and compare with the inferred result. However, this approach does not substantially achieve complete circuit behavior, and as circuit complexity and the exponential speed of application scenario combinations increase, reliability decreases. On the other hand, grammar checking can check for potential circuit errors caused by grammar, like input null-connect (input-flow) mismatch, wire width mismatch, etc. The grammar detection does not need to expect a result and has high reliability, but is limited to grammar judgment, and cannot detect a fault condition caused by a grammar correct but a design error in practice.

Disclosure of Invention

It is therefore a primary objective of the present invention to provide a method and related apparatus for detecting circuit faults at the design time of a transmission hierarchy of a buffer, so as to solve the above-mentioned problems.

The invention discloses a method for detecting circuit faults, which is used for designing time of a transmission hierarchy of a buffer, and comprises the following steps: obtaining signal points of each buffer from a circuit model based on the buffer transmission level design time; generating an attribute list according to each signal point of each buffer, wherein the attribute list comprises an attribute to be verified of each signal point; performing a normal verification operation according to the circuit model and the attribute list to determine whether the attribute of each signal point in the attribute list is true in the circuit model; and generating a circuit fault reason according to the signal points with the unsatisfied attributes.

The invention also discloses an electronic device for detecting circuit faults of the design time of a buffer transmission level, which comprises: an extraction buffer unit for obtaining each signal point of each buffer from a circuit model based on the design time of the buffer transmission hierarchy; the generation verification attribute unit is used for generating an attribute list according to each signal point of each buffer, wherein the attribute list comprises an attribute to be verified of each signal point; a normal method calculation unit for performing a normal verification operation according to the circuit model and the attribute list, and generating a signal list including signal points whose attributes are not established; and a circuit fault judging unit for generating a circuit fault reason according to the signal list and correcting the circuit model.

The invention also discloses an electronic device for detecting circuit faults of a buffer transmission layer design time, which comprises: a processing unit for executing a program code; a storage unit coupled to the processing unit for storing the program code, wherein the program code instructs the processing unit to execute the following steps: obtaining signal points of each buffer from a circuit model based on the buffer transmission level design time; generating an attribute list according to each signal point of each buffer, wherein the attribute list comprises an attribute to be verified of each signal point; performing a normal verification operation according to the circuit model and the attribute list to determine whether the attribute of each signal point in the attribute list is true in the circuit model; and judging the buffer fault corresponding to the signal point when the attribute of the signal point is not established.

Drawings

Fig. 1 is a schematic diagram of an electronic device according to an embodiment of the invention.

Fig. 2 is a schematic diagram of a circuit fault detection process according to an embodiment of the invention.

Fig. 3 is a flowchart of detecting a circuit fault according to an embodiment of the invention.

FIG. 4A is a schematic diagram of signal points of a register according to an embodiment of the invention.

Fig. 4B to fig. 4D are schematic diagrams illustrating fault inference without switching capability signal points according to an embodiment of the invention.

Detailed Description

Referring to fig. 1, fig. 1 is a schematic diagram of an electronic device 10 according to an embodiment of the invention. In detail, the electronic device 10 is used for detecting circuit faults and comprises a processing unit 100, a storage unit 110 and a transmission interface unit 120. The processing unit 100 may be a microprocessor. The storage unit 110 may be any data storage device for storing a program code 114 and reading and executing the program code 114 by the processing unit 100. The transmission interface unit 120 may be used to receive the circuit model at the RTL design time from other electronic devices (e.g., computer systems) through wired or wireless means. Alternatively, the circuit model of the RTL design time may be stored in the storage unit 110, and read from the storage unit 110 by the processing unit 100.

Referring to fig. 2, a schematic diagram of a circuit fault detection process 20 according to an embodiment of the invention is shown. The circuit fault detection process 20 is used in the electronic device 10 shown in fig. 1. The circuit fault detection process 20 may be compiled into the program code 114 and includes the following steps:

step 201: the signal points for each buffer are obtained from a circuit model based on the buffer transfer level design time.

Step 202: according to each signal point of each buffer, an attribute list is generated, wherein the attribute list comprises the attribute to be verified of each signal point.

Step 203: and performing normal verification operation according to the circuit model and the attribute list to determine whether the attribute of each signal point in the attribute list is established in the circuit model.

Step 204: and generating a circuit failure reason according to the signal points with the unsatisfied attributes.

According to the circuit fault detection process 20, the electronic device 10 extracts all buffers from the circuit model of the buffer transfer level (Register Transfer Level, RTL) design to obtain each signal point of each buffer. Then, the electronic device 10 generates an attribute list for performing the regular verification operation, wherein the attribute list includes each signal point of the register and its corresponding attribute (such as a condition of switching capability). When the electronic device 10 determines that the attribute of the signal point of the register is not satisfied (i.e. the signal has no switching capability) through the normal verification operation, the electronic device 10 can inspect the signal point having no switching capability or all signal points of the register corresponding to the signal point to generate a cause of circuit failure, thereby correcting the circuit model of the RTL design time. Therefore, the time and cost for redesigning the circuit model can be effectively reduced by the circuit fault detection process 20 of the present invention.

It is noted that the Formal Method (Formal Method) is a verification Method in a computer system, which may also be called Formal verification, and the core is model-verification (model-verification), or property-verification (property-verification). When the circuit model is verified by applying the regular method, the attribute (property) of the signal point of the buffer to be verified and the whole system input as the circuit model are judged whether the attribute is necessarily established in the system or not by the regular method, or a counter example may occur. Since the normalization method is based on strict mathematical evidence, the reliability is very high. The method is applied to network server operation, flying software verification, railway system design and the like. The most well known application for integrated circuits is the logical equivalence check (Logic Equivalence Check). The normalization method should be a technique well known to those skilled in the art and will not be described in detail here. The main objective of the present invention is to provide a process for detecting an RTL design circuit.

Please refer to fig. 3, which is a flowchart illustrating a circuit fault detection method according to an embodiment of the invention. The flow of detecting the circuit failure is used for the circuit detecting device 30. The circuit detection device 30 of the present invention includes an extraction buffer unit 300, a verification attribute generation unit 302, a normalization method calculation unit 304, and a circuit failure determination unit 306. Since the RTL design syntax does not directly announce registers on hardware, but signals in the form of registers, it is possible that these signals are combined circuits or truly registers on hardware. The extraction buffer unit 300 processes the whole RTL design syntax with a parser (parser), observes the signals announced in the form of buffers, and how they are specified in the design (assignment) to determine whether the signals correspond to real hardware buffers, and thus obtains the individual signal points of each buffer, such as frequency/reset/output/input. The generated verification attribute unit 302 converts the condition of the switching capability of the frequency/reset/output/input of the register into the verification attribute of the normal method. In other words, the generated verification attribute unit 302 takes as input the respective signal points (i.e., frequency/reset/output/input) of the buffer, and generates attribute lists of switching capabilities for the respective signal points, respectively. Then, the regular method calculation unit 304 takes the attribute list and RTL design generated by the generation verification attribute unit 302 as inputs to perform attribute verification so as to determine whether the frequency/reset/output/input attributes are established on the circuit. In other words, when the regular method calculating unit 304 determines that the attribute of a certain signal point is not satisfied, it represents that the signal has no switching capability, and may further generate a signal list having no switching capability. On the contrary, when the regular method calculating unit 304 determines that the attribute of a certain signal point is valid, it represents that the signal has the switching capability. Finally, the circuit fault determining unit 306 determines that the function of the buffer corresponding to the signal without switching capability cannot operate normally or is not necessary according to the signal list without switching capability. In addition, the circuit fault determining unit 306 can generate a deduced circuit fault report according to the signal list without switching capability, so that the RTL designer can review the design and make corresponding correction accordingly to avoid the occurrence of circuit faults.

Briefly, the present invention provides a method and related apparatus for detecting circuit faults, which can detect that the signal point to be observed has no switching capability at the early stage in the RTL design time, and obtain the related circuit faults accordingly. In an embodiment, the clock signal/reset signal reset/output signal Q/input signal D (as shown in fig. 4A) of the buffer is taken as the observation point, and the signal switching capability of the observation points is obtained by a normal method, so that the electronic device 10 or the circuit detection device 30 of the present invention can enumerate the failure cause of the buffer according to the observation points or signals without switching capability.

Please refer to fig. 4B-4D, which illustrate that the clock/reset/output Q of the register has no switching capability (i.e. the attribute verification is not established). As shown in fig. 4B, when the clock signal clock has no switching capability, the value of the input signal D can never be sent to the output signal Q by triggering the clock signal clock, so that the output signal Q is still always stuck in the reset value of the register after the reset signal reset is released. As shown in fig. 4C, when the reset signal reset has no switching capability, the case is divided into two cases, and if the reset signal reset is always in the reset state, the output signal Q is always stuck in the reset value of the register. However, if the reset state is always set, the buffer will lose the reset capability. As shown in fig. 4D, when the output signal Q has no switching capability, the buffer is not necessary at all. It can be replaced with a constant output component to save area and power consumption. Typically such a fault is caused by the frequency signal clock or the reset signal reset, but it is also possible that the value of the input signal D is never changed. The value of the input signal D is the result of the input logic operation (input logic control) of the register, and may be always unchanged because the logic operation itself is redundant or may be a normal phenomenon of the circuit under a certain configuration. It should be noted that the above-mentioned fault reasons listed for the no-switching-capability signal may be the content of the circuit fault report generated by the circuit fault determining unit 306, so that the RTL designer can quickly inspect and correct the circuit model of the RTL design.

As can be seen from the above, the non-switching capability of the clock/reset/output signal Q may occur simultaneously or separately when the buffer fails. For example, when the clock/reset signal reset has no switching capability, the output signal Q is always a reset value or cannot be reset because the clock cannot be switched but cannot accept the value sent by the input signal D, and the reset signal reset cannot be switched. Thus, the combination of no switching capability may cause multiple types of failures of the registers.

Based on the above-described failure causes, designers often need to revise the RTL design to eliminate it. But in practice it cannot be excluded that the RTL designer is deliberately designed for this. For example, as shown in fig. 4C, when the reset signal reset is never reset, the register loses the reset capability. In general, the reset function is necessary for most registers, but sometimes registers without the reset function are required because of special design considerations. At this time, the RTL design must be inspected and the writing process adjusted so that the extraction register unit 300 or other tools in the design process will not be misidentified. Or to reuse RTL sub-blocks (sub-blocks) on different circuits, so that some signals are intentionally left blank and then matched with the next design flow tool to achieve the required circuit. The designer must also avoid implementing circuits and envisions differences.

All the steps described above, including the proposed steps, may be implemented in hardware, firmware (i.e., a combination of hardware devices and computer instructions, where the data in the hardware devices is read-only software data), or electronic systems. For example, hardware may include analog, digital, and hybrid circuits (i.e., microcircuits, microchips, or silicon chips). The electronic system may include a System On Chip (SOC), a system in package (Sip), a computer module (computer on module, COM), and the electronic device 10/circuit inspection device 30.

In summary, the present invention provides a method for detecting circuit faults, which adopts a regular method, and can globally detect specific faults (malfunctions) of a circuit when a digital integrated circuit is in RTL design time with the assistance of strict mathematical proof, and is not limited to specific usage scenarios. In detail, the invention uses the normal method to obtain the signal points with the attribute not being established/without switching capability, so that the buffer fault can be deduced, and further the RTL design can be corrected. In contrast, if the conventional simulation method is used, the use of the situation must be limited, so that all faults can occur and react on the circuit behavior, but the method is too difficult to be implemented. In addition, if the grammar detection is used, the commercial software has the capability of tracking the connection of the signal, but is limited by the nature of the grammar detection, and all faults cannot be detected.

The foregoing description is only of the preferred embodiments of the invention, and all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

[ symbolic description ]

10. Electronic device

100. Processing unit

110. Storage unit

120. Transmission interface unit

114. Program code

20. Process flow

201 to 204 steps

30. Circuit detecting device

300. Extraction buffer unit

302. Generating verification attribute units

304. Regular method calculation unit

306. Circuit fault judging unit

clock frequency signal

reset signal

Q output signal

And D inputting a signal.

Claims

1. A method for detecting circuit faults for a buffer transmission hierarchy design time, the method comprising:

obtaining signal points of each buffer from a circuit model based on the buffer transmission level design time;

generating an attribute list according to each signal point of each buffer, wherein the attribute list comprises an attribute to be verified of each signal point;

performing a normal verification operation according to the circuit model and the attribute list to determine whether the attribute of each signal point in the attribute list is true in the circuit model; and

generating a circuit failure cause according to the signal points with the unsatisfied attributes, wherein,

the attribute is a switching capability of a signal point, and the attribute list includes a frequency, a reset, an output and an input of the register, and

when the attribute of at least one of the frequency, reset, input and output signal points is not established, it is determined that at least one of the frequency, reset, input and output signal points has no switching capability.

2. The method of claim 1, wherein the step of generating the cause of the circuit fault based on the signal points for which the attribute is not established comprises:

and checking each signal point in the buffer corresponding to the signal point without switching capability to generate the circuit fault cause.

3. The method for detecting a circuit fault as claimed in claim 1, further comprising:

when the attribute of a signal point is determined to be not established, judging that the signal point does not have switching capability;

generating a signal list of signal points without switching capability; and

and generating the circuit fault reason according to the signal list so as to correct the circuit model.

4. An electronic device for circuit fault detection at a buffer transmission hierarchy design time, the electronic device comprising:

an extraction buffer unit for obtaining each signal point of each buffer from a circuit model based on the design time of the buffer transmission hierarchy;

the generation verification attribute unit is used for generating an attribute list according to each signal point of each buffer, wherein the attribute list comprises an attribute to be verified of each signal point;

a normal method calculation unit for performing a normal verification operation according to the circuit model and the attribute list, and generating a signal list including signal points whose attributes are not established; and

a circuit fault judging unit for generating a circuit fault cause for correcting the circuit model according to the signal list, wherein,

5. The electronic device as claimed in claim 4, wherein the circuit fault determining unit is further configured to determine that the signal points in the signal list have no switching capability, and to inspect each signal point in the buffer corresponding to the signal points having no switching capability, so as to generate the circuit fault cause.

6. An electronic device for circuit fault detection at a buffer transmission hierarchy design time, the electronic device comprising:

a processing unit for executing a program code;

a storage unit coupled to the processing unit for storing the program code, wherein the program code instructs the processing unit to execute the following steps:

when the attribute of a signal point is not established, judging the buffer fault corresponding to the signal point, wherein,