CN111859843A - Method and device for detecting circuit fault - Google Patents
Method and device for detecting circuit fault Download PDFInfo
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- CN111859843A CN111859843A CN201910299160.3A CN201910299160A CN111859843A CN 111859843 A CN111859843 A CN 111859843A CN 201910299160 A CN201910299160 A CN 201910299160A CN 111859843 A CN111859843 A CN 111859843A
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- 238000000034 method Methods 0.000 title claims abstract description 45
- 239000000872 buffer Substances 0.000 claims abstract description 51
- 238000013461 design Methods 0.000 claims abstract description 41
- 238000012795 verification Methods 0.000 claims abstract description 23
- 230000005540 biological transmission Effects 0.000 claims abstract description 18
- 238000012545 processing Methods 0.000 claims description 11
- 238000004364 calculation method Methods 0.000 claims description 6
- 239000011536 extraction buffer Substances 0.000 claims description 4
- 238000001514 detection method Methods 0.000 description 12
- 238000010586 diagram Methods 0.000 description 6
- 238000013459 approach Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 238000010606 normalization Methods 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- 238000000605 extraction Methods 0.000 description 2
- 238000010998 test method Methods 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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Abstract
The present disclosure relates to a method and apparatus for detecting circuit failure, the method is used for a buffer transmission level design time, the method includes: obtaining each signal point of each buffer from a circuit model based on the RTL design time; generating an attribute list according to each signal point of each buffer, wherein the attribute list comprises an attribute to be verified of each signal point; performing a formal verification operation according to the circuit model and the attribute list to determine whether the attribute of each signal point in the attribute list is true in the circuit model; and generating a circuit fault reason according to the signal points with the unqualified attributes.
Description
Technical Field
The present invention relates to a method and related apparatus for detecting circuit failure, and more particularly, to a method and related apparatus for detecting circuit failure at buffer level design time based on a regular method.
Background
Integrated Circuits (ICs) are typically logically designed through a Register Transfer Level (RTL), i.e., the IC is described in a hardware description language such as Verilog-HDL. After the RTL design time is completed, a relatively complicated test procedure is required to fix the circuit. If the circuit failure (Malfunction) is caused by the RTL design error found during the circuit design, the RTL design must be modified and the test procedure should be repeated, or the circuit should be read and directly modified with high difficulty (generally called ECO, Engineering ChangeOrder), but in either way, the resources are wasted (the time and money for the redesign is wasted).
At present, the methods for ensuring the correctness of the RTL design mainly include simulation (simulation) and syntax checking (lockeck). In short, the simulation test is to guess the behavior of the circuit under a specific scene, process the RTL design with software, obtain the actual circuit behavior of the scene, and compare the actual circuit behavior with the guessed result. However, this approach does not substantially yield complete circuit behavior, and as circuit complexity and the exponential speed of application scenario combining increase, reliability also decreases. On the other hand, grammar detection may check out potential circuit errors caused by grammars, such as input null connections (input flowing), connection width mismatches, and the like. The syntax detection does not require an expected result and has high reliability, but is limited to syntax judgment and cannot detect a failure due to a syntax error.
Disclosure of Invention
Therefore, the present invention is directed to a method and related apparatus for detecting circuit failure at the buffer transmission level design time to solve the above-mentioned problems.
The invention discloses a method for detecting circuit fault, which is used for designing time of a buffer transmission level, and comprises the following steps: obtaining a signal point of each buffer from a circuit model based on the transmission level design time of the buffer; generating an attribute list according to each signal point of each buffer, wherein the attribute list comprises an attribute to be verified of each signal point; performing a formal verification operation according to the circuit model and the attribute list to determine whether the attribute of each signal point in the attribute list is true in the circuit model; and generating a circuit fault reason according to the signal points with the unqualified attributes.
The invention also discloses an electronic device for detecting circuit fault of buffer transmission level design time, comprising: an extraction buffer unit for obtaining signal points of each buffer from a circuit model based on the transmission level design time of the buffer; a verification attribute generation unit for generating an attribute list according to each signal point of each buffer, wherein the attribute list comprises an attribute to be verified of each signal point; a formal method calculation unit for performing a formal verification operation according to the circuit model and the attribute list, and generating a signal list including signal points whose attributes are not satisfied; and a circuit fault judging unit for generating a circuit fault reason according to the signal list and correcting the circuit model.
The invention also discloses an electronic device for detecting circuit fault of buffer transmission level design time, comprising: a processing unit for executing a program code; a storage unit, coupled to the processing device, for storing the program code, wherein the program code instructs the processing unit to perform the following steps: obtaining a signal point of each buffer from a circuit model based on the transmission level design time of the buffer; generating an attribute list according to each signal point of each buffer, wherein the attribute list comprises an attribute to be verified of each signal point; performing a formal verification operation according to the circuit model and the attribute list to determine whether the attribute of each signal point in the attribute list is true in the circuit model; and when the attribute of a signal point is not established, judging the fault of the register corresponding to the signal point.
Drawings
Fig. 1 is a schematic view of an electronic device according to an embodiment of the invention.
Fig. 2 is a schematic diagram of a circuit fault detection process according to an embodiment of the invention.
FIG. 3 is a flowchart illustrating a method for detecting circuit faults according to an embodiment of the invention.
FIG. 4A is a diagram illustrating signal points of a register according to an embodiment of the invention.
Fig. 4B to fig. 4D are schematic diagrams illustrating a fault inference of a signal point without handover capability according to an embodiment of the invention.
Detailed Description
Referring to fig. 1, fig. 1 is a schematic diagram of an electronic device 10 according to an embodiment of the invention. In detail, the electronic device 10 is used for detecting circuit faults and includes a processing unit 100, a storage unit 110 and a transmission interface unit 120. The processing unit 100 may be a microprocessor. The storage unit 110 may be any data storage device for storing a program code 114, and the program code 114 is read and executed by the processing unit 100. The transmission interface unit 120 may be used to receive the circuit model at the RTL design time from other electronic devices (e.g., computer systems) by wire or wirelessly. Alternatively, the circuit model of the RTL design time may be stored in the storage unit 110, and read from the storage unit 110 by the processing unit 100.
Please refer to fig. 2, which is a schematic diagram of a circuit failure detection process 20 according to an embodiment of the present invention. The circuit fault detection process 20 is used in the electronic device 10 shown in fig. 1. The circuit failure detection process 20 can be compiled into the program code 114 and includes the following steps:
Step 201: the signal points for each buffer are derived from a circuit model based on buffer transmission level design time.
Step 202: an attribute list is generated according to each signal point of each register, wherein the attribute list comprises the attribute to be verified of each signal point.
Step 203: based on the circuit model and the attribute list, a formal verification operation is performed to determine whether the attribute of each signal point in the attribute list is satisfied in the circuit model.
Step 204: according to the signal point with the attribute not being established, a circuit fault reason is generated.
According to the circuit fault detection process 20, the electronic device 10 extracts all the buffers from a circuit model designed in a buffer transfer level (RTL) to obtain each signal point of each buffer. Then, the electronic device 10 generates an attribute list for performing the formal verification operation, wherein the attribute list includes each signal point of the buffer and its corresponding attribute (e.g., the shear stress condition). When the electronic device 10 determines that the attribute of the signal point of the buffer is not satisfied (i.e., the signal has no switching capability) through the normal verification operation, the electronic device 10 can inspect the signal point having no switching capability or all the signal points of the buffer corresponding to the signal point to generate the cause of the circuit failure, so as to modify the circuit model of the RTL design time. Therefore, the time and cost for redesigning the circuit model can be effectively reduced by the circuit fault detection process 20 of the present invention.
It should be noted that the Formal Method (Formal Method) is a verification Method in a computer system, which may also be referred to as Formal verification, and the core of the Formal Method is model-verification (model-verification), or property-verification (property-verification). When the circuit model is verified by applying the regular method, the property (property) of the signal point of the whole system and the register to be verified, which is input as the circuit model, is judged by the regular method whether the property is necessarily established in the system or a counter example (counterexample) may occur. The reliability is very high since the normal method is based on rigorous mathematical proofs. The method is applied to network server operation, flight software verification, railway system design and the like. The most well known application for integrated circuits is the logical Equivalence Check (Logic Equivalence Check). The normalization method is well known to those skilled in the art and will not be described herein. The invention mainly aims to provide a flow for detecting an RTL design circuit.
Please refer to fig. 3, which is a flowchart illustrating a circuit fault detection method according to an embodiment of the invention. The flow of detecting a circuit failure is for the circuit detecting device 30. The circuit inspection apparatus 30 of the present invention includes an extraction register unit 300, a generation attribute verification unit 302, a normalization method calculation unit 304, and a circuit failure determination unit 306. Since the RTL design syntax does not declare the registers in hardware directly, but signals in the form of registers, these signals may be combinatorial circuits or true hardware registers. The extraction buffer unit 300 processes the whole RTL design syntax with a parser (parser), observes the declared signals in the form of buffers, and specifies (assigns) how they are in the design to determine whether the signals correspond to the real hardware buffers, and further derives the signal points of each buffer, such as frequency/reset/output/input. The generate verify attributes unit 302 converts the condition of the frequency/reset/output/input switching capability of the register into the verify attributes of the regular method. In other words, the generate-verify-attribute unit 302 takes each signal point (i.e., frequency/reset/output/input) of the buffer as an input, and generates an attribute list of switching capabilities for each signal point, respectively. Next, the normalization method calculation unit 304 takes the attribute list and the RTL design generated by the generation verification attribute unit 302 as input to perform attribute verification so as to determine whether the frequency/reset/output/input attribute is satisfied on the circuit. In other words, when the regular method calculating unit 304 determines that the property of a signal point is not satisfied, it indicates that the signal has no switching capability, and can further generate a signal list with no switching capability. On the contrary, when the formal method calculation unit 304 determines that the property of a signal point is satisfied, it means that the signal has switching capability. Finally, the circuit failure determining unit 306 determines that the function of the register corresponding to the signal without switching capability cannot be normally operated or is not necessary according to the signal list without switching capability. In addition, the circuit failure determination unit 306 can generate an inference circuit failure report according to the signal list without switching capability, so that the RTL designer can review the design accordingly and perform corresponding correction to avoid the occurrence of circuit failure.
Briefly, the present invention provides a method and related apparatus for detecting circuit faults, which can detect the non-switching capability of the signal point to be observed at an early stage during RTL design time, and obtain the related circuit faults based on the non-switching capability. In one embodiment, the clock signal clock/reset signal reset/output signal Q/input signal D (as shown in FIG. 4A) of the buffer are used as observation points, and the signal switching capability of these observation points is obtained by a regular method, so that the electronic device 10 or the circuit detecting device 30 of the present invention can list the failure cause of the buffer according to the observation points or signals without switching capability.
Please refer to fig. 4B to 4D, which are schematic diagrams illustrating the clock signal clock/reset signal reset/output signal Q of the register without switching capability (i.e. attribute verification is not true). As shown in fig. 4B, when the clock signal clock has no switching capability, the value of the input signal D can never be triggered by the clock signal clock and sent to the output signal Q, so that the output signal Q is always stuck to the reset value of the register after the reset signal reset is released. As shown in FIG. 4C, when the reset signal reset has no switching capability, the situation is divided into two cases, if the reset state is always set, the output signal Q is always stuck to the reset value of the register. However, if the reset state is always set, the buffer will lose the reset capability. As shown in fig. 4D, when the output signal Q has no switching capability, the buffer is not necessary at all. It can be replaced by a constant output component to save area and power consumption. Usually, the cause of such a fault comes from the clock signal or the reset signal reset, but it is also possible that the value of the input signal D is never changed. The value of the input signal D is the result of the input logic cone of the register, and the permanent reason may be that the logic cone itself is redundant or the normal phenomenon of the circuit under a certain configuration. It should be noted that the above mentioned failure causes for the no-switching capability signal can be the contents of the circuit failure report generated by the circuit failure determination unit 306, so that the RTL designer can quickly view and modify the circuit model of the RTL design.
As can be seen from the above, the clock signal clock/reset signal reset/no-switching capability of the output signal Q may occur simultaneously or independently when the buffer fails. For example, when the clock signal clock/reset signal reset is not switched simultaneously, the output signal Q cannot accept the value sent by the input signal D because the clock signal clock cannot be switched, and the reset signal reset cannot be switched, so that the output signal Q is always reset or cannot be reset. Thus, the combination of no switching capability may cause various types of failures in the registers.
For the reasons mentioned above, designers usually need to modify the RTL design for elimination. But in practice it cannot be excluded that the RTL designer intends. For example, as shown in fig. 4C, when the reset signal reset is never in the reset state, the buffer loses the reset capability. Generally, a reset function is necessary for most buffers, but sometimes it is necessary for buffers without a reset function to exist due to special design considerations. At this point, the RTL design must be inspected and the recipe must be adjusted so that the extraction register unit 300 or other tools in the design flow do not misinterpret it. Or to reuse RTL sub-blocks on different circuits, thereby deliberately blanking some signals and matching with the tools in the next design flow to achieve the required circuit. In this case, the designer must also avoid implementing circuits different from what is intended.
All of the steps described above, including the steps suggested, can be implemented by hardware, firmware (i.e., a combination of hardware devices and computer instructions, data in hardware devices being read-only software data), or an electronic system. For example, the hardware may include analog, digital, and hybrid circuits (i.e., microcircuits, microchips, or silicon chips). The electronic system may include a System On Chip (SOC), a system in package (Sip), a computer module (COM), and the electronic device 10/circuit detecting device 30.
In summary, the present invention provides a method for detecting circuit faults, which employs a formal method, and can globally detect a specific fault (fault) of a circuit when a digital integrated circuit is in an RTL design time with the assistance of rigorous mathematical proofs, and is not limited to a specific usage scenario. In detail, the invention uses a formal method to obtain signal points with non-satisfied/non-switchable attributes, so that the fault of the buffer can be deduced, and the RTL design can be corrected. In contrast, if a traditional analog approach is used, the context of use must be limited so that all faults can occur and react on circuit behavior, but this approach is too difficult to implement. In addition, if syntax detection is used, commercial software currently has the capability of tracking the connection of signals, but due to the nature of syntax detection, all faults cannot be detected.
The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made according to the claims of the present invention should be covered by the present invention.
[ notation ] to show
10 electronic device
100 processing unit
110 storage unit
120 transmission interface unit
114 program code
20 flow path
201 to 204 steps
30 circuit detection device
300 extraction buffer unit
302 generate attribute verification unit
304 normal method calculation unit
306 circuit fault judging unit
clock frequency signal
reset signal
Q output signal
D inputting the signal.
Claims (8)
1. A method for detecting circuit failure for a buffer transmission level design time, the method comprising:
obtaining a signal point of each buffer from a circuit model based on the transmission level design time of the buffer;
generating an attribute list according to each signal point of each buffer, wherein the attribute list comprises an attribute to be verified of each signal point;
Performing a formal verification operation according to the circuit model and the attribute list to determine whether the attribute of each signal point in the attribute list is true in the circuit model; and
and generating a circuit fault reason according to the signal points with the unqualified attributes.
2. The method of claim 1, wherein the attribute is a switching capability of a signal point, and the attribute list includes switching capabilities of signal points of a frequency, a reset, an output, and an input of a register.
3. The method of claim 2, further comprising:
and when the attribute of at least one of the frequency, reset, input and output signal points is not satisfied, judging that at least one of the frequency, reset, input and output signal points has no switching capability.
4. The method of claim 3, wherein the step of generating the cause of the circuit fault based on the signal points for which the attribute does not hold comprises:
and checking each signal point in the buffer corresponding to the signal point without switching capability to generate the fault reason of the circuit.
5. The method of claim 2, further comprising:
when the attribute of a signal point is determined not to be established, judging that the signal point has no switching capability;
Generating a signal list of signal points without switching capability; and
and generating the circuit fault reason according to the signal list so as to modify the circuit model.
6. An electronic device for detecting circuit failure of a buffer transmission level design time, the electronic device comprising:
an extraction buffer unit for obtaining signal points of each buffer from a circuit model based on the transmission level design time of the buffer;
a verification attribute generation unit for generating an attribute list according to each signal point of each buffer, wherein the attribute list comprises an attribute to be verified of each signal point; a formal method calculation unit for performing a formal verification operation according to the circuit model and the attribute list, and generating a signal list including signal points whose attributes are not satisfied; and
and a circuit fault judging unit for generating a circuit fault reason according to the signal list and correcting the circuit model.
7. The electronic device as claimed in claim 6, wherein the circuit failure determination unit is further configured to determine that the signal points in the signal list have no switching capability and examine each signal point in the register corresponding to the signal point having no switching capability to generate the cause of the circuit failure.
8. An electronic device for detecting circuit failure of a buffer transmission level design time, the electronic device comprising:
a processing unit for executing a program code;
a storage unit, coupled to the processing device, for storing the program code, wherein the program code instructs the processing unit to perform the following steps:
obtaining a signal point of each buffer from a circuit model based on the transmission level design time of the buffer;
generating an attribute list according to each signal point of each buffer, wherein the attribute list comprises an attribute to be verified of each signal point;
performing a formal verification operation according to the circuit model and the attribute list to determine whether the attribute of each signal point in the attribute list is true in the circuit model; and
when the attribute of a signal point is not satisfied, the register corresponding to the signal point is judged to be in fault.
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| US20180349521A1 (en) * | 2017-06-02 | 2018-12-06 | Synopsys, Inc. | Efficient mechanism of fault qualification using formal verification |
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