JP2008134808A - Function verification device for logic circuit, verification method for function coverage system, and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent omission of a function coverage item in the logic circuit function verification function of a system LSI using a random test pattern and a function coverage and the overlook of any failure accompanying the omission. <P>SOLUTION: This function verification device of a logic circuit is provided with: a function simulator 6 for calculating the comprehension rate (functional coverage) of the functional coverage item whose correct answer has been acquired by a predetermined test program; a code coverage calculation part for calculating the code coverage of a test by the test program; and an unexpected operation detection part 10 for outputting a test pattern when the code coverage changes and the functional coverage does not change during a test as an unexpected operation test pattern 11. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a logic circuit function verification apparatus, a function coverage item verification method, and a program included in a system LSI (semiconductor integrated circuit) and the like, and in particular, performs a logic circuit function test using a random test pattern. The present invention relates to a logic circuit function verification apparatus, a function coverage item verification method, and a program capable of measuring a coverage rate (function coverage).

  In recent years, the functions of system LSIs have become very complex, and it has become a lot of work to verify the functions at the development site. In practice, it is difficult to manually check all the functions of such a system LSI one by one, and a verification method using a random test pattern has come to be performed as a method for solving this. ing. Random test patterns are more complex and diverse than human-thinking test patterns, and have the advantage that unexpected logic faults can be found. Moreover, since it takes an enormous amount of time to manually create a test pattern for verifying all functions of a complex logic circuit, the development time is shortened.

  Here, although the integrity of the test pattern is a problem, when the function verification item that must be satisfied in the design specifications is set as a function coverage item and the random test pattern is generated, the function coverage is satisfied. Whether or not functional verification has been sufficiently performed is determined based on whether or not

  An apparatus for performing function verification of a system LSI using the random test pattern and function coverage is described in Patent Document 1. FIG. 5 is a system configuration diagram substantially equivalent to the function verification device described in Patent Document 1. As a result of simulation of a logic circuit described in RTL (Register Transfer Level) by a function simulator, detected function coverage is shown. Items are reflected in functional coverage.

  Patent Document 2 describes an apparatus that collects code coverage by a logic circuit simulation of a system LSI.

JP 2004-86838 A JP 2001-92873 A

  The above-described conventional technique measures the completeness of the function verification based on the above function coverage, but has a problem that the completeness of the function coverage item serving as the reference cannot be confirmed. A missing function coverage item means that the test is completed without knowing whether the function verification item corresponding to the missing function coverage item has been verified.

  In particular, as described at the beginning, it is extremely difficult to completely extract all the functions in the design specification while the functions of the system LSI are extremely complicated. It is also conceivable that a human error occurs when the extracted function is set as a function coverage item in the function verification apparatus.

  According to the first aspect of the present invention, a function coverage item for which a correct result is obtained by a test using a predetermined test program is obtained with respect to a function coverage item assumed in advance for a logic circuit described in a predetermined hardware description language. A function verification apparatus for a logic circuit including a function simulator for calculating a coverage ratio (function coverage), a code coverage calculation unit for calculating code coverage of a test by the test program, and the code coverage during a test And an unexpected operation detector that outputs a test pattern when the function coverage is not changed as an unexpected operation test pattern. And a program for causing a computer to function as the function verification device (Alternatively, the recording medium storing the program) is provided.

  According to the second aspect of the present invention, a function coverage item that has obtained a correct result by a test using a predetermined test program with respect to a function coverage item assumed in advance for a logic circuit described in a predetermined hardware description language. A function coverage item verification method using a computer system including a function simulator that calculates a coverage rate (function coverage) and a code coverage calculation unit that calculates code coverage of a test by the test program, A computer system detecting the code coverage change; the computer system detecting the function coverage change; the computer system changing the code coverage during testing; and The machine Include the steps of outputting a test pattern generated by said test program when there is no change in coverage as unexpected operation test pattern, a method of verifying a functional coverage items that feature is provided.

  According to the present invention, it is possible to detect a missing function coverage item (setting omission) as an unexpected operation test pattern. If the unexpected operation test pattern is not output, it is possible to confirm the completeness of the function coverage (a state in which all the functions to be verified set from the design specifications are covered).

  Next, the best mode for carrying out the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a function verification apparatus for a logic circuit of a system LSI according to the first embodiment of the present invention. As is clear from comparison between FIG. 1 and FIG. 5, the present embodiment provides the function simulator 6 with a code coverage calculation function, the calculated code coverage, and an unexpected operation detection function (unexpected) using the function coverage. The main feature is that an operation detection unit) is provided.

  The function coverage item (function coverage item) 2 is data in such a manner that the computer device can interpret the verification item 1 set based on the design specification of the system LSI to be verified. More specifically, the function coverage item 2 represents units of functions such as functions that the logic circuit of the system LSI to be verified must have in design specifications, input / output signal conditions, internal register values, and the like. For example, if the verification target is a controller that operates by receiving an instruction command, each instruction command type is a function coverage item, and each type of response to the instruction is also a function coverage item. It becomes.

  The RTL 3 expresses a logic circuit of a system LSI to be verified in a hardware description language at a register transfer level.

  The test program 4 is a program for generating a random test pattern (input signal pattern) for causing the logic circuit to be verified to function randomly and functionally. The test program 4 is read by a computer system constituting the function simulator 6. Generate a test pattern. For example, if the verification target is a controller that operates in response to an instruction command, the test pattern (input signal pattern) is a pattern in which the command type, combination, timing, etc. for inputting the instruction command are randomly arranged. Become.

  The function verification program 5 is a program for confirming whether or not the operation of the logic circuit is operating correctly with respect to the design specification. The function verification program 5 is read by the computer system constituting the function simulator 6 and the operation of the logic circuit to be verified. To verify. Specifically, the function verification program 5 observes the output data of the logic circuit to be verified with respect to the input signal, the value of the internal register, the temporal change of the internal signal, etc., and whether or not they are correct. Determine.

  The function simulator 6 and the unexpected operation detection unit 10 include a central processing unit (CPU) and its peripheral circuits / peripheral devices, and include a built-in semiconductor memory (ROM, RAM, etc.) and an external storage medium (hard disk, magneto-optical disk, etc.). It is configured on a computer system that operates based on the control program recorded in the above.

  The input data to the function simulator 6 includes RTL 3 in which the logic circuit of the system LSI to be verified is described, the test program 4 for generating a random test pattern, and whether the operation of the logic circuit to be verified is correct. Functional verification program 5 and functional coverage item 2.

  The output data of the function simulator 6 is function coverage, code coverage, and test pattern, which are output to the function coverage database 7, code coverage database 8, and test pattern 9, respectively.

  The function coverage is generally known as an index indicating how much a certain test covers the function of the logic circuit. The function coverage of 100% means that all functions to be verified set by the verifier from the design specifications are covered. In the present embodiment, as a result of the logic circuit simulation performed by the function simulator 6, (number of function coverage items detected normally) / (number of all function coverage items) [%] is defined as function coverage.

  Code coverage is generally known as an index representing how much a test program can generate a test pattern that activates a logic circuit. The code coverage is also used as an index of how much redundant RTL description is included. In the present embodiment, when the logic circuit simulation of RTL3 is performed by the function simulator 6, (number of lines of valid code detected (executed)) / (number of lines of all valid codes) [%] Code coverage. Here, the effective code means a code excluding a part that does not represent the operation of the logic circuit in the RTL description.

  FIG. 2 is a block diagram showing a detailed configuration of the function simulator 6. Referring to FIG. 2, the function simulator 6 includes a test pattern generator 12, a logic circuit simulator 14, a code coverage checker 17, a function checker 18, and a function coverage checker 19.

  The test pattern generator 12 executes the input test program 4 and generates a random test pattern 13.

  The logic circuit simulator 14 compiles the RTL 3 in which the logic circuit of the system LSI to be verified is described into an executable code (simulator execution code 15), and generates a random test generated by the test pattern generator 12. The logic circuit to be verified is reproduced (simulated) using the pattern 13 and a logic circuit signal value 16 is output.

  The code coverage checker 17 detects which line in the RTL 3 is executed by the logic circuit simulator 14 based on the input RTL 3 and the simulator execution code 15 output from the logic circuit simulator 14, and stores the code coverage database 8. Update.

  The function checker 18 receives the logic circuit signal value 16 input from the logic circuit simulator 14, the test pattern 13 at that time, and the function verification program 5. The function checker 18 compares the expected operation value of the logic circuit created from the test pattern 13 and the function verification program 5 with the logic circuit signal value 16 to check whether the logic circuit is operating correctly.

  The function coverage checker 19 receives the logic circuit signal value 16, the test pattern 13, and the function coverage item 2. The function coverage checker 19 detects a function coverage item corresponding to the logic circuit signal value 16 and the test pattern 13 when no error is detected by the function checker 18, that is, when the logic circuit is operating correctly. Then, the function coverage database 7 is updated.

  The unexpected operation detection unit 10 monitors the function coverage database 7, the code coverage database 8, and the test pattern 9, and there is a change in the code coverage calculated by the function simulator 6 and there is no change in the function coverage. The test pattern 13 is output as an unexpected operation test pattern.

  When such a function simulator 6 is continuously executed, random test patterns 13 are generated one after another, and the function coverage and code coverage are updated as needed for each test pattern.

  FIG. 3 is a flowchart showing the operation of the unexpected operation detection unit 10 executed every time the test pattern 13 is input. First, the unexpected operation detection unit 10 inputs the test pattern 9 and the data of the function coverage database 7 and the code coverage database 8 output from the function simulator 6 (step S1).

  The unexpected operation detection unit 10 determines whether or not there is a change in the code coverage input this time from the code coverage input last time (step S2). If there is no change in code coverage, the process returns to step S1 and waits for the next input.

  On the other hand, when there is a change in the code coverage, the unexpected operation detection unit 10 determines whether or not the function coverage input this time has changed from the function coverage input last time. (Step S3). If there is a change in the function coverage, the process returns to step S1 and waits for the next input. This is because if there is a change in both code coverage and function coverage, it indicates that the function assumed as the function coverage item has been operated and does not cause a problem.

  On the other hand, when there is no change in the function coverage despite the change in the code coverage, the unexpected operation detection unit 10 outputs the test pattern 9 at this time as the unexpected operation test pattern 11 (step S4). . A change in code coverage indicates that there is a function that has been newly operated according to the input test pattern 9, but there is no change in function coverage despite this, This is because it indicates that the function coverage item is not assumed.

[Example 1]
Subsequently, in order to deepen the understanding of the present invention, an operation example of the function verification device for a logic circuit according to the above embodiment when a simple logic circuit is a verification target will be described in detail.

The design specifications of the logic circuit to be verified in this embodiment are as follows.
Input terminals: IN1, IN2, CMD
Output terminal: OUT
Function: Performs the operation represented by CMD on the input data and outputs the result from OUT. When the CMD is A, the operation A is performed. When the CMD is B, the operation B is performed. When the CMD is C, the operation C is performed.

  FIG. 4 is a diagram of a logic circuit designed to satisfy the above design specifications. Referring to FIG. 4, this logic circuit includes arithmetic units A, B, and C that perform arithmetic operations A, B, and C, and is designed to switch the outputs OUT_A, OUT_B, and OUT_C of each arithmetic unit with a selector according to the value of CMD. ing.

  Here, it is assumed that the arithmetic unit C has a logic failure.

First, the verifier sets the function coverage item 2. The following functional coverage items can be considered from the design specifications to be verified.
Function coverage item 001: CMD is A.
Function coverage item 002: CMD is B.
Function coverage item 003: CMD is C.
Since these function coverage items are set by the verifier based on the design specifications, it is assumed that the function coverage item 003 has been lost due to the verifier's understanding of the design specifications and human error.

Assume that the selector in the logic circuit to be verified has the following description in RTL.
000: case (CMD)
001: A: OUT <= OUT_A;
002: B: OUT <= OUT_B;
003: B: OUT <= OUT_C;
004: endcase

Since lines 0 and 4 of the RTL description do not represent the operation of the logic circuit, the valid codes are lines 1, 2, and 3. Therefore, the target lines for code coverage are as follows.
Code coverage line 001: “A: OUT ≦ OUT_A;
Code coverage line 002: “B: OUT ≦ OUT_B;
Code coverage line 003: “B: OUT ≦ OUT_C;

  It is assumed that the test program 4 randomly generates A, B, and C for CMD and appropriate data for IN1 and IN2. The function verification program 5 generates an expected value of OUT for the values of CMD and IN, compares it with the value of OUT of the logic circuit signal value, and outputs an error if they do not match.

  The test starts with the above assumptions. First, a random test pattern is generated for IN1, IN2, and CMD by the test pattern generator 12, and is input to the logic circuit simulator 14.

  If the CMD at this time is A, information that the code coverage line 001 is detected is recorded in the code coverage database 8. In parallel with this, the function checker 18 confirms whether the value of OUT is the operation A of the values of IN1 and IN2. If there is no error as a result of confirmation by the function checker 18, the function coverage checker 19 determines that the function coverage item 001 has been detected and records it in the function coverage database 7.

  In this case, since the code coverage line 001 is detected and the code coverage is changed, the process proceeds from step S2 in FIG. 3 to step S3. However, since the function coverage item 001 is detected and the function coverage is also changed, it is unexpected. The operation detection unit 10 does not output the unexpected operation test pattern in step S4.

  Next, assuming that a test pattern in which the CMD is B is input, the code coverage line 002 and the function coverage item 002 are detected as in the case where the CMD is A. Accordingly, in this case as well, both code coverage and function coverage change, so the unexpected operation detection unit 10 does not output the unexpected operation test pattern in step S4.

  Next, assuming that a test pattern whose CMD is C is input, information that the code coverage line 003 is detected is recorded in the code coverage database 8. On the other hand, since the function coverage checker 19 cannot find the corresponding function coverage item 003 (because the function coverage item 003 is not set as described above), the function coverage on the function coverage database 7 is changed. I can't let you.

  In this case, the process proceeds from step S2 in FIG. 3 to step S3 and step S4, and the unexpected operation detection unit 10 uses the test pattern at this time (for example, CMD = C, IN1 = X, IN2 = Y) is output. As the unexpected operation pattern is detected in this manner, the verifier can notice that there is at least a lack of functional coverage.

  On the other hand, in the prior art that does not have the function coverage item 2 verification function as described above, all the function coverage items are detected, and the function coverage becomes 100%. This means that the function verification is sufficiently completed. If the above function coverage item 2 is only missing, it is still good. If the function verification program 5 does not have the function of checking that the operation C of OUT1 is IN1 and IN2 when CMD is C, the function checker 18 generates an error. Therefore, the verifier does not notice the logic failure of the arithmetic unit C.

  As described above, in the logic function verification of a system LSI using a random test pattern and function coverage, it is possible to reliably detect the presence or absence of a function that is missing the setting of the function coverage item. It is possible to detect a test pattern as a condition for operating.

  The preferred embodiments of the present invention and specific examples thereof have been described above in detail. However, the technical scope of the present invention is not limited to the above descriptions, and various modifications can be made without departing from the spirit of the present invention. Variations can be made. For example, in the above-described embodiment, an example in which the unexpected operation detection unit 10 is provided separately from the function simulator 6 has been described. However, the function simulator 6 has an unexpected operation detection function equivalent to the unexpected operation detection unit 10. Of course, it may be provided.

  In the above-described embodiments and specific examples thereof, description has been given by taking an example in which a logic circuit is described in RTL. However, other hardware capable of calculating a function coverage and a code coverage by performing a reproduction operation (simulation) with a function simulator. Of course, a hardware description language may be used.

1 is a block diagram illustrating a configuration of a function verification apparatus for a system LSI according to a first embodiment of the present invention. It is a block diagram showing the detailed structure of the function simulator of the function verification apparatus of the system LSI which concerns on the 1st Embodiment of this invention. 5 is a flowchart showing an operation of an unexpected operation detection unit of the system LSI function verification apparatus according to the first embodiment of the present invention. FIG. 3 is a sample circuit diagram for explaining a specific operation of the function verification apparatus for the system LSI according to the first embodiment of the present invention. It is a system block diagram equivalent to the function verification apparatus of the conventional system LSI.

Explanation of symbols

1 Verification item 2 Functional coverage item (functional coverage item)
3 RTL (description)
4 Test Program 5 Function Verification Program 6 Function Simulator 7 Function Coverage Database 8 Code Coverage Database 9, 13 Test Pattern 10 Unexpected Operation Detection Unit 11 Unexpected Operation Test Pattern 12 Test Pattern Generator 14 Logic Circuit Simulator 15 Simulator Execution Code 16 Logic Circuit signal value 17 Code coverage checker 18 Function checker 19 Function coverage checker

Claims (4)

A functional simulator that calculates the coverage rate (functional coverage) of functional coverage items for which correct results have been obtained by a test using a predetermined test program with respect to a functional coverage item assumed in advance for a logic circuit described in a predetermined hardware description language A logic circuit functional verification device comprising:
A code coverage calculation unit for calculating code coverage of a test by the test program;
An unexpected operation detection unit that outputs a test pattern as an unexpected operation test pattern when there is a change in the code coverage and no change in the function coverage during the test,
A functional verification device for a logic circuit. The functional simulator is
A test pattern generator for outputting a random test pattern by the predetermined test program;
A logic circuit simulator that reproduces the logic circuit to be verified;
A function checker for confirming whether the logic circuit is operating correctly by comparing the output result of the function verification program with the output of the logic circuit simulator;
A function coverage checker for detecting a function coverage item corresponding to a test pattern whose normal operation has been confirmed by the function checker;
The function verification apparatus for a logic circuit according to claim 1. A functional simulator that calculates the coverage rate (functional coverage) of functional coverage items for which correct results have been obtained by a test using a predetermined test program with respect to a functional coverage item assumed in advance for a logic circuit described in a predetermined hardware description language A code coverage calculation unit that calculates code coverage of a test by the test program, and a verification method of the functional coverage item using a computer system,
The computer system detecting a change in the code coverage;
The computer system detecting a change in the functional coverage;
The computer system outputs a test pattern generated by the test program when there is a change in the code coverage and no change in the function coverage during a test as an unexpected operation test pattern; Including,
Functional coverage item verification method characterized by A functional simulator that calculates the coverage rate (functional coverage) of functional coverage items for which correct results have been obtained by a test using a predetermined test program with respect to a functional coverage item assumed in advance for a logic circuit described in a predetermined hardware description language A code coverage calculation unit that calculates code coverage of a test by the test program, and a program that is executed by a computer system,
The output results of the function simulator and the code coverage calculation unit are monitored, and the test pattern generated by the test program when the code coverage is changed and the function coverage is not changed is an unexpected operation test pattern. A program that causes a computer system to execute processing to be output as

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