JP2006153531A - Method and apparatus for evaluating test vector of semiconductor integrated circuit and method and apparatus for verifying same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that it has been difficult to determine whether test vectors are as sufficient as they need to be or not in a method for verifying semiconductor integrated circuits for performing function simulation through the use of test vectors. <P>SOLUTION: Logical behaviors of semiconductor integrated circuits are simulated through the use of test vectors, and part or all input signals, output signals, and time-series variations A of internal state of the semiconductor integrated circuits during simulation are stored. A single or plurality of extraction time-series variations B in which desired waveform have occurred are extracted from the time-series variations A. When the extraction time-series variations B are plural, they are compressed into a smaller number of compression time-series variations C than the number of the extraction time-series variations B. Detection time-series variations D in which waveforms not included in the extraction time-series variations B occur are detected through the use of the compression time-series variations C. It is possible to automatically determine the time-series variations D not verified by test vectors and eliminate verification omissions. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a test vector evaluation method and verification method for a semiconductor integrated circuit, and a test vector evaluation apparatus and verification apparatus for a semiconductor integrated circuit.

  Conventionally, as a method for verifying a semiconductor integrated circuit, a method of performing a function simulation of a target semiconductor integrated circuit using a test vector (test pattern) and determining a result is used.

  Further, a method for improving the function simulation is described in, for example, Patent Document 1. Once the function simulation is performed, the state change of the semiconductor integrated circuit is stored, and the input signal of the semiconductor integrated circuit is changed variously with the state of the stored semiconductor integrated circuit as the initial state. There is a method of generating a state different from the state and improving the efficiency of the function simulation.

Another verification method is described in Non-Patent Document 1, for example. A formal function verification method is used in which the function of a semiconductor integrated circuit is described by a mathematical proposition, the mathematical proposition is compared with the semiconductor integrated circuit, and whether or not they match.
US Pat. No. 6,292,765 Masahiro Fujita, “Introduction to System LSI Verification Technology 1st Significance of Formal Verification”, Design Wave Magazine, June 2003, page 110

  However, in the semiconductor integrated circuit verification method in which the function simulation of the semiconductor integrated circuit is performed using the test vector, it is difficult to determine whether all conditions for generating a desired waveform have been verified. As a result, a verification failure has occurred. In addition, it is difficult to determine whether the desired waveform generation factor matches the specifications of the semiconductor integrated circuit. In addition, the scale of a semiconductor integrated circuit has been increasing year by year to increase its functionality. Also, it is not possible to find a defect that does not propagate outside the semiconductor integrated circuit.

  The configuration of Patent Document 1 is one method for solving this problem. As means for searching for an unverified state, the state of the stored semiconductor integrated circuit is set as an initial state, and various input signals of the semiconductor integrated circuit are used. Therefore, there are cases where not all states can be searched, and this is not necessarily a sufficient verification.

  In the configuration of Non-Patent Document 1, although it is possible to verify the mathematical proposition described without omission, there is no method for verifying whether the mathematical proposition is sufficient, and all functions are verified. Therefore, there are cases where the mathematical propositions necessary for this cannot be described, and it cannot be said that the verification is sufficient.

  The present invention solves the above-mentioned conventional problems, and automatically generates mathematical propositions from the results of functional simulation and verifies that they are covered using formal functional verification. It is an object to provide a method, a semiconductor integrated circuit verification method based on the test vector evaluation method, a semiconductor integrated circuit test vector evaluation device, and a semiconductor integrated circuit verification device based on the test vector evaluation method.

In order to achieve this object, a test vector evaluation method for a first semiconductor integrated circuit according to the present invention includes:
A state storage step of simulating the logical behavior of the semiconductor integrated circuit using a test vector, and storing a time series change of a part or all of the input signal and output signal of the semiconductor integrated circuit and the internal state during the simulation;
An extraction step of extracting one or more extraction time series changes in which a desired waveform is generated from the time series changes;
And an organizing step for collecting the compressed time series changes into a smaller number of compressed time series changes than the extracted time series changes.

A test vector evaluation apparatus corresponding to the test vector evaluation method for the first semiconductor integrated circuit,
A state storage means for simulating the logical behavior of the semiconductor integrated circuit using a test vector, and storing time series changes of a part or all of the input signal and output signal of the semiconductor integrated circuit and the internal state during the simulation;
Extraction means for extracting one or a plurality of extracted time series changes in which a desired waveform is generated from the time series changes;
When there are a plurality of extracted time-series changes, there are provided organizing means for grouping into a smaller number of compressed time-series changes than the extracted time-series changes.

The second semiconductor integrated circuit test vector evaluation method of the present invention is the first semiconductor integrated circuit test vector evaluation method,
The organizing step extracts a state of don't care that is not necessarily required to generate the desired waveform from the plurality of extracted time series changes, and collects the compressed time series changes to a smaller number than the extracted time series changes.

A test vector evaluation method for a third semiconductor integrated circuit according to the present invention is the test vector evaluation method for a first semiconductor integrated circuit.
The organizing step generates a first mathematical proposition which is a mathematical proposition when the desired waveform is generated from the single extracted time series change, and deletes a signal condition from the first mathematical proposition Generating a second mathematical proposition, and determining whether the first mathematical proposition and the second mathematical proposition are the same for the semiconductor integrated circuit using formal functional verification The state of the don't care is extracted by the above, and the compressed time series change is smaller than the extracted time series change.

  Since the first, second, and third test vector evaluation methods can confirm the state of the semiconductor integrated circuit that generates the desired waveform generated by the test vector in a state of being gathered in a compressed time series change, It is possible to easily determine whether or not the waveform change is sufficient to generate the waveform. Also, the don't care condition that appears in the compression time series change means that it is a logically unnecessary signal for generating the target waveform, and if it is determined that don't care in all the waveforms to be extracted, Since it is determined that the logic is unnecessary on the circuit, unnecessary logic in the semiconductor integrated circuit can be extracted.

  Next, in the first semiconductor integrated circuit verification method of the present invention, in addition to the test vector evaluation method of the first semiconductor integrated circuit, the compressed time series change represents all waveforms that should generate a desired waveform. It is characterized by including a test vector adding step for generating a leaked test vector when not.

  In addition to the test vector evaluation apparatus for the semiconductor integrated circuit, the first verification apparatus corresponding to the first semiconductor integrated circuit verification method generates all waveforms for which the compression time-series change should generate a desired waveform. When not shown, a test vector adding means for generating a leaked test vector is provided.

  According to a second method for verifying a semiconductor integrated circuit of the present invention, in addition to the test vector evaluation method for the first semiconductor integrated circuit, a waveform expressed by the compression time-series change is other than the specification of the semiconductor integrated circuit. When included, it includes a detection step of detecting as a defect of the semiconductor integrated circuit.

  In addition to the test vector evaluation device for the semiconductor integrated circuit, the second verification device corresponding to the second semiconductor integrated circuit verification method has a waveform expressed by the compressed time-series change in the specifications of the semiconductor integrated circuit. When a device other than the above is included, a detection means for detecting a failure pattern is provided.

  By the first and second verification methods, a combination of states including an internal state that generates a desired waveform is simply expressed, so that a difference from the specification can be easily found. In addition, since the compressed time series change includes the internal state of the semiconductor integrated circuit, it is possible to find a defect even when the defect does not propagate outside the semiconductor integrated circuit.

In addition to the first semiconductor integrated circuit test vector evaluation method, the third semiconductor integrated circuit verification method of the present invention includes:
A detection step of detecting, using the compressed time series change, a detection time series change in which the desired waveform not included in the extracted time series change is generated;
A test vector adding step for describing a test vector for reproducing the detected time series change when the detected time series change is detected.

In addition to the test vector evaluation apparatus for the semiconductor integrated circuit, a third verification apparatus corresponding to the third semiconductor integrated circuit verification method includes:
Detecting means for detecting, using the compressed time series change, a detection time series change in which the desired waveform not included in the extracted time series change is generated;
Test vector adding means for describing a test vector for reproducing the detected time series change when the detected time series change is detected.

  According to a fourth semiconductor integrated circuit verification method of the present invention, in the first to third semiconductor integrated circuit verification methods, the organizing step is not necessarily performed because the desired waveform is generated from the plurality of extracted time series changes. It is characterized in that unnecessary don't care states are extracted and combined into a smaller number of compressed time series changes than the extracted time series changes.

  According to a fifth semiconductor integrated circuit verification method of the present invention, in the first to third semiconductor integrated circuit verification methods, the organizing step is performed when the desired waveform is generated from the single extracted time series change. Generating a first mathematical proposition which is a mathematical proposition, and generating a second mathematical proposition in which a signal condition is deleted from the first mathematical proposition, and the first mathematical proposition and the first The state of the two mathematical propositions is the same as that for the semiconductor integrated circuit, and the state of the don't care is extracted by determining using formal function verification, so that the compressed time series change is smaller than the extracted time series change. It is characterized by grouping.

  According to a sixth semiconductor integrated circuit verification method of the present invention, in the third semiconductor integrated circuit verification method, the detection step includes a third mathematical proposition in which conditions and results of the second mathematical proposition are interchanged. And determining the detected time series change by using formal function verification to determine whether the third mathematical proposition correctly represents a part of the function of the semiconductor integrated circuit. Yes.

  According to the third, fourth, fifth, and sixth verification methods, it is possible to automatically obtain a detection time series change that is not verified by the test vector, thereby preventing a verification failure.

  According to the present invention, the state of the semiconductor integrated circuit that generates the desired waveform generated by the test vector can be confirmed in a state of being gathered in a compression time series change. You can easily judge whether changes are sufficient.

  In addition, the don't care condition that appears in the compression time series change means that it is a logically unnecessary signal for generating the target waveform, and if it is determined that don't care in all the waveforms to be extracted, Since it is determined that the logic is unnecessary on the circuit, unnecessary logic in the semiconductor integrated circuit can be extracted.

  In addition, by simply expressing a combination of states including an internal state that generates a desired waveform, it is possible to easily find a difference from the specification.

  In addition, since the compressed time-series change includes the internal state of the semiconductor integrated circuit, it is possible to find a defect even when the defect does not propagate outside the semiconductor integrated circuit.

  In addition, it is possible to automatically obtain a detection time series change that is not verified by the test vector, thereby preventing a verification failure.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
FIG. 1 is a flowchart showing processing of a test vector evaluation method for a semiconductor integrated circuit according to the first embodiment of the present invention. 1 is a computer device, 2 is a test vector, 3 is a circuit description of the semiconductor integrated circuit, and S1 is a first , S2 is the second step, S3 is the third step, and S4 is the fourth step. The test vector 2 and the circuit description 3 of the semiconductor integrated circuit are stored in a hard disk external to the computer apparatus 1 and are taken into the computer apparatus 1 via an interface. The computer apparatus 1 executes the processes of the first to third steps S1 to S3 using the internal CPU, and outputs it again to the hard disk as a compression time series change. The verifier can evaluate the coverage of the test vector more easily than before by checking the compressed time-series change captured in the hard disk. Further, in the present embodiment, the compressed time-series change is input to another computer apparatus, and the fourth step S4 is processed using the CPU of the other computer apparatus, thereby generating an unverified test vector. Is also possible. The computer apparatus that processes the fourth step S4 may be the same as the computer apparatus 1 that processes the first to third processes S1 to S3.

  Hereinafter, the first to fourth steps S1 to S4 will be described more specifically.

  In the first step S1, a simulation is executed, and the time series change of all or part of the simulation is performed for a part or all of the input signal, output signal, and internal state of the target semiconductor integrated circuit. Save as A.

  In the second step S2, a partial time series is defined for a signal selected from the input signal, the output signal, and the internal state recorded in the time series change A, and matches the defined partial time series. A partial time series is extracted from the time series change A and is set as an extracted time series change B. The extraction time series change B includes signals other than the signal selected for extraction.

  In the third step S3, a plurality of extracted time series changes B are merged by judging the significance of each signal from the extracted time series changes B, and a compressed time series change C is generated.

  In the fourth step S4, an untested pattern is detected using the compressed time series change C obtained in the third step S3, and an additional pattern is generated.

  The test vector evaluation method for the semiconductor integrated circuit of the present embodiment configured as described above will be described below in the case where the circuit description 3 of the semiconductor integrated circuit is a timer circuit and the test vector 2 is a test vector of the timer circuit. .

  FIG. 2 is a functional block diagram of the timer circuit, in which 21 is a timer, 22 is a first mode register (exe) that permits a count operation by writing a signal “1”, and 23 is written with a signal “1”. Accordingly, the second mode register (cas) that permits the cascade operation, 24 is a reset signal (rst) that initializes the entire timer 21, 25 is a cascade input signal (cin), and 26 is a reference for the operation of the entire timer. A clock (clk), 27 is a 4-bit binary counter, 28 is an interrupt output, 29 is an IO bus accessible to the first mode register (exe) 22 and the second mode register (cas) 23. The timer 21 is stored as a circuit description in a hard disk external to the computer apparatus 1.

  The function of the timer 21 will be described. In the counting operation, when the first mode register (exe) 22 is set to “1” and the second mode register (cas) 23 is set to “0”, the binary counter 27 counts up in synchronization with the clock 26. Immediately after the value of the binary counter 27 changes from “15” to “0”, the interrupt output 28 outputs “1” for one cycle period. The interrupt output 28 is output only when the binary counter 27 is in operation, that is, when the first mode register (exe) 22 is “1”. The cascade operation is when the first mode register (exe) 22 is “1” and the second mode register (cas) 23 is “1”, and the binary counter is only when the cascade input signal 25 is “1”. 27 performs an up-count operation.

  FIG. 3 shows an example of the time series change A of the timer 21. In FIG. 3, Time represents the simulation time, rst represents the reset signal 24, cin represents the cascade input signal 25, cas represents the second mode register (cas) 23, and exe represents the first mode register ( exe) 22, BC represents the binary counter 27, and irq represents the interrupt output 28. The period of the clock 26 is Time10. In FIG. 3, the operation of the clock 26 is omitted. The test vectors that are input signals are rst, cin, cas, and exe, the time series change of the internal state obtained by the simulation is BC, and the time series change of the output signal is irq. The time series change A of the timer 21 is a first that stores the time series change of the input signal and output signal of the timer 21 and the internal state by performing a simulation by inputting the test vector and the circuit description of the timer 21 to the computer apparatus 1. It is obtained in step S1 and stored in a hard disk external to the computer device 1.

  The time series change A in the case of the timer 21 will be described in detail. The timer 21 is initialized by setting rst to “1” at Time 0. At time 20, exe is set to “1” and the timer 21 starts counting. From Time 30 to Time 410 where exe is set to “0”, the BC performs an up-count operation for each Time 10 one by one. irq becomes “1” in the next cycle when BC becomes “15”. In time 410, cin and exe are set to “0”, and in time 420, cas and exe are set to “1”. For this reason, BC is incremented by 1 at Time 460 which is the next cycle of Time 450 when cin becomes “1” (“7” → “8”).

  FIG. 4 shows a result of extracting the extracted time series change group B in which the desired waveform related to the timer 21 is generated from the time series change A in the second step S2. Here, the desired waveform is set from one cycle before irq becomes “1” until irq becomes “1”. Two types of Time 170 and Time 180, and Time 330 and Time 340 are extracted.

  FIG. 5 shows the result of the extraction time series change B combined into the compression time series change C in the third step S3.

  Here, a method of combining the extracted time series changes B into a smaller number of compressed time series changes C will be specifically described. It generates a first mathematical proposition which is a mathematical proposition when a desired waveform is generated from the extracted time series change B1 and the extracted time series change B2. Further, a second mathematical proposition in which the signal condition is deleted from the first mathematical proposition is generated. Then, the state of the don't care is extracted by determining whether the first mathematical proposition and the second mathematical proposition are the same for the timer 21 using formal function verification. As a result, the extracted time series changes B are combined into a smaller number of compressed time series changes C.

  The case where irq becomes “1” from the extracted time series change B1 is converted into a mathematical proposition. Specifically, “rst is“ 0 ”, cin is“ 0 ”, cas is“ 0 ”, exe is“ 1 ”, BC is“ 15 ”and irq is“ 0 ”, and the next cycle If rst is “0”, cin is “0”, cas is “0”, exe is “1”, and BC is “0”, irq is “1” in the next cycle ”. Describe the mathematical proposition.

  Next, a formal function verification is performed by removing one signal condition of the first mathematical proposition. For example, the first signal condition “rst is“ 0 ”and” is removed from the first mathematical proposition, “cin is“ 0 ”, cas is“ 0 ”, exe is“ 1 ”, and BC is If “15” and irq are “0”, and rst is “0”, cin is “0”, cas is “0”, exe is “1”, and BC is “0” in the next cycle For example, in the next cycle, the second mathematical proposition “irq is“ 1 ”” is generated. Next, a formal function verification of the second mathematical proposition and timer 21 is performed. If it is determined to be equivalent, since “rst is“ 0 ”and” is a condition for don't care, it is deleted from the first mathematical proposition. Actually, it is determined as inequality, and “rst is“ 0 ”and” is not a condition of don't care, and cannot be deleted from the first mathematical proposition.

  When this operation is repeated and the don't care condition is deleted, from the extracted time series change B1 and extracted time series change B2 shown in FIG. 4, “rst is“ 0 ”, cas is“ 0 ”, and exe is“ 1 ””. If BC is “15” and rst is “0” in the next cycle, the second mathematical proposition “irq is“ 1 ”in the next cycle” is generated. The compressed time series change C1 shown in FIG. 5 can be obtained by expressing the second mathematical proposition combined into one waveform.

  Next, in the fourth step S4, it is determined whether or not the compression time series change C generates all the desired waveforms. If not, an unverified test vector that generates the desired waveform is described. The process proceeds to step S1. Specifically, a signal value that is not determined as don't care (“x”) is left as a logical value “0” or “1” in the compression time series change C in the third step S3. A signal in which only one of the values appears or a combination of all the logical values in a specific signal combination in which a combination other than those that cannot be logically generated does not appear is detected.

  In the example of the timer 21, the first mode register (exe) 22 is “1”, the second mode register (cas) 23 is “1”, the reset signal 24 is “0”, and the cascade input signal 25 is It is assumed that a test vector in which the binary counter 27 is “15”, the clock 26 is input, and the interrupt output 28 is “1” in the next clock cycle is added to the time-series change A (see FIG. 4 C2). In this case, the compression time series change C is obtained as the compression time series change C1 and the compression time series change C2. Comparing the compression time-series change C1 and the compression time-series change C2, in both cases, when Time is n, exe is “1” and BC is “15”. This is a signal in which only one of the logical values in the timer 21 appears, and it is determined whether or not exe is “0” or BC is not “15”.

  As described above, according to the present embodiment, the number of signal lines to be determined is determined by collecting the extracted time series change B in which a desired waveform is generated into the compressed time series change C by extracting the don't care conditions. Therefore, it is easier to determine whether or not the extracted time series change B is sufficient when a desired waveform is generated as compared with the conventional case.

  In addition, a combination of states including an internal state that generates a desired waveform is simply expressed by the compression time series change C, so that a difference from the specification can be easily found.

  In addition, a combination of states including an internal state that generates a desired waveform is simply expressed by the compression time series change C, so that a difference from the specification can be easily found.

  In addition, the don't care condition that appears in the compressed time series change C generated by the present embodiment means that the signal is logically unnecessary for generating the target waveform, and the don't care in all the waveforms to be extracted. If it is determined, it is determined that the logic is unnecessary on the circuit. As described above, according to the present embodiment, it is possible to extract unnecessary logic in the semiconductor integrated circuit.

  In the present embodiment, the condition of don't care is extracted using formal function verification in the fourth step S4. However, the formal function verification is not used and the signals other than the target signal are exactly the same from the extracted time series change B. It is also possible to extract the don't care conditions by selecting one, examining the logic of the target signal, and confirming that all logic has occurred. In this embodiment, the conditions are determined one by one by formal function verification. However, it is also possible to delete a plurality of conditions at once, and it is possible to extract the don't care conditions based on the determination result. It is.

  Further, when there is a signal that can be determined to be clearly unrelated to the signal selected for extraction at the time of extraction of the extraction time series change B, it is possible to extract the third signal by excluding that signal. This step S3 can be simplified.

(Embodiment 2)
FIG. 6 is a flowchart showing the process of the semiconductor integrated circuit verification method according to the second embodiment of the present invention. S1, S2 and S3 are the same as those in the first embodiment, and S5 is the fifth step. In the fifth step S5, it is determined whether the logic of the unselected signal matches the specification of the semiconductor integrated circuit with respect to the change in the signal selected in the second step S2, using the compressed time series change C. If they do not match, it is detected as a defective part of the semiconductor integrated circuit and necessary corrections are made. Alternatively, it is determined whether the signal determined to be don't care in the compression time-series change C is also don't care in the specification. If there is a problem in the circuit description of the semiconductor integrated circuit, the circuit description is corrected. Then, it progresses to 1st process S1.

  It is assumed that there is a defect in the circuit description of the timer 21 and the compressed time series change C3 shown in FIG. 5 is obtained. Even if exe is don't care “x”, the interrupt output 28 is “1”. From the specification, it can be seen that the interrupt output 28 cannot be “1” unless the timer 21 is in operation (exe is “1”), so that the circuit description of the timer 21 is defective.

  As described above, according to the present embodiment, by extracting the don't care conditions from the extracted time series change B in which the desired waveform is generated, the minimum necessary state in which the desired waveform including the internal state of the semiconductor integrated circuit is generated. Are summarized as a compression time series change C. Therefore, in a plurality of cases where a desired waveform is generated, it can be determined with a small number of states whether or not they match the specifications. Furthermore, since this verification method can be applied to an internal signal, it is possible to easily find a defect that does not propagate outside the semiconductor integrated circuit.

(Embodiment 3)
FIG. 7 is a flowchart showing the process of the semiconductor integrated circuit verification method according to the third embodiment of the present invention. S1, S2, and S3 are the same as those in the first embodiment, S6 is the sixth step, and S7 is the first step. 7 steps. In the sixth step S6, a waveform to be extracted that is not included in the extracted time series change B is generated using the waveform that extracts the compression time series change C and the extraction time series change B obtained in the third step S3. A detection time series change D is detected. In the seventh step S7, a test vector for generating the detection time series change D detected in the sixth step S6 is generated. A method for verifying the semiconductor integrated circuit of the present embodiment configured as described above will be described below using a timer circuit and its test vector.

  FIG. 8 shows the detected time series change D detected in the sixth step S6 using the timer 21 and its compressed time series change C.

  Here, a third mathematical proposition in which the condition and result of the second mathematical proposition are exchanged is generated, and a formal representation is made as to whether the third mathematical proposition correctly represents a part of the function of the semiconductor integrated circuit. A method of obtaining the detection time series change D by making a determination using functional verification will be specifically described. Replacing the condition and result of the second mathematical proposition, “If irq is“ 1 ”in the next cycle, rst is“ 0 ”, cas is“ 0 ”, exe is“ 1 ”, BC is“ 15 ”and In the next cycle, a third mathematical proposition “rst is“ 0 ”” (see C1 in FIG. 5) is generated. When formal function verification is performed using the third mathematical proposition, if there is another case in which irq is “1”, they are inconsistent and can be detected. In the example of the timer 21, a detection time series change D is detected. This indicates that the verification that the interrupt output is output correctly in the cascade mode is missing.

  Next, if the detected time series change D is detected in the seventh step S7, a test vector for reproducing the detected time series change D is described, and the process proceeds to the first step S1.

  As described above, according to the present embodiment, it is possible to automatically generate a mathematical proposition for finding a detected time-series change D that has not been verified by a test vector, thereby preventing a functional verification from leaking a desired waveform. It becomes possible.

  The method for evaluating a test vector of a semiconductor integrated circuit according to the present invention is useful as a method for determining whether a test vector used for verification of a semiconductor integrated circuit is necessary or sufficient.

  The semiconductor integrated circuit verification method of the present invention using the test vector evaluation method is useful as a method for efficiently verifying the semiconductor integrated circuit.

  In addition, this test vector evaluation method is effective in reducing test vectors and is effective in reducing verification time. Similarly, it can be used to reduce test vectors during LSI evaluation using a tester.

  In addition, since this test vector evaluation method extracts don't care conditions, it can detect a portion that may be a redundant circuit on the circuit, and can also be used to detect an unnecessary circuit.

7 is a flowchart showing processing of a test vector evaluation method for a semiconductor integrated circuit according to the first embodiment of the present invention. Functional block diagram of a timer circuit in the first embodiment FIG. 4 is a diagram illustrating an example of a time-series change of a timer in the first embodiment. FIG. 7 is a diagram of an extracted time series change group in which a desired waveform related to the timer in the first embodiment is generated. The figure of the result put together in the compression time series change in Embodiment 1 7 is a flowchart showing processing of a test vector verification method for a semiconductor integrated circuit according to the second embodiment of the present invention. The flowchart which shows the process of the test vector verification method of the semiconductor integrated circuit in Embodiment 3 of this invention FIG. 7 is a diagram of detection time-series change in the third embodiment

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Computer apparatus 2 Test vector 3 Circuit description of semiconductor integrated circuit A Time series change B1, B2 Extraction time series change C1, C2, C3 Compression time series change D Detection time series change

Claims (13)

A state storage step of simulating the logical behavior of the semiconductor integrated circuit using a test vector, and storing time series changes of the input signal and output signal of the semiconductor integrated circuit and the internal state during the simulation;
An extraction step of extracting one or more extraction time series changes in which a desired waveform is generated from the time series changes;
A test vector evaluation method for a semiconductor integrated circuit, comprising: a step of arranging a plurality of extracted time series changes into a smaller number of compressed time series changes than the extracted time series changes.   2. The organizing step extracts a state of don't care that is not necessarily required to generate the desired waveform from the plurality of extracted time series changes, and summarizes the compressed time series changes to a smaller number than the extracted time series changes. The test vector evaluation method of the semiconductor integrated circuit as described.   The organizing step generates a first mathematical proposition which is a mathematical proposition when the desired waveform is generated from the single extracted time series change, and deletes a signal condition from the first mathematical proposition Generating a second mathematical proposition, and determining whether the first mathematical proposition and the second mathematical proposition are the same for the semiconductor integrated circuit using formal functional verification 2. The test vector evaluation method for a semiconductor integrated circuit according to claim 1, wherein states of don't cares are extracted by the above and are combined into a smaller number of compressed time series changes than the extracted time series changes. A state storage step of simulating the logical behavior of the semiconductor integrated circuit using a test vector, and storing time series changes of the input signal and output signal of the semiconductor integrated circuit and the internal state during the simulation;
An extraction step of extracting one or more extraction time series changes in which a desired waveform is generated from the time series changes;
When there are a plurality of the extracted time series changes, an organizing step for collecting the compressed time series changes into a smaller number of compressed time series changes;
A test method for a semiconductor integrated circuit, comprising: a test vector adding step of generating a test vector that leaks when the compressed time series change does not represent all the waveforms that should generate a desired waveform. A state storage step of simulating the logical behavior of the semiconductor integrated circuit using a test vector, and storing time series changes of the input signal and output signal of the semiconductor integrated circuit and the internal state during the simulation;
An extraction step of extracting one or more extraction time series changes in which a desired waveform is generated from the time series changes;
When there are a plurality of the extracted time series changes, an organizing step for collecting the compressed time series changes into a smaller number of compressed time series changes;
A method for verifying a semiconductor integrated circuit, comprising: a step of detecting as a defect of the semiconductor integrated circuit when the waveform expressed by the compressed time series change includes a waveform other than the specification of the semiconductor integrated circuit. A state storage step of simulating the logical behavior of the semiconductor integrated circuit using a test vector, and storing time series changes of the input signal and output signal of the semiconductor integrated circuit and the internal state during the simulation;
An extraction step of extracting one or more extraction time series changes in which a desired waveform is generated from the time series changes;
When there are a plurality of the extracted time series changes, an organizing step for collecting the compressed time series changes into a smaller number of compressed time series changes;
A detection step of detecting, using the compressed time series change, a detection time series change in which the desired waveform not included in the extracted time series change is generated;
And a test vector adding step for describing a test vector for reproducing the detected time series change when the detected time series change is detected.   5. The organizing step extracts a state of don't care that is not necessarily required for generating the desired waveform from the plurality of extracted time series changes, and summarizes the compressed time series changes to a smaller number than the extracted time series changes. The method for verifying a semiconductor integrated circuit according to claim 6.   The organizing step generates a first mathematical proposition which is a mathematical proposition when the desired waveform is generated from the single extracted time series change, and deletes a signal condition from the first mathematical proposition Generating a second mathematical proposition, and determining whether the first mathematical proposition and the second mathematical proposition are the same for the semiconductor integrated circuit using formal functional verification 7. The method for verifying a semiconductor integrated circuit according to claim 4, wherein states of don't cares are extracted by the above and are collected into a smaller number of compressed time series changes than the extracted time series changes.   The detecting step generates a third mathematical proposition in which conditions and results of the second mathematical proposition are exchanged, and the third mathematical proposition correctly represents a part of the function of the semiconductor integrated circuit. The semiconductor integrated circuit verification method according to claim 6, wherein the detection time-series change is obtained by determining whether the detection time series changes using formal function verification. State storage means for simulating the logical behavior of the semiconductor integrated circuit using a test vector, and for storing time series changes in the input signal and output signal of the semiconductor integrated circuit and the internal state during the simulation;
Extraction means for extracting one or a plurality of extracted time series changes in which a desired waveform is generated from the time series changes;
An apparatus for evaluating a test vector of a semiconductor integrated circuit, comprising: an organizing unit that summarizes into a smaller number of compressed time series changes than the extracted time series changes when there are a plurality of extracted time series changes. State storage means for simulating the logical behavior of the semiconductor integrated circuit using a test vector, and for storing time series changes in the input signal and output signal of the semiconductor integrated circuit and the internal state during the simulation;
Extraction means for extracting one or a plurality of extracted time series changes in which a desired waveform is generated from the time series changes;
When there are a plurality of extracted time series changes, organizing means for collecting the compressed time series changes into a smaller number of compressed time series changes;
A verification apparatus for a semiconductor integrated circuit, comprising: test vector adding means for generating a test vector that is leaked when the compressed time series change does not represent all waveforms that should generate a desired waveform. State storage means for simulating the logical behavior of the semiconductor integrated circuit using a test vector, and for storing time series changes in the input signal and output signal of the semiconductor integrated circuit and the internal state during the simulation;
Extraction means for extracting one or a plurality of extracted time series changes in which a desired waveform is generated from the time series changes;
When there are a plurality of extracted time series changes, organizing means for collecting the compressed time series changes into a smaller number of compressed time series changes;
A verification apparatus for a semiconductor integrated circuit, comprising: detection means for detecting a failure pattern when a waveform expressed by the compressed time-series change includes a waveform other than the specification of the semiconductor integrated circuit. State storage means for simulating the logical behavior of the semiconductor integrated circuit using a test vector, and for storing time series changes in the input signal and output signal of the semiconductor integrated circuit and the internal state during the simulation;
Extraction means for extracting one or a plurality of extracted time series changes in which a desired waveform is generated from the time series changes;
When there are a plurality of extracted time series changes, organizing means for collecting the compressed time series changes into a smaller number of compressed time series changes;
Detecting means for detecting, using the compressed time series change, a detection time series change in which the desired waveform not included in the extracted time series change is generated;
A verification apparatus for a semiconductor integrated circuit, comprising: test vector adding means for describing a test vector for reproducing the detected time series change when the detected time series change is detected.

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