KR101958540B1 - Apparatus and method of debugging post silicon using on-chip dram for multi-core design - Google Patents

Abstract

The present invention relates to a technique for selectively debugging only data estimated to be an error in post silicon debugging in a multicore environment using an on-chip DRAM, wherein a method of debugging post silicon according to an embodiment includes: The method of claim 1, further comprising the steps of: generating golden data corresponding to the detected error intervals and uploading the generated golden data to a trace buffer to identify error intervals in the debug interval; And selectively debugging the error data corresponding to the error cycle.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a post-silicon debug apparatus and method in a multi-core environment using an on-chip DRAM,

The present invention relates to a technique for debugging post silicon, and a technical idea of selectively debugging only data estimated to be error in post silicon debug in a multicore environment using an on-chip DRAM.

Recently, with the development of semiconductor design and process technology, the amount of error that can not be found in the design stage before the manufacturing process is increasing more and more. Semiconductors such as system on chips (SoCs), which are developed to improve the integration of designs, include a large number of cores in a single chip, which can be handled by hardware debugging to achieve higher semiconductor yields and cost savings. The process of dispatching became necessary.

The biggest limitation in this process is that it is difficult to observe the data inside the chip in real time for debugging. In order to overcome this problem, recently, a DfD (Design for Debug) method has been studied in which chip internal data is stored in real time using a trace buffer and stored data is extracted from an external interface through an external interface such as JTAG (Joint Test Action Group) .

That is, a debug process of the post silicon stage is required to detect errors that may occur after circuit verification and testing, and a Design for Debug (DfD) technique for debugging is proposed to assist the debug process. This is a technique currently proposed for observing data in a semiconductor in real time, and this DfD technique corresponds to an embedded logic analysis technique using a trace buffer.

A unit using this technique determines an observation start point or an end point of an internal circuit state, and when the observation is started, the debug data stores corresponding data in a sample unit including a trace buffer (embedded memory) To the external debug software through an off-load unit, and analyzes the data.

This technique has the advantage of extracting and analyzing data in real time, but the disadvantage is that the number of observable data is limited by the capacity of the trace buffer. In order to overcome this problem, the debug data is actively utilized and observed in the chip, and debugging is performed by comparing and compressing the error section and the error cycle step by step using the compression technique used in the test such as MISR have.

However, since the amount of data that can be stored in real time for observation is directly proportional to the trace buffer size, which is directly related to the hardware overhead cost, this method requires a lot of debugging operations in hardware debug where tens of millions of observation cycles are required. Time. Therefore, a technique for shortening the debug time is needed.

1 is a view for explaining a debug method in a conventional DRAM.

As shown in FIG. 1, in the conventional DRAM method, only one core is considered in one debug session. Therefore, when considering a plurality of cores, a session corresponding to the number of cores is usually required. This increases the total debug time in the current semiconductor technology situation, which is an increasing trend of the number of integrated cores in the chip.

Korean Patent No. 10-1430218 entitled "Debug State Machine and Processor Including It" U.S. Patent No. 10-8990622 entitled "Post-silicon validation using a partial reference model &

An object of the present invention is to provide a technique for selectively debugging only data estimated to be an error in post silicon debugging in a multicore environment using an on-chip DRAM.

The present invention compresses and analyzes an error section selectively using a MISR (Multiple Input Signature Register), stores debug data in a DRAM existing in the chip, and debugs only three debug sessions To reduce the debug time.

The present invention aims at shortening the total debug time, thereby reducing the total chip manufacturing time and reducing the cost for chip production.

The method of debugging post silicon according to an exemplary embodiment includes generating golden data corresponding to a debug section based on a simulation before debug starts and uploading the generated golden data to a trace buffer to identify error intervals in the debug section , Detecting an error cycle corresponding to the identified error intervals, and selectively debugging the error data corresponding to the detected error cycle.

The step of recognizing the error intervals according to an embodiment may include uploading the golden data to the trace buffer, and uploading the golden data through an external interface including Joint Test Action Group (JTAG).

The step of recognizing the error intervals according to an exemplary embodiment may include determining data corresponding to a period that is estimated to be not an error through the simulation as the golden data, performing a MISR (Multiple Input Signature Register) The method includes the steps of: determining whether an error is detected by comparing an interval that is an error in real time with the golden data by using a 1-bit EI tag And recording the data.

The method of debugging post silicon according to an exemplary embodiment may further include the step of recording, using the index (EI index), an interval in which no error occurs as a result of the determination.

The step of determining error intervals in the debug interval according to an exemplary embodiment of the present invention includes dividing and dividing the golden data corresponding to the debug interval into MISR (Multiple Input Signature Register) sizes and dividing the divided and compressed golden data To a DRAM in a chip (DRAM).

The step of selectively debugging the error data corresponding to the detected error cycle according to an exemplary embodiment may include selectively storing error data corresponding to the detected error cycle, And a step of debugging.

The method of debugging post silicon according to an embodiment may further include adding the generated golden data to a DRAM when all the cores within the identified error period are in error.

The step of detecting the error cycle according to an exemplary embodiment of the present invention includes the steps of determining an error cycle for each cycle and storing the error cycle in the form of an EC tag and storing the determined error cycle using a shadow buffer .

The post silicon debug apparatus according to an embodiment generates golden data corresponding to a debug section based on a simulation before the start of debugging and uploads the generated golden data to the trace buffer to identify error sections in the debug section A session 2 processor for detecting an error cycle corresponding to the detected error intervals, and a session 3 processor for selectively debugging the error data corresponding to the detected error cycle.

The session 1 processor according to an exemplary embodiment may include uploading the golden data to the trace buffer, and uploading the golden data through an external interface including Joint Test Action Group (JTAG).

The session 1 processing unit according to an exemplary embodiment determines data corresponding to a section expected to be not an error through the simulation as the golden data and compresses the data through a Multiple Input Signature Register (MISR) It is possible to compare an erroneous section in real time with the golden data and judge whether an error has occurred. As a result of the determination, the erroneous data can be recorded using a 1-bit EI tag.

The session 1 processing unit according to an exemplary embodiment may record an interval in which no error occurs as a result of the determination using an index (EI index).

The session 1 processing unit divides the golden data corresponding to the debug interval into the MISR (Multiple Input Signature Register) size, compresses the divided and compressed golden data into a DRAM Can be stored.

The session 3 processor according to an exemplary embodiment may selectively store error data corresponding to the detected error cycle, and may selectively debug the stored error data.

The session 1 processor according to an exemplary embodiment may add the generated golden data to a DRAM when all the cores in the identified error interval are in error.

The session 2 processor according to an exemplary embodiment may determine an error cycle on a cycle-by-cycle basis, store the error cycle in the form of an EC tag, and store the determined error cycle using a shadow buffer.

According to one embodiment, an on-chip DRAM can be used to provide a technique for selectively debugging only data estimated to be error in post silicon debug in a multicore environment.

According to an exemplary embodiment, an error section is selectively compressed and analyzed using a MISR (Multiple Input Signature Register), and debug data is stored in a DRAM existing in the chip. Thus, only three debug sessions Debug time can be shortened by completing the debug.

According to one embodiment, by shortening the total debug time, it is possible to reduce the total chip manufacture time and at the same time reduce the cost for chip production.

1 is a view for explaining a debug method in a conventional DRAM.
2 is a diagram for explaining a debug method according to an embodiment of the present invention.
3 is a diagram for explaining a method of debugging post silicon using a debug session in three stages.
FIG. 4 is a view for explaining an embodiment of a hardware structure for determining an error interval in debug session 1. FIG.
5 is a view for explaining an embodiment in which debug software analyzes an error section through a corresponding result extracted by a tag bit after execution of debug session 1.
6 is a view for explaining a golden data stream selector for generating golden data in real time in the debug session 2.
7 is a diagram illustrating a hardware structure for determining an error cycle in the debug session 2.
FIG. 8 is a view for explaining an embodiment in which the debug software analyzes the error cycle through a corresponding result extracted by the tag bit after the debug session 2.
9 is a diagram for explaining a hardware structure for capturing an error cycle in the debug session 3;
10 is a timing chart for debug session 1.
11 is a timing diagram for debug session 2.
Fig. 12 is a diagram showing the timing for debug session 3. Fig.
13 is a view for explaining a post silicon debug device according to an embodiment.

It is to be understood that the specific structural or functional descriptions of embodiments of the present invention disclosed herein are presented for the purpose of describing embodiments only in accordance with the concepts of the present invention, May be embodied in various forms and are not limited to the embodiments described herein.

Embodiments in accordance with the concepts of the present invention are capable of various modifications and may take various forms, so that the embodiments are illustrated in the drawings and described in detail herein. However, it is not intended to limit the embodiments according to the concepts of the present invention to the specific disclosure forms, but includes changes, equivalents, or alternatives falling within the spirit and scope of the present invention.

The terms first, second, or the like may be used to describe various elements, but the elements should not be limited by the terms. The terms may be named for the purpose of distinguishing one element from another, for example without departing from the scope of the right according to the concept of the present invention, the first element being referred to as the second element, Similarly, the second component may also be referred to as the first component.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between. Expressions that describe the relationship between components, for example, "between" and "immediately" or "directly adjacent to" should be interpreted as well.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In this specification, the terms "comprises ", or" having ", and the like, are used to specify one or more of the features, numbers, steps, operations, elements, But do not preclude the presence or addition of steps, operations, elements, parts, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the meaning of the context in the relevant art and, unless explicitly defined herein, are to be interpreted as ideal or overly formal Do not.

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. However, the scope of the patent application is not limited or limited by these embodiments. Like reference symbols in the drawings denote like elements.

2 is a diagram for explaining a debug method according to an embodiment of the present invention.

The debug method 200 according to an exemplary embodiment of the present invention may end the entire debug session three times in case of debugging a plurality of cores.

The first debug session (Session 1) proceeds to an error section search session in which an error section of each core can be found. Then, an error section is compared with the golden data in real time, An error cycle search session (session 2) proceeds. Finally, Session 3 can proceed, which can complete the entire debug process with an error data capture session that stores data corresponding to the error cycle of each core.

FIG. 3 is a diagram for explaining a debug method 300 of post silicon using a three-step debug session.

First, the post silicon debug method 300 can determine error intervals in the debug section through the debug session 1 (310).

Specifically, the debug method 300 of post silicon can generate (311) golden MISR signatures. For example, you can create golden MISR signatures by compressing the observation interval by dividing it by the MISR size through the MISR before debugging begins.

In addition, the post silicon debug method 300 may generate the capture results 312 of the region detection and thereby detect (313) error regions.

That is, the post silicon debug method 300 can store the golden data in the in-chip DRAM. At this time, while debugging, the actual debug value and the golden data of each core are compared in real time through the comparator, and when the data values are different from each other, the corresponding debug interval of the corresponding core is regarded as an error, (EI tag).

The method 300 for debugging post silicon according to an exemplary embodiment may determine data corresponding to a section that is predicted to be not an error through simulation by using golden data in order to grasp error intervals.

In addition, during debugging, it is possible to determine whether there is an error by comparing the error section and the golden data in real time by compressing the data through the MISR (Multiple Input Signature Register). On the other hand, as a result of the determination, it is possible to detect error sections by recording the data in which an error occurs by using a 1-bit EI tag.

On the other hand, the post silicon debug method 300 may additionally store the EI index tag bits in the debug session 1. Specifically, the debug method 300 of the post silicon can detect the error intervals using the capture result of the interval detection, and can record the interval in which the error does not occur using the index (EI index). That is, a tag bit called an EI index is additionally stored in order to distinguish a case where data of all cores is not an error in the corresponding interval.

In the first debug session, the error section of core under debug (CUD), which is the core being debugged at all, is detected by MISR-based compression technology. This technique was used to identify the section where an error occurred during post silicon debug.

First, golden MISR signatures can be generated by simulating motion models or using an FPGA prototyping board. To capture debug data in the third session, the length of the MISR can be determined as M cycles.

The pre-calculated golden signature can then be uploaded to the DRAM via a serial external interface (such as JTAG) or a high-speed trace port.

When the debug process is started in step 313, a debug configuration is performed to set a trigger event condition and select debug data. In addition, the golden signature can be loaded into the DRAM's golden signature register, and after the functional operation is started, the debug data of each CUD can be compressed by the MISR set for M cycles equal to the interval of the golden signature.

After M cycles, the signature compares the data in the core to the golden data to detect the section in which the error occurred. If the signature value of the core is the same as the golden data, it can be determined that there is no error in the current section of the core.

Otherwise, the current interval can be expressed as an error interval. One bit is required to check the gap error detection result of all cores.

For example, if the value of one bit is '1', it indicates that one or more cores are erroneous during the interval and if it is '0', all cores can indicate that there is no error in all cores.

In the present specification, the 1 bit can be interpreted as an EI index.

That is, if the EI index is '1', n bits called an EI tag are stored in the EI tag register to check the interval detection result of each core. If the EI index is '0', there is no need to capture the EI tag.

After the capture process, the EI tag can be stored in the DRAM before the next interval sensing process is finished. The next golden signature is then loaded and the debug data can be analyzed for N cycles in this manner.

At the end of the first session (debug session 1, 310), the EI tag of the DRAM and the EI index of the register are transmitted to the workstation, that is, off-chip, A tag bit can be generated.

The error section can be selectively distinguished during the observation period through the tag bit storage method. The hardware structure for this is described in detail later in FIG.

Next, the debug method 300 of the post silicon can detect an error cycle corresponding to the error intervals detected through the debug session 2.

The off-chip debug process 321, 323 may be performed by the debug software after sending a tag bit to the workstation (off-chip) indicating that an error interval has been detected.

The process of using the debug software is not burdened with respect to the debug time because the on-chip debug experiment and the debug data are simultaneously executed during the process of being transferred from the debug by debug.

An EI index and an EI tag can be used to generate an error interval matrix representing the error interval information of each core. When n is 4 and the number of EI indexes is 10, the matrix size is 4 x 10 as described in Fig.

To detect the error clock cycles of all CUDs during the second debug session (debug session 2, 320), golden data is needed to analyze the debug data corresponding to each clock cycle.

However, as N or L increases, it is inefficient to store all the golden data in the DRAM.

For this purpose, the off-chip can generate a golden data stream (GDS) during N cycles through step 321. [ That is, the generated GDS can be used to compare golden data with data from cores of the same size.

In addition, the post silicon debug method 300 can selectively debug error data corresponding to the detected error cycle.

The second session (debug session 2, 320) is a session in which the error is directly detected in a certain cycle using the information that has determined the error interval.

In debug session 2 320, cycle-by-cycle golden data is required to analyze error data on a cycle-by-cycle basis, which causes a lot of data overhead. Therefore, a hardware structure called a Golden Data Stream Selector may be added in the present invention in order to reduce this. In the debug session 1 310, since core data in an interval other than the identified error can be assumed to be golden data, the value of the corresponding core can be used as golden data in real time without adding additional golden data. Therefore, it is possible to generate golden data using these conditions. If all the cores are in error in the corresponding interval, then add the golden data to the DRAM.

A block diagram of a golden data stream selector for performing this function is shown in FIG. In this manner, in the debug session 2, the error cycle is discriminated in comparison with the error period in cycles, and the tag bit is generated (323) and stored (322). Since the difference between DRAM speed and chip speed can be different when the DRAM is stored in a cycle unit, it is possible to solve this speed problem by using a shadow buffer in the case of a buffer storing an EC tag bit.

Also, in the debug session 2 320, the trace buffer to be used in the debug session 3 330 can be used to store the golden data.

The golden data stored at this time can be interpreted as the golden data required when all the cores in the corresponding section are in error as mentioned above.

At debug session 3 330, error cycle tag bits are generated (331), error data is captured (332), and debug data (333) is captured.

Specifically, after transmitting the EC tag to the debug software (off-chip), it may be regenerated to detect error data of all cores in a series of clock cycles during debug session 3 330. [

This will be described in more detail with reference to FIG.

FIG. 4 is a diagram illustrating an embodiment of a hardware architecture 400 for determining an error interval in debug session 1.

By using the tag bit storage method, an error section can be selectively distinguished during a corresponding observation period. The hardware structure 400 for this is described in detail in FIG.

As shown in reference numeral 400, after storing the entire section of the data as the EI tag and the EI index, the tag bit is extracted through the debug software connected to the outside, and the comparator 430 detects through the error section Can be distinguished.

For example, when the EI index 440 is 0, all of the cores 410 are error-free in the corresponding interval, and when the EI index 440 is 1, This means that an error has occurred. In the hardware structure 400, it is possible to determine which section the error section is in this way.

More specifically, the matrix of error cycles can be computed as a matrix of EC tags and error intervals. If the length of each MISR in the entire MISR 420 is 5, a 4x5 error period matrix may be generated for each section. If this matrix is used, an EC index can be generated.

The EC index indicates whether there is an error in at least one of the cores 410 in the corresponding clock cycle. First, if the EI index 440 is 0, the interval is ignored, and if the EI index 440 is 1, the required number of EC indexes is M.

If the EC index is 1, an EC tag is required by n and can be regenerated by the error clock matrix, and if the EC index is 0, the cycle can be ignored and the EC tag can be regenerated.

After this tag bit is generated, the final debug session can be performed. The precomputed tag bits can be uploaded to the DRAM and the debug configuration can be performed.

After the trigger point, the EI index 440 detects the error interval, the EC index detects the error period, and the EC tag selects the error core in real time.

The error data of all the cores can be captured in the trace buffer. When the trace buffer is full, the captured data can be moved to the shadow buffer through the EI tag 450 and stored in the DRAM. The next tag bit can then be loaded into the Golden Signatures register 460 in the DRAM and all error data can be stored in the DRAM after the debug is executed. Once the debug session is complete, the stored data is transferred to the workstation and analyzed to find the root cause of the error.

FIG. 5 is a view for explaining an embodiment 500 in which the debug software analyzes an error section through a corresponding result extracted by a tag bit after execution of the debug session 1.

In the example of FIG. 5, according to the present invention, intervals 1, 3, 4, 7 and 8 can select cores as golden data. In this case, core 4 (core_sel = 11) is for intervals 1 and 3 and core 3 (core_sel = 10) for intervals 4, 7 and 8. In the case of error interval matrix 540, it may be identified as result tag bits 520 for session one.

According to the GDS tag bits 530 for session 2, it is possible to start the second debug session after generating the GDS tag to capture the error clock cycle information of each core. First, if the previously calculated tag bit is uploaded to the DRAM, if the GDS index is 1, additional golden data is uploaded and further use of the DRAM is required. However, this case rarely occurs because the error rate of the post silicon debug process discussed above is low.

When the debug process is started, a debug configuration is performed and tag bits are uploaded to each tag register. Also, in the case of added golden data, they can be uploaded to the trace buffers and shadow buffers in turn, since they must be compared to the debug data in consecutive clock cycle order.

This buffer can also be used again to capture error data in debug session 3.

After the trigger point, the EI index detects the error interval and the EI tag inadvertently selects the error core. If the EI index is zero, this interval can be skipped, otherwise the error core can be compared to the GDS selector's golden data stream. May be captured in the EC tag on-chip buffer for M cycles through a comparison result bit referred to herein as an EC tag.

The size of the EC tag buffer may be n x M to handle the worst case where all cores have errors. A shadow EC tag buffer is needed because the capture process is performed in a continuous clock cycle.

When the EC tag buffer is full, the data can be moved to the shadow and stored in the DRAM. Then the next tag bit is loaded into the register in the DRAM and the debug data can be analyzed during this N cycles in this manner. After the second session is completed, the tag bits stored in the DRAM are transferred to the workstation and analyzed for the third session, which can be performed through the hardware structure 400 of FIG.

6 is a view for explaining a golden data stream selector for generating golden data in real time in the debug session 2.

In the present invention, a golden data stream can be generated by selecting an error-free core.

For this purpose, a GDS tag and a GDS index can be used to select error-free data for each section of the Golden Data Stream (GDS) selector 600.

The GDS tag can be interpreted as a GDS tag consisting of a GDS index and a core_sel for core selection. In addition, the GDS index determines how to select the golden data, and the core_sel can be interpreted as a selected core set with no errors.

Specifically, cores without errors are collected in core_sel if the EI index is not zero.

The algorithm can then determine the GDS index.

If the GDS index is 0, it indicates that the core data can be selected from the core_sel. If the GDS index is 1, it means that all the cores have an error during the corresponding interval. In addition, golden data can be selected from DRAM.

On the other hand, if the sum of the EI tags is equal to n, the GDS index can be interpreted as 1.

Otherwise, the GDS index can be interpreted as zero. First, core_sel can be performed only when the EI index is '1' and the GDS index is '0'. Further, the maximum number of cores can be selected by calculating the number of cores of the core_sel.

7 is a diagram illustrating a hardware structure 700 for determining an error cycle in debug session 2.

Referring to the hardware structure 700, a plurality of cores 701 may be implemented with the same size.

The core selector 702 may select a core for detection of an error interval and compare data and golden data from the selected core via comparators 703. As a result of the comparison, data estimated to be error can be classified through the EC tag 704 and stored via the shadow EC tag 705. [ This error section can be stored.

When the debug process is started, a debug configuration is performed and tag bits are uploaded to each tag register. In addition, in the case of the added golden data, they can be sequentially uploaded to the trace buffer 706 and the shadow buffer 707 since they must be compared with the debug data in consecutive clock cycle order.

The Golden Data Stream (GDS) selector 711 may use the GDS tag 708 to select error free data for each interval. The GDS tag can be interpreted as a GDS tag consisting of a GDS index and a core_sel for core selection. In addition, the GDS index determines how to select the golden data, and the core_sel can be interpreted as a selected core set with no errors.

Specifically, cores without errors are collected in core_sel if the EI index is not zero.

The EI tag 709 and the EI index 710 may operate as the inputs of the core selector 702 and may be selected from a plurality of cores 701 according to the combination of the outputs of the EI tag 709 and the EI index 710 The core can be selected.

FIG. 8 is a diagram illustrating an embodiment 800 in which debug software analyzes an error cycle through a tag bit extracted after debug session 2.

According to embodiment 800, the result tag bits 810, i.e., EI tags, of the debug session 2 may be separated into an error interval matrix 820 and an error cycle matrix 830. Meanwhile, the resultant tag bits 810 of the debug session 2 can be represented by an EC index and an EC tag 840 for the debug session 3.

Specifically, after transmitting the EC tag to the debug software, it can be regenerated to detect error data of all cores in a series of clock cycles during the third session. First, the error period matrix is calculated by the EC tag and the error interval matrix, and if the length of the MISR is 5, a 4 × 5 error period matrix is generated for each interval.

Using this matrix, an EC index is generated, which indicates that at least one core in the corresponding clock cycle is faulty or not.

First, if the EI index is '0', the corresponding interval is ignored. If the EI index is '1', the required number of EC indexes is M. If the EC index is 1, an EC tag is required by n and can be regenerated by the error clock matrix. If the EC index is '0', the period can be ignored, and the EC tag can be regenerated.

Figure 9 is a diagram illustrating a hardware architecture 900 for capturing error cycles in debug session 3.

Looking at the hardware structure 900, a plurality of cores 901 may be implemented with the same size. The core selector 902 selects a core for detection of the error interval and may be stored via the trace buffer 903 and the shadow buffer 904. [

The loaded data can be output to the EC tag 905, the shadow EC tag 906, the EC index 907, the shadow EC index 908, and the EI index 909. Each output may be selectively transmitted to an input of a core selector to be used as information for selecting a specific core among the plurality of cores 901. [

In FIGS. 10 to 12, the timings for the sessions 1 to 3 will be described in more detail.

10 is a timing diagram 1000 for debug session 1.

To illustrate how to communicate with the DRAM during the three debug sessions, the operation of the proposed DfD module can be captured in the EI index and EI tag registrations where each interval is compressed into a MISR signature as compared to the golden signature in the first session . The EI index is captured in the register and is offloaded to the workstation after the debug session because of the small data volume. Meanwhile, the captured EI tag (n bits) is stored in the DRAM and the next golden signature (L bit) can be loaded in the DRAM.

11 is a timing diagram 1100 for debug session 2.

In the second session, the error core of the erroneous interval can be compared to the golden data stream and captured in the EC tag buffer. Shadow EC tags are required because the capture process is performed during M cycles. The dotted line means that the process is performed conditionally, and if the EI index is zero, it is not necessary to perform error clock cycle detection.

If the EI index is 1, the EC tag is selectively captured by the EI tag.

When the EC tag buffer is full, the tag bit can move to the shadow bit. Generally, the amount of captured tag bits differs from one M cycle to another. However, it is possible to know when the EC tag is filled with the calculated EI tag and the EI index before the second session.

As a result, the DfD controller can determine the shift timing, and subsequent data can be stored in the DRAM. Additional golden data can be loaded into the trace and shadow buffers, in turn, as needed during the next interval.

With this mechanism, no additional golden data is needed for the sequence. Thereafter, if the EI index is 1, the EI tag can be loaded, and the GDS tag can be loaded for the next interval.

12 is a timing diagram 1200 for debug session 3.

In the third session, the error data of all cores is captured in the trace buffer, and a shadow buffer is needed for the reason described above. As with the second session, the timing at which the trace buffer is full can be controlled by the EI index, EC index and EC tags.

Once the trace buffer is full, the captured data can be moved to the shadow buffer and stored in the DRAM. Finally, when the EI index is 1, the EC index and the EC tag are loaded, and when the EC index is 1, the EC tag is provided so that it can be compared with the debug data, thereby preventing duplication of necessary data.

The save and load operations are irregular in the second and third sessions, so the saved time domain is required and can be determined using the tag bits as described above.

Also, there may be a limit on n to satisfy the behavior of the third session. In the worst case where every core has an error per cycle, the minimum retention time can be assumed to be M / n cycles. Thus, the maximum n is less than M divided by the write access latency. For example, if the average access latency of the DRAM is 25 ns and the circuit is running at the 1 GHz frequency, the maximum n is 20 when M is 512.

13 is a diagram for explaining a post silicon debug device 1300 according to an embodiment.

The post silicon debug device 1300 according to one embodiment may include a session 1 processing unit 1310, a session 2 processing unit 1320, and a session 3 processing unit 1330.

The session 1 processor 1310 according to an exemplary embodiment generates golden data corresponding to a debug section based on a simulation before the start of debug and uploads the generated golden data to the trace buffer to determine error intervals in the debug section have.

The session 1 processor 1310 according to an embodiment uploads the golden data to the trace buffer, and uploads the data through an external interface including a JTAG (Joint Test Action Group).

The session 1 processing unit 1310 according to an exemplary embodiment determines data corresponding to a section expected to be not an error as the golden data through simulation and compresses the data through a Multiple Input Signature Register (MISR) And determines whether there is an error. If it is determined that an error has occurred, the data can be recorded using a 1-bit EI tag.

Also, the session 1 processing unit 1310 can record the section in which no error occurs as a result of determination using the index (EI index). In addition, the session 1 processor 1310 may divide and decompress the golden data corresponding to the debug interval into a multiple input signature register (MISR) size, and store the divided and compressed golden data in a DRAM (on-chip DRAM). The session 1 processing unit 1310 may add the generated golden data to the DRAM if all the cores in the detected error period are in error.

The session 2 processor 1320 according to one embodiment may detect an error cycle corresponding to the detected error intervals. The session 2 processor 1320 may determine an error cycle for each cycle and store the error cycle in the form of a tag bit (EC tag), and store the determined error cycle using a shadow buffer.

The session 3 processor 1330 according to an exemplary embodiment can selectively debug error data corresponding to the detected error cycle, selectively stores error data corresponding to the detected error cycle, You can debug it selectively.

The debug configuration module can be controlled through a trace port such as JTAG during the configuration phase. This module can control the trigger point of the debug process and select CUD and debug data. Also, the MISR set and the golden register may be included in the session 1 processing unit 1310 for the first session.

The tag bit register may be included in the processing units 1320 and 1330 for the second and third sessions. These buffers and tag bit registers can be reused to reduce hardware area overhead during the entire debug session.

When the debug process starts, a finite state machine (FSM) is performed to control the debug module and communicate with the DRAM.

The FSM in the first session can capture the EI tag and control the timing of communicating with the DRAM controller using an interval counter. In the second session, the FSM can use the GDS tag to control the GDS selector to generate a golden data stream. If additional golden data is needed, the FSM may in turn select a trace buffer and a shadow buffer to load data from the DRAM. The FSM can also determine the timing of capturing the EC tags and moving the EC tags to the shadow EC tags. Timing information that is full of EC tags can be calculated using the EI tag before the second session and can be configured at the debug configuration stage. After moving the data to the shadow EC tag, the FSM can support operations to communicate with the DRAM controller as previously described.

In the session 3 processor 1330, the FSM may capture error data in the trace buffer, move to the shadow buffer, and control the timing of communication with the DRAM. In order to satisfy the operation of the session 2 processing unit 1320 and the session 3 processing unit 1330, the saved time area can be controlled by the FSM and the interval counter.

Adapters can be added in front of the shadow EC index, EC tags, and shadow buffers to store data in the DRAM. With this adapter, debug data can be transferred to the memory interface even if the frequency of the interface is different from CUD.

The post silicon debug device 1300 according to an embodiment is capable of using DRAM and debug time analysis using a probability model.

Probability models can be used by DfD designers to establish various debug strategies and to determine the size of DfD modules.

In order to simplify the probability model, it is assumed that an error occurs in all of the cores. In this case, the expectation values of Pi and X (E [Xi]) can be expressed as follows.

[Equation 1]

In Equation (1), pi can be interpreted as the error clock period probability of the i-th core, and Pi can be interpreted as the Pi error interval probability of the i-th core. Xi can be interpreted as a random variable as the number of erroneous intervals of the i-th core.

Since the previous method stores only the debug data for the error interval, the DRAM usage of the i-th session in the previous method can be calculated as shown in Equation (2).

&Quot; (2) "

Xi can be interpreted as a random variable as the number of erroneous intervals of the i-th core, and DUprevi can be interpreted as the DRAM usage Tprev (prop) debug time of the i-th session. S is the size of the timestamp identifying the error interval and LN / M can be interpreted as the golden MISR signature number stored in the DRAM.

E [Y], E [Z] and E [Z '] are required to calculate the amount of DRAM used in the proposed method. They can be explained as follows.

First, E [Y] can be calculated through [Equation 3].

&Quot; (3) "

Pi can be interpreted as the Pi error interval probability of the ith core. Xi can be interpreted as a random variable as the number of erroneous intervals of the i-th core.

Next, E [Z] can be calculated through the following equation (4).

&Quot; (4) "

Pi can be interpreted as the Pi error interval probability of the ith core. Xi can be interpreted as a random variable as the number of erroneous intervals of the i-th core.

Next, E [Z '] can be calculated through [Equation 5].

&Quot; (5) "

Pi can be interpreted as the Pi error interval probability of the ith core. Xi can be interpreted as a random variable as the number of erroneous intervals of the i-th core.

A Golden MISR signature is required in the first session, and the EI index and EI tag can be stored in the DRAM every M cycles, and as a result, the DRAM usage for the first session can be described as [Equation 6].

&Quot; (6) "

In Equation (6), the EI index can be interpreted as N / M and the EI tag can be interpreted as nE [Z].

In the second session, GDS tags, additional golden data, EI indexes, and EI tags can be uploaded to the DRAM to detect the error clock period. The GDS tag and the additional golden data can be described as [Equation 7].

&Quot; (7) "

The sum of the GDS tag, the additional golden data, the EI tag, and the EI index is the total data volume uploaded before the start of the second session. After the debug process is started, the EC tags can be stored in the DRAM every M cycles.

Thus, the DRAM usage of the second session can be described as [Equation 8].

&Quot; (8) "

의 볼륨이다. 즉, 구간 동안 모든 코어의 오류 발생 분포가 이항 분포를 따르고 각 Pi가 동일하다고 가정할 수 있다.In Equation (8), the captured EC tag is used for the second session

. That is, it can be assumed that the distribution of error occurrence of all cores during the interval follows the binomial distribution and each Pi is the same.

In the third session, EI index, EC index and EC tag can be uploaded to DRAM to detect error data of all cores. EC tags can be regenerated as described above, and when the debug process is started, the error data of all cores can be stored in the DRAM every M cycles. As a result, DRAM usage for the third session is calculated as:

&Quot; (9) "

In Equation (9), the storage area of the DRAM is required to perform the debug process, and the area may be equal to or greater than the maximum DRAM usage in all the sessions.

That is, the DRAM usage for the previous and proposed methods can be described as [Equation 10].

&Quot; (10) "

On-chip sampling time and communication time are required to calculate the debug execution time.

The on-chip sampling time is related to the clock cycle from the trigger point to the end of the debug session. Previously, the entire on-chip sampling clock cycle was nN. However, in the present invention, only 3N is required.

Assuming there is no error in all cores, only N is needed because only the first session is needed. That is, the present invention can significantly reduce the debug time with respect to the on-chip sampling time.

The communication time is the time that the debug data is uploaded and offloaded through the trace port. In the previous method, the golden MISR signature is uploaded once and the error data of each session and the corresponding S can be offloaded in all sessions.

On the other hand, in the present invention, DRAM usage must be transmitted during three sessions, and when there is no error in all cores, only DRAM usage of session 1 can be transmitted.

As a result, using the present invention, it is possible to provide a technique of selectively debugging only data estimated to be an error in post silicon debugging in a multicore environment using an on-chip DRAM. In addition, by selectively compressing and analyzing the error interval using the Multiple Input Signature Register (MISR), the debug data is stored in the DRAM existing in the chip, so that the debugging is completed in only three debug sessions This can shorten the debug time. In addition, by shortening the total debug time, it is possible to reduce the total chip manufacturing time and the cost for mass production of the chip.

The apparatus described above may be implemented as a hardware component, a software component, and / or a combination of hardware components and software components. For example, the apparatus and components described in the embodiments may be implemented within a computer system, such as, for example, a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable array (FPA) A programmable logic unit (PLU), a microprocessor, or any other device capable of executing and responding to instructions. The processing device may execute an operating system (OS) and one or more software applications running on the operating system. The processing device may also access, store, manipulate, process, and generate data in response to execution of the software. For ease of understanding, the processing apparatus may be described as being used singly, but those skilled in the art will recognize that the processing apparatus may have a plurality of processing elements and / As shown in FIG. For example, the processing unit may comprise a plurality of processors or one processor and one controller. Other processing configurations are also possible, such as a parallel processor.

The software may include a computer program, code, instructions, or a combination of one or more of the foregoing, and may be configured to configure the processing device to operate as desired or to process it collectively or collectively Device can be commanded. The software and / or data may be in the form of any type of machine, component, physical device, virtual equipment, computer storage media, or device , Or may be permanently or temporarily embodied in a transmitted signal wave. The software may be distributed over a networked computer system and stored or executed in a distributed manner. The software and data may be stored on one or more computer readable recording media.

The method according to an embodiment may be implemented in the form of a program command that can be executed through various computer means and recorded in a computer-readable medium. The computer-readable medium may include program instructions, data files, data structures, and the like, alone or in combination. The program instructions to be recorded on the medium may be those specially designed and configured for the embodiments or may be available to those skilled in the art of computer software. Examples of computer-readable media include magnetic media such as hard disks, floppy disks and magnetic tape; optical media such as CD-ROMs and DVDs; magnetic media such as floppy disks; Magneto-optical media, and hardware devices specifically configured to store and execute program instructions such as ROM, RAM, flash memory, and the like. Examples of program instructions include machine language code such as those produced by a compiler, as well as high-level language code that can be executed by a computer using an interpreter or the like. The hardware devices described above may be configured to operate as one or more software modules to perform the operations of the embodiments, and vice versa.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. For example, it is to be understood that the techniques described may be performed in a different order than the described methods, and / or that components of the described systems, structures, devices, circuits, Lt; / RTI > or equivalents, even if it is replaced or replaced.

Therefore, other implementations, other embodiments, and equivalents to the claims are also within the scope of the following claims.

300: Debug method of post silicon
310: Debug Session 1
311: Create Golden MISR Signatures
312: Capture result of interval detection
313: Detection of error intervals
320: Debug Session 2
321: Generation of GDS tag bits
322: Capture result of clock cycle detection
323: Generate error interval tag bits
330: Debug Session 3
331: Generate error cycle tag bits
332: Capture error data
333: Debug the captured data

Claims (16)

Generating golden data corresponding to a debug section based on a simulation before the start of debug and uploading the generated golden data to a trace buffer to identify error intervals in the debug section;
Detecting an error cycle corresponding to the identified error intervals; And
And selectively debugging the error data corresponding to the detected error cycle,
Wherein the step of selectively debugging error data corresponding to the detected error cycle comprises:
Selectively storing error data corresponding to the detected error cycle; And
Selecting and debugging the stored error data
/ RTI >
The method according to claim 1,
The step of determining the error intervals comprises:
Uploading the golden data to the trace buffer through an external interface including JTAG (Joint Test Action Group)
/ RTI >
Generating golden data corresponding to a debug section based on a simulation before the start of debug and uploading the generated golden data to a trace buffer to identify error intervals in the debug section;
Detecting an error cycle corresponding to the identified error intervals; And
And selectively debugging the error data corresponding to the detected error cycle,
The step of determining the error intervals comprises:
Determining, as the golden data, data corresponding to a section expected to be not an error through the simulation;
Compressing the data through the MISR (Multiple Input Signature Register) while performing the debug, comparing the errored interval with the golden data, and determining whether the error is erroneous; And
And recording the data in which an error occurs as a result of the determination using a 1-bit EI tag
/ RTI >
The method of claim 3,
As a result of the determination, recording is performed using an index (EI index)
Further comprising the steps of:
The method of claim 3,
The step of determining error intervals in the debug interval comprises:
Dividing the golden data corresponding to the debug section into MISR (Multiple Input Signature Register) sizes and compressing the divided data; And
Storing the divided and compressed golden data in an in-chip DRAM (DRAM)
/ RTI >
delete The method according to claim 1,
If all the cores in the identified error period are in error, adding the generated golden data to a DRAM
Further comprising the steps of:
Generating golden data corresponding to a debug section based on a simulation before the start of debug and uploading the generated golden data to a trace buffer to identify error intervals in the debug section;
Detecting an error cycle corresponding to the identified error intervals; And
And selectively debugging the error data corresponding to the detected error cycle,
Wherein the detecting the error cycle comprises:
The error cycle is determined for each cycle and stored in the form of an EC tag, and the error cycle is stored using a shadow buffer
/ RTI >
A session 1 processing unit for generating golden data corresponding to a debug section based on a simulation before the start of debug and uploading the generated golden data to a trace buffer to identify error intervals in the debug section;
A session 2 processing unit for detecting an error cycle corresponding to the identified error intervals; And
And a session 3 processing unit for selectively debugging the error data corresponding to the detected error cycle,
The session 3 processing unit,
The error data corresponding to the detected error cycle is selectively stored, and the stored error data is selected and debugged
/ RTI >
10. The method of claim 9,
The session 1 processing unit,
Uploading the golden data to the trace buffer through an external interface including JTAG (Joint Test Action Group)
/ RTI >
A session 1 processing unit for generating golden data corresponding to a debug section based on a simulation before the start of debug and uploading the generated golden data to a trace buffer to identify error intervals in the debug section;
A session 2 processing unit for detecting an error cycle corresponding to the identified error intervals; And
And a session 3 processing unit for selectively debugging the error data corresponding to the detected error cycle,
The session 1 processing unit,
Through the simulation, it is determined that the data corresponding to the section expected to be non-error is determined as the golden data, and the debugging is performed through the Multiple Input Signature Register (MISR) And judges whether or not an error has occurred, and writes the error-generating data using a 1-bit EI tag.
12. The method of claim 11,
The session 1 processing unit,
And wherein an interval (EI index) is used to record an interval in which no error occurs as a result of the determination.
12. The method of claim 11,
The session 1 processing unit,
Dividing the golden data corresponding to the debug section into the MISR (Multiple Input Signature Register) size, and storing the divided and compressed golden data in a DRAM (on-chip DRAM).
delete 10. The method of claim 9,
The session 1 processing unit,
And adding the generated golden data to a DRAM if all of the cores in the identified error period are an error.
A session 1 processing unit for generating golden data corresponding to a debug section based on a simulation before the start of debug and uploading the generated golden data to a trace buffer to identify error intervals in the debug section;
A session 2 processing unit for detecting an error cycle corresponding to the identified error intervals; And
And a session 3 processing unit for selectively debugging the error data corresponding to the detected error cycle,
The session 2 processing unit,
Wherein the error cycle is determined for each cycle and stored in the form of an EC tag, and the determined error cycle is stored using a shadow buffer.

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