JP2007080183A - Data processor and its control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique for performing verification of higher reliability and for verifying an operation of a device at a higher speed. <P>SOLUTION: When detecting a request for writing processing data in a main memory 404, a determination is made on whether an external device is an operation verifying object device, and a determination is also made on whether an address in the main memory 404 of a writing requester is in a predetermined address area. When the external device is the operation verifying object device and the address in the main memory 404 of the writing requester is in the predetermined address area, expected value data corresponding to the processing data is read out of the main memory 404. A determination is made on whether or not the processing data coincides with the read-out data. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a technique for verifying the operation of an external device, particularly an LSI logic circuit.

  The scale of logic systems including LSIs is increasing year by year, and the functions installed in the systems are becoming more sophisticated and diversified. Under such circumstances, as a means for efficiently realizing the target system, the CPU, peripheral input / output control device, image processing device, and other circuits are electrically connected using a bus to one chip. The on-board system LSI is being developed. In order to meet the demands for the performance of electronic devices that are expanding year by year, the amount of data handled by system LSIs has increased dramatically, and in response to this, large-capacity memory devices are being used. In verification of a circuit that handles enormous data such as image processing and moving image processing, enormous time is required to verify all the events that can occur in a real machine using logic simulation, which is impossible in practice.

Therefore, a technique for speeding up verification using a device called an emulator is used (see, for example, Patent Document 1). However, an emulator requires a lot of time to build a verification environment and is slower than an actual machine operation, so it must be used only for a specific test pattern. For these reasons, verification using large-capacity data such as moving image processing is performed by using an engineering sample (hereinafter referred to as ES) to perform hardware verification simultaneously with software verification. As a verification method, a method is used in which processing data stored in a memory after completion of a series of data processing by hardware is compared with expected value data stored in advance in the ROM or memory by the CPU.
JP 2004-361171 A

  However, in these methods, since the processed data and the expected value data are compared after a series of data processing in the hardware is completed, it is difficult to analyze the cause when the failure occurs. As another data comparison method, a method in which the CPU compares the processing data with the expected value data for each data processing can be considered. However, in this case, the expected value and the processing data read from the CPU are added to the original data processing sequence every time, so that the reliability of the test is lowered and the simulation time is increased.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a technique for performing device operation verification at a higher speed and performing verification with higher reliability.

  In order to achieve the object of the present invention, for example, a data processing apparatus of the present invention comprises the following arrangement.

That is, when an operation verification target device included in a plurality of external devices performs a normal operation, a first memory that holds data obtained from the operation verification target device as expected value data;
A second memory holding information for specifying the operation verification target device;
A third memory holding information indicating a predetermined address area in the first memory;
First determination means for determining whether or not the external device of interest is an operation verification target device when detecting a request to write processing data obtained as a result of the operation of the external device of interest to the first memory; ,
Second detection means for determining whether the address in the first memory of the write request destination is within the predetermined address area when the request is detected;
As a result of the determination processing by the first determination unit and the second determination unit, the target external device is an operation verification target device, and the address in the first memory of the write request destination is the predetermined address A reading means for reading expected value data corresponding to the processing data from the first memory if within the area;
Verification means for verifying the operation of the external device of interest by determining whether or not the processing data matches the data read by the reading means.

  In order to achieve the object of the present invention, for example, a method for controlling a data processing apparatus of the present invention comprises the following arrangement.

That is, when an operation verification target device included in a plurality of external devices performs a normal operation, a first memory that holds data obtained from the operation verification target device as expected value data;
A second memory holding information for specifying the operation verification target device;
A control method of a data processing apparatus comprising: a third memory that holds information indicating a predetermined address area in the first memory,
A first determination step of determining whether or not the target external device is an operation verification target device when detecting a request to write processing data obtained as a result of the operation of the target external device to the first memory; ,
A second determination step of determining whether an address in the first memory of a write request destination is within the predetermined address area when the request is detected;
As a result of the determination processing in the first determination step and the second determination step, the target external device is an operation verification target device, and the address in the first memory of the write request destination is the predetermined address If within the region, a read step of reading expected value data corresponding to the processing data from the first memory;
A verification step of verifying the operation of the external device of interest by determining whether or not the processing data matches the data read in the reading step.

  With the configuration of the present invention, it is possible to perform device operation verification at a higher speed and to perform verification with higher reliability.

  Hereinafter, the present invention will be described in detail according to preferred embodiments with reference to the accompanying drawings.

<About data processing device>
In the present embodiment, a data processing apparatus connected to a plurality of external devices including a device to be verified for operation will be described.

  Here, the operation verification target device outputs data of a processing result when a predetermined processing is performed. The data of the processing result is as expected if the operation of the operation verification target device is normal. However, if the operation of the operation verification target device is not normal, the processing result data is not as expected.

  Therefore, in this embodiment, first, data (expected value data) that will be output when the operation verification target device is normal is held in the memory. The data processing apparatus receives the processing result data output from the operation verification target device, compares the received data with the expected value data held in the memory, and the processing result data is the expected data. It is checked whether or not. As a result, it is possible to verify whether or not the operation of the operation verification target device is normal.

  FIG. 1 is a block diagram showing a hardware configuration and a data flow of a data processing apparatus according to the present embodiment. As shown in the figure, the data processing apparatus according to the present embodiment includes a memory controller 110 and a memory 106.

  When the memory controller 110 detects an access to the memory 106 from an external device, the memory controller 110 controls the access. When a request for writing the data output from the operation verification target device among the external devices to the memory 106 is received from the operation verification target device, the processing result data is verified.

  The memory 106 holds data that is expected to be output from the operation verification target device, that is, expected value data when the operation verification target device is normal. When there are a plurality of operation verification target devices, expected value data is held for each operation verification target device. The memory 106 also has an empty area for holding processing result data output from the operation verification target device.

  Next, the configuration of the memory controller 110 will be described. The memory controller 110 receives data (write data 102) obtained as a result of processing on the external device side, a request to write the write data 102 to the memory 106, and information (bus master identifier) for identifying the external device.

  When receiving a request to write the write data 102 to the memory 106, the write command generating apparatus 101 generates a command (write command) that specifies an address on the memory 106 to which the write data 102 is written.

  Upon receiving this request, the read command generation device 104 generates a command (read command) that specifies an address on the memory 106 in which expected value data corresponding to the write data 102 is held. The address on the memory 106 in which the expected value data corresponding to the write data 102 is held can be obtained, for example, by adding a predetermined bias to the address on the memory 106 to which the write data 102 is written.

  On the other hand, the register 109 holds the bus master identifier of the operation verification target device and information (area information) for specifying an area (the above-mentioned empty area) for storing the write data 102 on the memory 106.

  Upon receiving the write request, the control device 103 first compares the bus master identifier received from the external device with the bus master identifier held in the register 109, and determines whether or not this external device is an operation verification target device. Check. Further, the control device 103 refers to the area information held in the register 109 and checks whether or not the write address included in the command generated by the write command generation device 101 is included in the empty area. To do.

  As a result of the above two check processes, when the external device is the operation verification target device and the write address is included in the empty area, the control device 103 controls the command selection device 105 to select the read command. . As a result, the command selection device 105 reads expected value data (read data 107) from the memory 106 based on the selected read command. The read data 107 corresponds to the write data 102, and the write data 102 and the read data 107 should match if the operation verification target device is operating normally.

  Therefore, the comparison device 108 compares the write data 102 and the read data 107 and checks whether they match each other. If they do not coincide with each other, it means that the operation of the operation verification target device is not normal, and the comparison device 108 outputs that fact.

  On the other hand, if the external device is not the operation verification target device and / or the write address is not included in the free area as a result of the above two check processes, the control device 103 controls the command selection device 105 to write Lets you select a command. As a result, the command selection device 105 writes the write data 102 in the empty area of the memory 106 based on the selected write command.

<Devices incorporating data processing devices>
FIG. 4 is a block diagram showing a hardware configuration when the data processing apparatus that performs the above-described operation is incorporated in a system including a device whose operation is to be verified.

  Image data input from a digital camera or the like via the USB IF 405 is transferred to the memory controller 403 (having the same configuration as the memory controller 110 shown in FIG. 1) via the bus 402 by the DMAC 406. The memory controller 403 transfers this image data to the main memory 404 and stores it there.

  When the CPU 401 controls the JPEG encoder 410, the JPEG encoder 410 sequentially reads out the image data stored in the main memory 404 by the DMAC 409, and performs an encoding process on the read image data. The encoding result data (encoded data) is stored in the main memory 404 again.

  When the encoding process for one frame of image data is completed, the CPU 401 reads out the encoded data for one frame that has been encoded earlier from the main memory 404 via the memory controller 403. The read encoded data is transferred to the flash ROM 408 via the ROMC 407 and stored therein.

  In the system having such a configuration, the operation of the JPEG encoder 410 will be described using the memory controller 403 as an example, and the operation of the memory controller 403 will be described below.

<About processing performed by the data processing device>
FIG. 2 is a flowchart of processing performed by the memory controller 110 constituting the data processing apparatus when the data processing apparatus is incorporated in a system including a device whose operation is to be verified, as shown in FIG.

  First, in the previous stage in which the processing according to the flowchart of FIG. 10 is performed, various initialization processes such as system initialization are performed. As a result, the memory controller 403 can accept a data write request / read request to the main memory 404 from a “bus master” such as the CPU 401 or the DMAC 109.

  Further, it is assumed that the main memory 404 holds expected value data (here, encoded data obtained when the JPEG encoder 410 performs a normal operation).

  Each unit constituting the memory controller 403 receives a request (step S202). In this state, when each unit detects that an access request from the external device (bus master) to the main memory 404 is a request to read data from the main memory 404 (Read request), the process is performed via step S203. Proceed to S204.

  Then, the read command generation device 104 generates a command (Read command) for reading the data that is the target of the read request from the main memory 404 (step S204). Then, the command selection device 105 reads the data requested to be read based on this command (step S204).

  On the other hand, if the access request to the main memory 404 is a data write request to the main memory 404, the process proceeds to step S205 via step S203. Then, the control device 103 checks whether or not a test mode is set for the current memory controller 403 (step S205). The memory controller 403 can set either a mode for performing an operation verification of an external device or a mode for not performing the operation verification. For example, when the operation verification is performed, TestMode = 1 is set, and when the operation verification is not performed, TestMode = 0 is set. The value of TestMode is set in the register 109 in advance. Therefore, in step S205, the control device 103 refers to the value of TestMode set in the register 109 and performs a process of checking whether the referenced value is 1 or 0.

  If TestMode = 0, the process proceeds to step S206. Then, the write command generating apparatus 101 generates a command (Write command) for writing the data (encoded data here) received together with the write request to the main memory 404 as the data to be written (step S206). Based on this command, the command selection device 105 writes the write-requested data in the main memory 404 (step S206).

  On the other hand, if TestMode = 1, the process proceeds to step S207. Then, the control device 103 compares the bus master identifier received from the external device together with the write request with the bus master identifier held in the register 109 (step S207). Thereby, it is checked whether or not this external device is an operation verification target device (here, JPEG encoder 410) (step S207). If the bus master identifiers do not match as a result of the check, it is determined that this external device is not an operation verification target device, and the process proceeds to step S206.

  On the other hand, if the respective bus master identifiers match, the process proceeds to step S208. Then, the control device 103 refers to the area information held in the register 109 and checks whether or not the write address included in the command generated by the write command generation device 101 is included in the empty area. (Step S208). If it is not included as a result of the check, the process proceeds to step S206.

  On the other hand, if it is included, the process proceeds to step S209. First, the control device 103 controls the command selection device 105 to select a read command. As a result, the command selection device 105 reads expected value data from the memory 106 based on the selected read command. Next, the comparison device 108 compares the data requested to be written with the read expected value data and checks whether or not they match (step S210). If they do not match as a result of the check, it means that the operation of the operation verification target device is not normal. Therefore, the comparison device 108 outputs that fact (error) to the CPU 401 using an interrupt (step S211). .

<Processing performed by the system>
FIG. 3 is a flowchart of processing performed by the system shown in FIG. First, the CPU 401 reads a program for causing the memory controller 403 to execute processing according to the flowchart of FIG. 2 from the flash ROM 408, and stores it in the main memory 404 via the memory controller 403 (step S302).

  Next, the CPU 401 reads the expected value data to be stored in the main memory 404 from the flash ROM 408 and stores it in the main memory 404 via the memory controller 403 (step S303). Next, the CPU 401 reads the bus master identifier and area information from the flash ROM 408, outputs them to the register 109, and stores them therein (step S304).

  Next, the CPU 401 sets a value of TestMode (step S305). After performing the above processing, the CPU 401 instructs the JPEG encoder 410 to execute an image encoding process for one frame, so the JPEG encoder 410 starts processing according to this instruction (step S306). ). When the JPEG encoder 410 completes the image encoding process for one frame, the CPU 401 instructs the memory controller 403 to execute the process according to the flowchart of FIG. Thereby, the memory controller 403 executes processing according to the flowchart of FIG. 2 (step S306). 2 is performed by the memory controller 403 executing the program stored in the main memory 404 in step S302.

  Next, the CPU 401 determines whether or not an error has been received from the comparison device 108 of the memory controller 403 (step S307). If an error has been received, the process proceeds to step S308 to interrupt the operation of each part of the system and notify that an error has occurred (step S308). The notification form is not particularly limited. For example, when a monitor is connected to the bus 402, the fact that the encoding of this frame has failed together with the frame number of the currently encoded image on this monitor. Is displayed.

  With the above processing, according to the present embodiment, since the memory controller is provided with the data comparison function with the expected value data, the validity of the processing data is checked by the memory controller. This eliminates the necessity and improves the verification speed.

  In addition, since the data comparison is performed for each process without impairing the verification speed, error information can be immediately notified to the CPU when a problem occurs, and the cause of the problem can be easily identified.

  In the present embodiment, an empty area for storing processing data and an area for storing expected value data are provided in the main memory 404. However, when the processing data matches the expected value data, this processing data may be overwritten on the expected value data. In this case, it is not necessary to provide an area for storing processing data separately from the area for storing expected value data, so that the memory efficiency can be improved.

It is a block diagram which shows the hardware constitutions of the data processor which concerns on embodiment of this invention, and the flow of data. FIG. 4 is a flowchart of processing performed by the memory controller 110 constituting the data processing apparatus when the data processing apparatus is incorporated in a system including a device whose operation is to be verified. 5 is a flowchart of processing performed by the system shown in FIG. It is a block diagram which shows the hardware constitutions at the time of incorporating a data processor into the system containing the device which is going to verify operation | movement.

Claims (5)

A first memory that holds data obtained from the operation verification target device as expected value data when the operation verification target device included in the plurality of external devices performs normal operation;
A second memory holding information for specifying the operation verification target device;
A third memory holding information indicating a predetermined address area in the first memory;
First determination means for determining whether or not the external device of interest is an operation verification target device when detecting a request to write processing data obtained as a result of the operation of the external device of interest to the first memory; ,
Second detection means for determining whether the address in the first memory of the write request destination is within the predetermined address area when the request is detected;
As a result of the determination processing by the first determination unit and the second determination unit, the target external device is an operation verification target device, and the address in the first memory of the write request destination is the predetermined address A reading means for reading expected value data corresponding to the processing data from the first memory if within the area;
A data processing apparatus comprising: verification means for verifying the operation of the target external device by determining whether or not the processing data matches the data read by the reading means.   The data processing apparatus according to claim 1, wherein the external device is an LSI logic circuit.   The data processing apparatus according to claim 1, wherein the verification unit notifies an error when the processing data does not match the data read by the reading unit. Furthermore,
As a result of the determination process by the first determination unit and the second determination unit, the target external device is not an operation verification target device, and / or the address in the first memory of the write request destination is the The data processing apparatus according to claim 1, further comprising a writing unit that writes the processing data to the address when it is not in a predetermined address area. A first memory that holds data obtained from the operation verification target device as expected value data when the operation verification target device included in the plurality of external devices performs normal operation;
A second memory holding information for specifying the operation verification target device;
A control method of a data processing apparatus comprising: a third memory that holds information indicating a predetermined address area in the first memory,
A first determination step of determining whether or not the target external device is an operation verification target device when detecting a request to write processing data obtained as a result of the operation of the target external device to the first memory; ,
A second determination step of determining whether an address in the first memory of a write request destination is within the predetermined address area when the request is detected;
As a result of the determination processing in the first determination step and the second determination step, the target external device is an operation verification target device, and the address in the first memory of the write request destination is the predetermined address If within the region, a read step of reading expected value data corresponding to the processing data from the first memory;
A verification step of verifying the operation of the external device of interest by determining whether or not the processing data and the data read in the reading step match. Control method.

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