JP2003208361A - Memory test method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory test method by which the number of processes required for a test of a ROM and a RAM can be reduced, test time can be shortened, the required number of elements can be reduced and costs can be saved. <P>SOLUTION: The memory test method includes the steps of: reading data from the ROM; writing the data read from the ROM into the RAM; reading the data written in the RAM; and confirming the operations of the ROM and the RAM on the basis of the data read from the RAM. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory testing method, and more particularly to an operation confirmation test of each memory in an electric circuit equipped with a read only memory (ROM) and a rewritable memory (RAM).

[0002]

2. Description of the Related Art FIG. 1 is a block diagram illustrating an electric circuit for performing a conventional memory test. On the circuit board 1, the ROM block 2 and the RAM block 3 to be tested are
And a control circuit 4, and the ROM block 2 and R
The AM block 3 and the control circuit 4 communicate with each other via a data / address bus provided on the circuit board 1. The control circuit 4 is a circuit that reads and writes data from and into the ROM block 2 and the RAM block 3, for example, a CPU, and includes a check circuit 5, an arithmetic circuit 6, and a test data storage unit 7.

FIG. 2 is a ROM in the circuit board 1 of FIG.
It is a block diagram explaining the conventional test of the block 2.
Elements similar to those of FIG. 1 are designated by the same reference numerals. In this figure, the signal flow relating to the test of the ROM block 2 is emphasized. The control circuit 4 sends a ROM control signal, which means a read instruction, to the ROM block 2. R
The data read from the OM block 2 via the data / address bus is calculated in the arithmetic circuit 6 according to a certain rule such as a checksum, and the correct value calculated in advance in the check circuit 5 is used. Collate.

FIGS. 3 and 4 are block diagrams illustrating a conventional test of the RAM block 3 on the circuit board 1 of FIG. In these figures, the signal flow relating to the test of the RAM block 3 is emphasized. In these figures, the same elements as in FIG. 1 are designated by the same reference numerals. First, test data is written in the RAM block 3. FIG. 3 is a block diagram illustrating writing of such test data. The control circuit 4 sends a RAM control signal indicating a write instruction to the RAM block 3,
The test data stored in the test data storage unit 7 of the control circuit 4 is written in the RAM block 3 via the data / address bus.

FIG. 4 is a block diagram for explaining the reading of test data from the RAM block 3 and the subsequent processing. The control circuit 4 sends a RAM control signal, which means a read instruction, to the RAM block 3 in which the test data is written as described above, and reads the test data from the RAM block 3 via the data / address bus. The check circuit 5 of the control circuit 4 uses the original test data read from the test data storage unit 7 and the RAM block 3
It collates with the test data read from.

In the conventional test method as described above, since the ROM and RAM are individually tested,
ROM read, read result confirmation, RAM write,
There is a problem in that the steps of RAM reading and reading result confirmation are required, and the test time becomes long.
There is also a problem in that an arithmetic circuit and a test data storage section are required, resulting in high cost.

[0007]

Therefore, the present invention reduces the number of steps required for testing ROM and RAM,
An object of the present invention is to provide a memory test method that can reduce the test time, reduce the number of required elements, and reduce the cost.

[0008]

According to a first aspect of the present invention, there is provided a memory testing method including a step of reading data from the ROM, and a step of reading the data read from the ROM with the RA.
It is characterized by including a step of writing in M, a step of reading the data written in the RAM, and a step of confirming the operation of the ROM and the RAM based on the data read from the RAM. By performing read control on the ROM and write control on the RAM at the same time, two steps can be performed at one time. In addition, RA which copied the data of ROM
By reading and confirming the M data, it is possible to confirm the normality of the ROM data and the normality of the RAM writing / reading at once.

A memory test method according to a second aspect of the present invention is a step of reading data from the ROM, and the data read from the ROM is stored in the first block of the memory area of the RAM divided into three blocks. Writing the operation data obtained by performing a predetermined operation on the data read from the ROM to the second block of the memory area of the RAM, and writing the operation data from the first and second blocks of the RAM to these blocks. Reading the written data, the first of the RAM
And the operation data obtained by performing a predetermined operation on the data read from the second block, is stored in the third area of the memory area of the RAM.
Writing to a block, reading data written to a first block of the RAM, performing operation check of the ROM based on the data read from the first block of the RAM, the RAM
And a step of reading the data written in the third block, and a step of confirming the operation of the RAM based on the data read from the third block of the RAM. The ROM data is copied to the first block of the RAM in the same procedure as in the first aspect of the present invention, and is read and checked to confirm the normality of the ROM. Then, data that facilitates confirmation is written, for example, inverted data that makes all data "1" when ORed. Further, these two recorded data are read out, and the data resulting from the calculation is written in the remaining third block of the RAM. Read this data,
Make sure that all the data is an expected value, for example, in the case of the above example, "1". Thereby, the normality of the second block and the third block of the RAM can be confirmed.

A memory testing method according to a third aspect of the present invention is the step of reading data from the ROM, and the first block of the data read from the ROM, in which the memory area of the RAM is divided into a plurality of n blocks. To the RAM, reading data from the first block of the RAM, writing the data read from the first block of the RAM to the second block of the RAM, and writing to the second block of the RAM. Similar to the step, writing data read from a certain block of the RAM sequentially to the next block of the RAM, and continuing this until data is written to the last nth block of the RAM, Reading the data written in the nth block of the RAM; Characterized in that on the basis of the data read out from the n-th block of M and a step of performing an operation confirmation of the ROM and RAM. The RAM is divided into a plurality of blocks, the ROM data is copied to one block, and then the copied data is sequentially copied to the next block until the data is written in all blocks, and finally copied. By checking the data of the blocks, it is possible to check all areas of the ROM and RAM.

[0011]

According to the first aspect of the present invention, the ROM reading and the RAM writing are simultaneously performed, and the reading result can be confirmed only once, so that the test time can be shortened. Moreover, since the ROM data is used as the test data, the data for the RAM test becomes unnecessary. Second of the present invention
According to the present invention, the RAM is divided into three blocks, and the entire area of the RAM can be inspected by checking only two blocks of the blocks, so that the test time can be shortened. Moreover, since the ROM data is used as the test data, the data for the RAM test becomes unnecessary. According to the third aspect of the present invention, the RAM is divided into a plurality of blocks,
By sequentially copying the ROM data and checking only the data of the last copied block, the entire area of the ROM and RAM can be inspected, so that the test time can be shortened. Moreover, since the ROM data is used as the test data, the data for the RAM test becomes unnecessary.

[0012]

5 to 15 are block diagrams illustrating an electric circuit for performing a memory test according to the present invention. In these figures, similar elements are designated by the same reference numerals. Common to these figures, on the circuit board 11,
A ROM block 12 and a RAM block 13 to be tested and a control circuit 14 are provided, and the ROM block 1
2 and the RAM block 13 and the control circuit 14 communicate with each other via a data / address bus provided on the circuit board 11. The control circuit 14 includes the ROM block 2 and the RAM.
A circuit for reading and writing to block 3,
For example, a CPU, a check circuit 15, and an arithmetic circuit 1
6 and.

Hereinafter, how an embodiment of the memory testing method according to the present invention is executed will be described with reference to FIGS. First, as shown in FIG. 5, the control circuit 14 sends a ROM control signal meaning a read instruction to the ROM block 12.
At the same time, the RAM control signal indicating a write instruction is sent to the RAM block 13. In this way, RO
The data stored in the M block 12 is read, this data is transmitted to the RAM block 13 via the data / address bus, and is written in the RAM block 13.

Next, as shown in FIG. 6, the control circuit 14
Sends a RAM control signal, which means a read instruction, to the RAM block 13. In this way, the RAM block 1
The data is read from the data No. 3 and supplied to the arithmetic circuit 16 of the control circuit 14 via the data / address bus. The calculation circuit 16 calculates the data according to a certain rule such as a checksum, and supplies the calculation result to the check circuit 15. The check circuit 15 collates the correct value calculated in advance. As a result, RO
The normality of the M block 12 and the RAM block 13 is confirmed.

The manner of executing another embodiment of the memory testing method according to the present invention will be described with reference to FIGS. First, as shown in FIG. 7, the control circuit 14 sends a ROM control signal meaning a read instruction to the ROM block 12.
At the same time, the RAM control signal indicating a write instruction is sent to the RAM block 13. In this way, RO
The data stored in the M block 12 is read, the data is transmitted to the RAM block 13 via the data / address bus, and the memory area of the RAM block 13 is written into the block 1 out of three.

Next, as shown in FIG. 8, the control circuit 14
Is an instruction to send a ROM control signal, which means an instruction to read data that has been subjected to a predetermined operation, such as inverted data, to the ROM block 12, and at the same time, to write to a block 2 of the memory area of the RAM block 13 divided into three. A RAM control signal that means is sent to the RAM block 13.
In this way, the operation data is read from the ROM block 12, the operation data is transmitted to the RAM block 13 via the data / address bus, and is written in the block 2 in the memory area of the RAM block 13.

Next, as shown in FIG. 9, the control circuit 14
Is a predetermined operation, for example, OR, on the data respectively written in the block 1 and the block 2 of the RAM block 13.
A RAM control signal is read from the calculation data resulting from the calculation, and a RAM control signal is sent to the RAM block 13, which indicates that the memory area of the RAM block 13 is divided into three. In this way, the operation data is read from the RAM block 12, the operation data is transmitted to the RAM block 13 via the data / address bus, and the RAM is
Write to block 3 in the memory area of block 13.

Next, as shown in FIG. 10, the control circuit 14
Sends a RAM control signal to the RAM block 13, which means an instruction to read the block 1. In this way, RA
The data is read from the block 1 of the M block 13 and supplied to the arithmetic circuit 16 of the control circuit 14 via the data / address bus. The calculation circuit 16 calculates the data according to a certain rule such as a checksum, and supplies the calculation result to the check circuit 15. The check circuit 15 collates the correct value calculated in advance.

Next, as shown in FIG. 11, the control circuit 14
Sends a RAM control signal to the RAM block 13, which means an instruction to read the block 3. In this way, RA
The data is read from the block 3 of the M block 13 and supplied to the check circuit 15 of the control circuit 14 via the data / address bus. In the check circuit 15,
For example, the calculation result such that all the data are “1” is compared with the expected value. As a result, the normality of the block 3 of the RAM block 13 and the blocks 1 and 2 which are the copy sources of the data in the block 3 are confirmed.

The manner of executing still another embodiment of the memory testing method according to the present invention will be described with reference to FIGS. First, as shown in FIG.
Indicates that a ROM control signal indicating a read instruction is sent to the ROM block 12, and at the same time, R indicating a write instruction.
The AM control signal is sent to the RAM block 13. In this way, the data stored in the ROM block 12 is read and this data is transferred to the RA via the data / address bus.
The data is transmitted to the M block 13 and is written in the block 1 of the n divided memory areas of the RAM block 13 (n is
2 or more natural number). That is, the data in the ROM block 12 is copied to the block 1 in the RAM block 13.

Next, as shown in FIG. 13, the control circuit 14
Reads data from the block 1 of the RAM block 13 and sends a RAM control signal, which is an instruction to write to the block 2, to the RAM block 13 to copy the data of the block 1 to the block 2.

Next, as shown in FIG. 14, in the same manner as described above with reference to FIG.
Data of a certain block is copied to the next block of the RAM block 13, and this is copied to the RAM block 13
Continue until all blocks are filled with data.

Next, as shown in FIG. 15, the control circuit 14
Sends a RAM control signal to the RAM block 13, which means an instruction to read the last block n of the RAM block 13. In this way, the data is read from the block n of the RAM block 13 and supplied to the arithmetic circuit 16 of the control circuit 14 via the data / address bus. In the check circuit 15, the calculation circuit 16 calculates the data according to a certain rule such as a checksum, and supplies the calculation result to the check circuit 15. The check circuit 15 collates the correct value calculated in advance. As a result, the ROM block 12 and the RAM
Check the normality of all blocks in block 13.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating an electric circuit that performs a conventional memory test.

FIG. 2 is a ROM block 2 in the circuit board 1 of FIG.
It is a block diagram explaining the conventional test of.

FIG. 3 is a RAM block 3 in the circuit board 1 of FIG.
It is a block diagram explaining the conventional test of.

4 is a RAM block 3 in the circuit board 1 of FIG.
It is a block diagram explaining the conventional test of.

FIG. 5 is a block diagram of an electric circuit that performs a memory test according to the present invention, and is a block diagram illustrating an embodiment of the memory test according to the present invention.

FIG. 6 is a block diagram of an electric circuit that performs a memory test according to the present invention, and is a block diagram illustrating an embodiment of the memory test according to the present invention.

FIG. 7 is a block diagram of an electric circuit that performs a memory test according to the present invention, and is a block diagram illustrating another embodiment of the memory test according to the present invention.

FIG. 8 is a block diagram of an electric circuit that performs a memory test according to the present invention, and is a block diagram illustrating another embodiment of the memory test according to the present invention.

FIG. 9 is a block diagram of an electric circuit that performs a memory test according to the present invention, and is a block diagram illustrating another embodiment of the memory test according to the present invention.

FIG. 10 is a block diagram of an electric circuit that performs a memory test according to the present invention, and is a block diagram illustrating another embodiment of the memory test according to the present invention.

FIG. 11 is a block diagram of an electric circuit that performs a memory test according to the present invention, and is a block diagram illustrating another embodiment of the memory test according to the present invention.

FIG. 12 is a block diagram of an electric circuit that performs a memory test according to the present invention, and is a block diagram illustrating still another embodiment of the memory test according to the present invention.

FIG. 13 is a block diagram of an electric circuit that performs a memory test according to the present invention, and is a block diagram illustrating still another embodiment of the memory test according to the present invention.

FIG. 14 is a block diagram of an electric circuit for performing a memory test according to the present invention, and is a block diagram illustrating still another embodiment of the memory test according to the present invention.

FIG. 15 is a block diagram of an electric circuit for performing a memory test according to the present invention, which is a block diagram illustrating still another embodiment of the memory test according to the present invention.

[Explanation of symbols]

1, 11 circuit board 2,12 ROM block 3, 13 RAM block 4, 14 Control circuit 5,15 check circuit 6, 16 arithmetic circuit 7 Test data storage

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 2G132 AA08 AA09 AC03 AD06 AK07                       AK13 AL09                 5B018 GA03 JA01 JA12 JA22 MA23                       NA01 NA04 QA13                 5L106 AA07 DD22 DD23

Claims (3)

[Claims] 1. A memory test method for testing the ROM and RAM in an electric circuit equipped with the ROM and RAM, the step of reading data from the ROM, the step of writing the data read from the ROM to the RAM, Reading the data written in the RAM, and the RO based on the data read from the RAM
And a step of confirming the operation of the M and the RAM. 2. A memory test method for testing the ROM and RAM in an electric circuit equipped with the ROM and RAM, the step of reading data from the ROM, the data read from the ROM being stored in a memory area of the RAM. Writing into a first block of the two blocks, writing operation data obtained by performing a predetermined operation on the data read from the ROM into a second block of the memory area of the RAM, Reading the data written in these blocks from the first and second blocks; and calculating data obtained by performing a predetermined operation on the data read from the first and second blocks of the RAM, and storing the calculated data in the memory of the RAM. Writing to the third block of the area, and writing to the first block of the RAM Reading the embedded data; confirming the operation of the ROM based on the data read from the first block of the RAM; and reading the data written to the third block of the RAM. And a step of confirming the operation of the RAM based on the data read from the third block of the RAM. 3. A memory test method for testing the ROM and RAM in an electric circuit equipped with the ROM and RAM, the step of reading data from the ROM, and the data read from the ROM in a plurality of memory areas of the RAM. writing to a first block of the n blocks, reading data from a first block of the RAM, and writing data read from a first block of the RAM to a second block of the RAM Similarly to the step and the step of writing to the second block of the RAM, the data read from a certain block of the RAM is sequentially written to the next block of the RAM,
Continuing until data is written in the last nth block of the RAM, reading data written in the nth block of the RAM, based on data read from the nth block of the RAM And a step of confirming the operation of the ROM and the RAM.