CN117272922A

CN117272922A - Chip failure analysis method, chip design method, device, equipment and medium

Info

Publication number: CN117272922A
Application number: CN202311197359.8A
Authority: CN
Inventors: 张亚光; 薛明达
Original assignee: Chengdu Haiguang Microelectronics Technology Co Ltd
Current assignee: Chengdu Haiguang Microelectronics Technology Co Ltd
Priority date: 2023-09-15
Filing date: 2023-09-15
Publication date: 2023-12-22

Abstract

The embodiment of the application provides a failure analysis method, a chip design method, a device, equipment and a medium for a chip, wherein the failure analysis method comprises the following steps: obtaining a local failure analysis result of a chip, wherein the local failure analysis result comprises a local failure position of the chip with failure abnormality and a process reason corresponding to the failure abnormality of the local failure position; determining a suspected failure position of the chip according to the local failure position; simulating a process reason at the suspected failure position; checking whether failure abnormality occurs after the suspected failure position simulates a process reason, and obtaining a checking report; and generating a failure analysis result of the chip according to the inspection report. According to the embodiment of the application, the coverage of failure analysis on the chip can be improved, more comprehensive direction and evidence are provided for the improvement of the chip in the production, manufacture and design links, and a basis is provided for improving the yield of the chip and reducing the probability of failure abnormality of the chip.

Description

Chip failure analysis method, chip design method, device, equipment and medium

Technical Field

The embodiment of the application relates to the technical field of chips, in particular to a failure analysis method of a chip, a chip design method, a device, equipment and a medium.

Background

A Chip such as a System On Chip (SOC) generally has Failure anomalies such as short circuits, circuit breaks, and functional failures, and therefore, failure Analysis (FA) of the Chip is required. However, failure analysis is currently directed to failure anomalies local to the chip, which results in failure analysis with relatively low coverage on the chip. Therefore, how to provide a failure analysis scheme for a chip to improve coverage of failure analysis on the chip becomes a technical problem to be solved by those skilled in the art.

Disclosure of Invention

In view of this, embodiments of the present application provide a chip failure analysis method, a chip design method, a device, equipment, and a medium, so as to improve coverage of failure analysis on a chip; furthermore, the embodiment of the application can perform chip inspection in the chip design stage based on failure analysis, so that failure abnormality is avoided by design modification in advance in the chip design stage.

In order to achieve the above purpose, the embodiments of the present application provide the following technical solutions.

In a first aspect, an embodiment of the present application provides a failure analysis method for a chip, including:

obtaining a local failure analysis result of a chip, wherein the local failure analysis result comprises a local failure position of the chip with failure abnormality and a process reason corresponding to the failure abnormality of the local failure position;

Determining a suspected failure position of the chip according to the local failure position, wherein the suspected failure position is a chip position suspected of failure abnormality due to process reasons;

simulating a process reason at the suspected failure position;

checking whether failure abnormality occurs after the suspected failure position simulates a process reason, and obtaining a checking report;

and generating a failure analysis result of the chip according to the inspection report.

In a second aspect, an embodiment of the present application provides a chip design method, including:

acquiring a staged design result of the chip;

invoking a chip checking tool, wherein the chip checking tool records a failure analysis result of a chip, and the failure analysis result indicates the position of the chip with abnormal failure risk and a corresponding process reason; wherein the failure analysis result is obtained according to the failure analysis method of the chip described in the first aspect;

checking whether the periodic design result is abnormal in failure at the chip position by using a chip checking tool;

if so, modifying the staged design result according to the process reason corresponding to the chip position until the modified staged design result does not generate failure abnormality at the chip position.

In a third aspect, an embodiment of the present application provides a failure analysis apparatus for a chip, including:

the local result acquisition module is used for acquiring a local failure analysis result of the chip, wherein the local failure analysis result comprises a local failure position of the chip with failure abnormality and a process reason corresponding to the failure abnormality of the local failure position;

the suspected position determining module is used for determining the suspected failure position of the chip according to the local failure position, wherein the suspected failure position is the position of the chip suspected of having failure abnormality due to the process;

the simulation module is used for simulating the process reason at the suspected failure position;

the checking module is used for checking whether failure abnormality occurs after the suspected failure position simulates the process reason, and obtaining a checking report;

and the result generation module is used for generating a failure analysis result of the chip according to the inspection report.

In a fourth aspect, embodiments of the present application provide a chip design apparatus, including:

the staged result obtaining module is used for obtaining staged design results of the chip;

the calling module is used for calling a chip checking tool, wherein the chip checking tool records a failure analysis result of a chip, and the failure analysis result indicates the position of the chip with abnormal failure risk and the corresponding technological reason; wherein the failure analysis result is obtained according to the failure analysis method of the chip described in the first aspect;

The design checking module is used for checking whether the periodic design result is abnormal in failure at the chip position by using a chip checking tool;

and the design modification module is used for modifying the staged design result according to the process reason corresponding to the chip position if the judgment result of the design checking module is yes, until the modified staged design result does not generate failure abnormality at the chip position.

In a fifth aspect, embodiments of the present application provide a computer device, including at least one memory and at least one processor, where the memory stores one or more computer-executable instructions, and the processor invokes the one or more computer-executable instructions to perform a failure analysis method of a chip as described in the first aspect, or a chip design method as described in the second aspect.

In a sixth aspect, embodiments of the present application provide a storage medium storing one or more computer-executable instructions that, when executed, implement a method for failure analysis of a chip as described in the first aspect, or a method for chip design as described in the second aspect.

The chip failure analysis method provided by the embodiment of the application can acquire the local failure analysis result of the chip, wherein the local failure analysis result comprises the local failure position of the chip with failure abnormality and the process reason corresponding to the failure abnormality of the local failure position; therefore, according to the local failure position, determining the suspected failure position of the chip, wherein the suspected failure position is the position of the chip suspected of having failure abnormality due to the process; that is, according to the local failure analysis result of the chip, the embodiment of the application can determine a wider suspected failure position in the chip, where failure abnormality may occur due to process reasons, and the suspected failure position is used as a suspected object in the chip, where failure abnormality may occur. In order to check whether the suspected failure position has failure abnormality due to the process reason, the embodiment of the application can simulate the process reason at the suspected failure position and check whether failure abnormality occurs after the suspected failure position simulates the process reason, so as to obtain a check report; if the suspected failure position simulates the process reason and then fails to be abnormal, the risk that the suspected failure position fails to be abnormal due to the process reason is indicated; furthermore, according to the embodiment of the application, the failure analysis result of the chip can be generated according to the inspection report, so that the failure analysis result of the chip can cover the suspected failure position with failure abnormality risk and the process reason of the suspected failure position.

Therefore, the embodiment of the application can promote the coverage of failure analysis on the chip by comprehensively and detailed investigation on the local failure position and the process reason of the failure abnormality of the chip actually and the suspected failure position and the process reason of the failure abnormality risk of the chip, provide more comprehensive direction and evidence for the improvement of the chip in the production, manufacture and design links, and provide a basis for improving the yield of the chip and reducing the probability of the failure abnormality of the chip. Furthermore, the embodiment of the application can perform chip inspection in the chip design stage based on failure analysis, so that failure abnormality is avoided by design modification in advance in the chip design stage.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present application, and that other drawings may be obtained according to the provided drawings without inventive effort to a person skilled in the art.

Fig. 1 is a flowchart of a failure analysis method of a chip according to an embodiment of the present application.

Fig. 2A is an exemplary diagram of a short circuit occurring between metal layers.

Fig. 2B is an exemplary diagram of a short circuit occurring between metal patterns.

Fig. 3A is an exemplary diagram of chip layout inspection using an LVS tool.

Fig. 3B is an exemplary diagram of chip layout inspection using DRC tools.

Fig. 4A is an exemplary diagram of inspecting a reduced chip layout using an LVS tool.

Fig. 4B is an exemplary diagram of a simplified chip layout checked using a DRC tool.

Fig. 5 is a diagram showing a comparative example of the simulation result.

Fig. 6 is an exemplary diagram of the results of eFA layout inspection, simulation results, and test results matching each other.

Fig. 7A is a diagram of current and voltage examples of a chip pin short.

Fig. 7B is a graph illustrating current and voltage after cutting out the short circuit area from the chip pins.

Fig. 8 is a phase example diagram of failure analysis of a chip according to an embodiment of the present application.

Fig. 9 is a flowchart of a chip design method according to an embodiment of the present application.

Fig. 10 is a block diagram of a failure analysis apparatus for a chip according to an embodiment of the present application.

Fig. 11 is a block diagram of a chip design apparatus according to an embodiment of the present application.

Fig. 12 is a block diagram of a computing device provided by an embodiment of the present application.

Detailed Description

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.

In chip manufacture, a wafer can be thinned and cut to form a plurality of crystal grains, and the crystal grains can be packaged into chips; after the chip is obtained, the chip needs to be tested to distinguish good products from defective products; good products can be marketed after meeting certain reliability standards, and defective products are scrapped. In order to ensure the quality and reliability of the chip, the yield needs to be continuously improved, so that failure analysis is required to be performed on the tested defective products or the chips with failure abnormality, and the positions and reasons of the failure abnormality of the chips are found, thereby providing directions and evidences for the production, manufacture and design improvement of the chips. Therefore, the method has important significance in failure analysis of the chip.

It should be noted that, failure analysis refers to performing electrical analysis, failure positioning, physical dissection, analysis and the like on a failure sample with failure abnormality by using various electrical, physical, chemical and other devices and methods, and finding out the position and reason of the failure abnormality, thereby providing direction and evidence for improvement of production and design.

In the chip field, the reason for the failure abnormality of the chip may be a process problem existing in the actual process engineering of the chip (for example, the failure abnormality of the chip is caused due to the process problem of the chip), so the failure analysis of the chip may be: locating the failure position of the chip with failure abnormality (for example, locating the position of the chip with failure abnormality such as short circuit, circuit breaking, functional failure and the like), and analyzing the process reason (the reason of the chip process problem is simply called as the process reason) corresponding to the failure abnormality of the failure position; further, verification of the failure location and the corresponding process cause (e.g., verification of whether the failure location is abnormal due to the analyzed process cause) is performed, and in the case of verification passing, direction and evidence are provided for improvement of chip production and design based on the failure analysis result (e.g., the failure location and the corresponding process cause).

A chip may actually have complex failure anomalies (for example, for a chip with a large area, there may be a large number of failure anomalies in the chip, and multiple types of failure anomalies), so it is desirable to perform a more detailed and comprehensive failure analysis on the chip for each type of failure anomaly. For example, for each type of failure abnormality, determining the failure position in the chip where the failure abnormality may occur and the process reason for the failure abnormality occurring in the failure position, so that the failure analysis can cover the chip area more comprehensively; and further, through a more detailed and comprehensive failure analysis result of each type of failure abnormality, a direction and evidence are provided for the improvement of the production, the manufacture and the design of the chip, and the risk of the failure abnormality of the chip is reduced.

However, a technology for performing more detailed and comprehensive failure analysis on a chip is lacking at present, and the current failure analysis mode mainly performs failure analysis on a local failure abnormality of the chip (for example, performs failure analysis on a local failure abnormality of the chip, and defines a position and a reason of the local failure abnormality of the chip), which results in that the coverage area of the failure analysis on the chip is relatively low, and the relatively comprehensive failure analysis on the chip cannot be performed.

Based on the above, the embodiment of the application provides a novel failure analysis scheme of the chip, based on the failure analysis result of the chip part, the related analysis of the program or the script is combined, and the failure analysis of the chip part is extended to the more comprehensive failure analysis of the chip, so that the more detailed and comprehensive failure analysis is carried out on the chip, and the coverage of the failure analysis on the chip is improved.

As an optional implementation, fig. 1 illustrates an optional flowchart of a method for failure analysis of a chip provided in an embodiment of the present application, where the method flowchart may be implemented by executing a computer device, and the computer device may be a computer device running a failure analysis program, and the embodiment of the present application is not limited to the form of a terminal device or a server device. Referring to fig. 1, the method flow may include the following steps.

In step S110, a local failure analysis result of the chip is obtained, where the local failure analysis result includes a local failure position where a failure abnormality occurs in the chip, and a process reason corresponding to the failure abnormality occurs in the local failure position.

Aiming at defective products or chips with abnormal failures, the embodiment of the application can perform preliminary failure analysis on the chips, and the preliminary failure analysis is performed on the local failure anomalies of the chips, so that the embodiment of the application can acquire the local failure analysis results of the chips. The analysis result of the local failure of the chip can comprise the local failure position of the failure abnormality of the chip and the process reason corresponding to the failure abnormality of the local failure position. For example, when a failure abnormality exists in a chip, the embodiment of the application may perform preliminary failure analysis, so as to determine a local failure position where the failure abnormality occurs in the chip and a process reason for the failure abnormality occurring in the local failure position.

In alternative implementations, embodiments of the present application may be deployed from multiple dimensions in performing a preliminary failure analysis on a chip. For example, the local failure position of the chip with failure abnormality is located by using experimental equipment, and then yield data of the chip is analyzed, modeling analysis is performed on the failure abnormality, and analysis is performed on the manufacturing equipment related to chip manufacturing, so that the process reason corresponding to the failure abnormality at the local failure position of the chip is obtained through analysis.

In possible implementation, at least one type of failure abnormality (one type of failure abnormality or multiple types of failure abnormalities) may exist in the chip, and the embodiment of the present application may perform preliminary failure analysis on the chip aiming at various types of failure abnormalities, so as to determine local failure positions where various types of failure abnormalities occur in the chip, and process reasons corresponding to the local failure positions. For example, the results of the local failure analysis of the chip may indicate at least one type of failure anomaly of the chip, as well as the local failure location and corresponding process cause of each type of failure anomaly on the chip.

The preliminary failure analysis aims at locating the failure position (namely the local failure position) of the chip with the failure abnormality and the process problem reason (namely the process reason) of the failure abnormality at the local failure position, and obtaining the local failure analysis result of the chip, thereby providing a basis for the subsequent detailed and comprehensive failure analysis of the chip; therefore, the specific implementation means of the preliminary failure analysis are not limited, and any mode capable of positioning the local failure position and the process reason aiming at the failure abnormality of the chip is applicable.

In an alternative implementation, the local failure location where the failure exception occurs to the chip may include: the position of a local physical layer with abnormal failure of the chip; the process reason for the local failure location may be a process reason for failure abnormality of the local physical location of the chip. That is, the result of the local failure analysis of the chip may indicate the local failure location where the failure abnormality occurs from the perspective of the physical layer of the chip; and, the process cause of the local failure location is indicated from the perspective of the process defect of the physical layer.

In alternative implementation examples, the physical layer locations may be locations between physical layers or locations within the physical layer. For example, the physical layer of the chip may be a metal layer of the chip; accordingly, the physical layer location may be a location between metal layers, or may be a location within a metal layer (such as a location between metal patterns within a metal layer, or a location of a metal pattern within a metal layer). Based on this, in an alternative implementation, the failure abnormality of the chip may be a failure abnormality between metal layers, a failure abnormality between metal patterns of the metal layers, or a failure abnormality inside the metal patterns of the metal layers, etc.; accordingly, the local physical layer location where the failure exception occurs may include any one of the following: positions between the partial metal layers, positions between the partial metal patterns, positions of the partial metal patterns, and the like.

It should be noted that, the positions between the metal layers of the chip relate to a plurality of metal layers of the chip, so that the failure abnormality occurring at the positions between the metal layers belongs to the failure abnormality occurring in the vertical space of the chip, that is, the chip space corresponding to the failure abnormality is the vertical space; the internal conditions of the metal layers are related to the metal patterns of the chip or the inside of the metal patterns, so that the failure abnormality between the metal patterns or the inside of the metal patterns belongs to the failure abnormality generated in the horizontal space of the chip, namely the chip space corresponding to the failure abnormality is the horizontal space.

For easy understanding, taking failure exception of short circuit of the chip as an example, through preliminary failure analysis, the embodiment of the application can obtain the position of the local physical layer of the short circuit of the chip, and obtain the process reason of the short circuit of the position of the local physical layer.

For example, in the vertical space of the chip, short circuits occur between metal layers due to process problems, and through preliminary failure analysis, the embodiments of the present application can obtain the positions between the local metal layers where the short circuits occur, and the process reasons for the short circuits at the positions between the local metal layers.

In one example, assuming that a short circuit occurs between metal layers due to a process defect of insufficient thickness of an isolation layer between the metal layers in a vertical space of a chip, a position between partial metal layers where the short circuit occurs and a process reason for the short circuit at the position between the partial metal layers can be obtained through preliminary failure analysis, which is that: the thickness of the isolation layer between the partial metal layers is insufficient. By way of example, fig. 2A illustrates an exemplary diagram of a short circuit occurring between metal layers, and as shown in fig. 2A, a short circuit occurs between metal layer 210 and metal layer 220 in the vertical space of the chip, and then, through preliminary failure analysis, the position between the local metal layers where the short circuit occurs can be located in the vertical space of the chip: a location between metal layer 210 and metal layer 220; meanwhile, the process reason that the short circuit occurs at the position between the partial metal layers is obtained: the thickness of the isolation layer between the metal layer 210 and the metal layer 220 is insufficient.

For another example, in the horizontal space of the chip, short circuits occur between the metal patterns due to the process problem, and through the preliminary failure analysis, the embodiment of the application can obtain the positions between the local metal patterns where the short circuits occur and the process reasons for the short circuits at the positions between the local metal patterns.

In one example, assuming that a short circuit occurs between metal patterns due to a process defect in which the space between metal patterns is small in the horizontal space of the chip, the positions between the partial metal patterns where the short circuit occurs and the process reason for the short circuit at the positions between the partial metal patterns can be obtained through preliminary failure analysis, which is that: the spacing between the partial metal patterns is small. By way of example, fig. 2B illustrates an exemplary diagram of a short circuit occurring between metal patterns, and as illustrated in fig. 2B, a short circuit occurs between metal pattern 201 and metal pattern 202 in a horizontal space of a chip, and then, through preliminary failure analysis, a position between local metal patterns where a short circuit occurs may be located in the horizontal space of the chip: a position between the metal pattern 201 and the metal pattern 202; meanwhile, the process reason that the short circuit occurs at the position between the local metal patterns is obtained: the space between the metal pattern 201 and the metal pattern 202 is small.

Taking the failure abnormality of the broken circuit (namely open circuit) of the chip as an example, the embodiment of the application can obtain the position of the local physical layer of the broken circuit of the chip through preliminary failure analysis, and obtain the process reason of the broken circuit of the position of the local physical layer. For example, in the horizontal space of the chip, the metal patterns are broken due to the technical reasons such as smaller spacing of the metal patterns; correspondingly, through preliminary failure analysis, the embodiment of the application can position the position of the local metal pattern with the open circuit in the horizontal space of the chip, and meanwhile, the process reason for obtaining the short circuit at the position of the local metal pattern is that the space between the metal patterns in the horizontal space is smaller.

In step S120, a suspected failure location of the chip is determined according to the local failure location.

In addition, the embodiment of the application can determine the suspected failure position in the chip, which is likely to generate failure abnormality, according to the local failure position after the local failure analysis result of the chip is obtained, so as to automatically find the suspected chip position in the chip layout, which is likely to generate failure abnormality. It should be explained that, the local failure location is a location where a failure abnormality of the chip is actually generated by the positioning of the preliminary failure analysis, and the suspected failure location may be regarded as a chip location where a failure abnormality may exist due to a process reason (i.e., the suspected failure location is a suspected object where a failure abnormality may occur) suspected in the embodiment of the present application; for example, the suspected failure location may have failure abnormality due to the process reason, or may not have failure abnormality due to the process reason, and thus, the investigation needs to be performed later.

In an optional implementation, according to the position attribute of the local failure position, the embodiment of the application may search the chip for a position corresponding to the position attribute of the local failure position as a suspected failure position of the chip.

Alternatively, the local failure location may be a local physical layer location where a failure exception occurs to the chip, for example, any one of the following: positions between the partial metal layers, positions between the partial metal patterns, positions of the partial metal patterns, and the like. Accordingly, the suspected failure location may be a suspected physical layer location in the chip where failure anomalies are suspected to occur, for example any of the following: positions between the suspected metal layers, positions between the suspected metal patterns, positions of the suspected metal patterns, and the like.

In an alternative implementation, to facilitate searching for a suspected failure location, the embodiment of the present application may set the location attribute of the local failure location to: chip space corresponding to the location of the local physical layer, and physical layer type of the local physical layer. Therefore, in an optional implementation, the embodiment of the application may search, based on the chip space corresponding to the local physical layer, a position corresponding to the physical layer type of the local physical layer in the chip, so as to obtain a suspected physical layer position in the chip, where failure abnormality is suspected to occur. Alternatively, the physical layer types may be the same or similar, respectively (the standards for physical layer type approximation may be set according to the actual situation).

In one implementation example, taking the example of insufficient thickness of the isolation layer between the local metal layers, resulting in a short circuit between the local metal layers (e.g., as shown in the example of fig. 2A), the local failure location may be a location between the local metal layers where the short circuit occurs, and the location attribute may indicate a vertical space of the chip, and a type of the local metal layer; therefore, according to the position attribute of the position between the local metal layers, the embodiment of the application can search the suspected metal layers corresponding to the types of the local metal layers (for example, search the suspected metal layers which are the same as or similar to the types of the local metal layers) in the vertical space of the chip, and the found positions between the suspected metal layers are used as the suspected physical layer positions. For example, when the local failure analysis result indicates that a short circuit occurs between two local metal layers, the embodiment of the application may search for two other metal layers corresponding to the type according to the type of the two local metal layers with the short circuit occurring between the metal layers in the vertical space of the chip, and consider the found positions between the two other metal layers as positions between suspected metal layers with the suspected possibility of occurring the short circuit.

In another implementation example, taking the example that the space between the local metal patterns is smaller, resulting in a short circuit between the local metal patterns (for example, as shown in the example of fig. 2B), the local failure location may be a location between the local metal patterns where the short circuit occurs, and the location attribute may indicate a horizontal space of the chip, and a type of the local metal patterns; therefore, according to the position attribute of the position between the local metal patterns, the embodiment of the application can search the suspected metal patterns corresponding to the types of the local metal patterns (for example, search the suspected metal patterns which are the same as or similar to the types of the local metal patterns) in the horizontal space of the chip, and the found positions between the suspected metal patterns are used as the suspected physical layer positions. For example, when the local failure analysis result indicates that a short circuit occurs between two local metal patterns, the embodiment of the application may search for other two metal patterns corresponding to the type according to the type of the two local metal patterns with the short circuit occurring between the metal patterns in the horizontal space of the chip, and consider the found position between the other two metal patterns as the position between the suspected metal patterns with the suspected possibility of occurring the short circuit.

In still another implementation example, taking an example that the space between the local metal patterns is smaller, so that a circuit break occurs in the local metal patterns, the embodiment of the application can find a suspected metal pattern in which the circuit break is suspected to occur according to the type of the local metal pattern in which the circuit break occurs in the horizontal space of the chip, so as to obtain the position of the suspected physical layer.

The foregoing describes the failure abnormality of the chip by taking the examples of the occurrence of a short circuit between the metal layers, the occurrence of a short circuit between the metal patterns, and the occurrence of a short circuit inside the metal patterns; in actual cases, other types of failure anomalies may occur between metal layers, between metal patterns, inside metal patterns, without being limited to the examples described above. That is, the positions of the failure anomalies of the chip may be between metal layers, between metal patterns, or inside the metal patterns, and the types of the failure anomalies of the positions are not limited, and may be determined according to the specific situation.

In step S130, the process cause is simulated at the suspected failure location of the chip.

In step S140, whether a failure abnormality occurs after the suspected failure location simulation process cause is checked, and a check report is obtained.

After determining the suspected failure position of the chip, in order to perform more detailed and comprehensive failure analysis on the chip, the embodiment of the application can simulate the process reason at the suspected failure position and check whether failure abnormality occurs at the suspected failure position after simulating the process reason; if the suspected failure position is abnormal after the process reason is simulated, the suspected failure position is indicated to have the risk of abnormal failure caused by the process reason, and the suspected failure position and the simulated process reason of the suspected failure position can be written into the failure analysis result of the chip, so that the process defect possibly abnormal failure is prevented from being introduced into the suspected failure position during the production, the manufacture and the design of the chip.

That is, the meaning of the simulation of the process reason at the suspected failure position of the chip in the embodiment of the application is that: and comprehensively checking the position (such as a suspected failure position) where failure abnormality possibly occurs in the chip, and under the condition that the suspected failure position is at risk of failure abnormality caused by a process reason, indicating the risk through failure analysis results, so that the risk can be avoided in links of production, manufacture and design of the chip. According to the embodiment of the application, the local failure position and the process reason of the failure abnormality of the chip actually occur and the suspected failure position and the process reason of the failure abnormality risk of the chip are comprehensively and detailed checked, so that the coverage surface of failure analysis on the chip can be improved, more comprehensive direction and evidence are provided for the improvement of the chip in the production, manufacture and design links, and a basis is provided for improving the yield of the chip and reducing the probability of failure abnormality of the chip.

In an optional implementation, in the code file of the chip inspection tool, the inspection rule of the suspected failure location may be modified to simulate a design corresponding to the process reason at the suspected failure location, so as to simulate the process reason at the suspected failure location. Alternatively, a chip inspection tool may be used to perform layout inspection on the chip. Furthermore, chip layout inspection can be performed through a chip inspection tool so as to inspect whether failure abnormality occurs in the suspected failure position in the chip layout inspection process, and an inspection report is obtained.

The chip inspection tool for inspecting the chip layout is provided with a code file for executing the layout inspection, wherein the code file expresses inspection rules (such as inspection codes, rule critical values of the chip layout position and the like) for inspecting the chip layout; the inspection code of the code file may describe an inspection location (e.g., a metal layer to be inspected, etc.) of the chip and inspection logic of the inspection location (e.g., whether the metal layers are connected, whether the pitch of the metal layers are too close, etc.). Therefore, in the code file of the chip inspection tool, according to the process reason (for example, the process reason corresponding to the local failure position according to which the suspected failure position is found) to be simulated in the suspected failure position, the inspection rule of the suspected failure position is modified, so that the design corresponding to the process reason is simulated in the suspected failure position, and the process reason is simulated in the suspected failure position.

In one example, the chip inspection tool that performs the layout inspection may be, for example, LVS (Layout Verse Schematic) tool, DRC (Design Rule Check, design rule inspection) tool, ERC (Electrical Rule Checking, electrical rule inspection) tool, ESD (Electro Static Discharge ) tool, or the like. It should be noted that the LVS tool is used for performing consistency verification on the connection relationship and the schematic diagram of the devices in the chip layout, and performing consistency verification on the attribute and the schematic diagram of the devices in the chip layout. The DRC tool is used for checking whether the pattern spacing, the size, the overlapping and the like in the chip layout meet the process requirements, and can perform checking on the geometric patterns of the chip layout so as to ensure that layout data can be produced and obtain higher yield in the given integrated circuit process technology. The ERC tool is used to check whether there is an electrical connection problem in the chip layout or not.

In an optional implementation, the embodiment of the application may simulate the process reason at the suspected failure position by adding an inspection code of the suspected failure position to a code file of the chip inspection tool without changing an original design of the suspected failure position, and expressing that the suspected failure position has a design corresponding to the process reason.

In an implementation example, taking the suspected failure position as the position between the suspected metal layers as an example, in the code file of the chip inspection tool, the embodiment of the application can newly add the inspection codes between the suspected metal layers, and the newly added inspection codes express that the suspected metal layers have a connection relationship corresponding to the process reason, so that the position between the suspected metal layers is simulated. For example, assuming that the local failure analysis result indicates that the thickness of the isolation layer between the local metal layers is insufficient, so that a short circuit exists at a position between the local metal layers, after finding a position between the suspected metal layers where the short circuit may occur, in the code file of the chip inspection tool, the inspection codes between the suspected metal layers may be newly added, and the newly added inspection codes express the connection relationship between the suspected metal layers with the connection layer, so as to implement the process reason of simulating the insufficient thickness of the isolation layer between the suspected metal layers.

For ease of understanding, assuming that the position between the suspected metal layers is the position between the metal layers M1 and M2 (i.e., a short circuit is suspected to occur between the metal layers M1 and M2 under the process defect of insufficient thickness of the isolation layer), if the original connection design of the metal layers M1 and M2 is that the metal layers M1 and M2 are connected through vias, for example, the metal layers M1 and M2 are connected through vias (Via), then in order to simulate the process defect of insufficient thickness of the isolation layer of the metal layers M1 and M2, in the code file of the chip inspection tool, the inspection code between the metal layers M1 and M2 may be newly added, and the newly added inspection code expresses that the metal layers M1 and M2 are connected through the connection layer. That is, the metal layer M1 and the metal layer M2 are originally connected through the Via (Via), and in this embodiment of the present application, on the basis of the original connection relationship, the inspection code is added, so that the metal layer M1 and the metal layer M2 have the connection relationship connected through the connection layer in addition to the connection relationship through the Via. In one example, the embodiment of the present application may add a check code to the code file of the LVS tool to add a connection relationship between the metal layer M1 and the metal layer M2 suspected of having a short circuit.

In another alternative implementation, if the suspected failure location is inside the metal layer, the embodiment of the present application may modify, according to the process reason, the rule critical value of the metal layer in the code file of the chip inspection tool, so as to simulate the process reason inside the metal layer. In one implementation example, the suspected failure positions are positions between the suspected metal patterns, or the positions of the suspected metal patterns are taken as an example, and since the suspected failure positions are dimensions of the suspected metal patterns (such as positions between the suspected metal patterns, or positions of a certain suspected metal pattern), the positions where failure abnormality is suspected to exist are the interiors of the metal layers, so that the embodiment of the application can simulate the process reasons by modifying the rule critical values of the metal layers where the suspected metal patterns are located in the code file of the chip inspection tool according to the process reasons.

For example, in the code file of the chip inspection tool, the rule critical values of the metal layers where the suspected metal patterns are located may be modified to implement the simulation of the process reasons at the positions between the suspected metal layers or the simulation of the process reasons at the positions of the suspected metal patterns. For example, if a short circuit is suspected between the metal patterns or if a circuit break is suspected in the metal patterns, a rule critical value related to a space (space) of the metal layer where the metal patterns are located can be modified, so that the internal space design of the metal layer is adjusted, and the process reason is simulated between the metal patterns in the metal layer or in a certain metal pattern.

The chip checking tools such as LVS, DRC and the like are provided with code files for checking the chip layout, and the code files are provided with checking codes, and the suspected failure position can be simulated for the process reason by adjusting and modifying the code files of the chip checking tools such as LVS, DRC and the like; and in the process of checking the chip layout, checking whether corresponding failure abnormality occurs after the suspected failure position simulates the process reason. Under this concept, the embodiment of the present application does not limit modification of the code file of the chip inspection tool such as LVS, DRC, etc. to implement the method of simulating the process reason at the suspected failure location, and the simulation method illustrated from the angles of the metal layer and the metal pattern is provided only as an optional example.

After simulating the process reason at the suspected failure position, the embodiment of the application can check whether the suspected failure position is abnormal or not to obtain a check report. The inspection report may indicate the simulated process reason for the suspected failure location and whether a failure anomaly occurred at the suspected failure location. In an alternative implementation, the embodiment of the application may use a chip inspection tool such as LVS, DRC, etc. to perform chip layout inspection after simulating the process reason at the suspected failure location, so as to inspect whether the suspected failure location is abnormal in failure, and obtain an inspection report. For example, after a connection layer is newly added between suspected metal layers suspected of being shorted, a chip layout inspection is performed to inspect whether or not a short circuit occurs between the suspected metal layers.

In an alternative implementation, the embodiment of the application may use a chip inspection tool such as LVS, DRC, etc. to perform chip layout inspection after simulating the process reason at the suspected failure location, and obtain the inspection report through a reporting tool of electronic design assistance software such as the Signoff tool. Signoff refers to an important concept in chip design and refers to a flag that completes all checks of the chip design successfully.

In a further implementation example, step S120 and step S130 may be implemented by a program or script, for example, by writing a related program or script, so that after the local failure analysis result of the chip is obtained, the local failure analysis result of the chip is input into the program or script, so as to automatically determine the suspected failure position of the chip through the program or script, and the code file of the chip inspection tool such as LVS, DRC, etc. is modified through the program or script, so as to simulate the process reason at the suspected failure position of the chip; further, chip layout inspection is performed by a chip inspection tool such as LVS or DRC to inspect whether failure abnormality occurs in the suspected failure position, and an inspection report is output by a Signoff tool.

It should be noted that, in the embodiment of the present application, based on preliminary failure analysis, a more comprehensive suspected failure position in a chip, where a failure abnormality risk may exist, is determined by using a program or a script, and a process reason is simulated at the suspected failure position, and then chip layout inspection is performed by using a chip inspection tool such as LVS, DRC, etc. to inspect whether the suspected failure position is abnormal after the process reason is simulated. Therefore, in the embodiment of the application, when the chip layout inspection tool such as the LVS and the DRC performs chip layout inspection, more comprehensive and detailed failure analysis can be performed, namely, whether the suspected failure position is abnormal or not can be comprehensively and detailed inspected under the condition that the process reason exists, the relation among the comprehensive and detailed suspected failure position, the process reason and the failure abnormality is obtained, and the coverage of the failure analysis on the chip is improved. Based on this, the chip layout inspection performed by the chip inspection tools such as LVS and DRC in the embodiment of the present application may also be referred to as eFA (electrical Failure Analysis ) layout inspection, and eFA may be understood as performing chip failure analysis by nondestructive means such as electrical analysis.

It should be further noted that, as an optional implementation, there may be multiple suspected failure positions under one type of failure anomaly, and for any type of failure anomaly, in the embodiment of the present application, in a code file of a chip inspection tool, inspection rules of each suspected failure position may be modified, so as to simulate a design corresponding to a process reason at each suspected failure position, and whether each suspected failure position has a failure anomaly is inspected respectively. That is, for any type of failure abnormality, when determining a plurality of suspected failure positions under the type of failure abnormality, based on each suspected failure position, the embodiment of the application may modify the inspection rule one by one in the code file of the chip inspection tool and inspect whether the failure abnormality occurs one by one.

In step S150, a failure analysis result of the chip is generated from the inspection report.

After checking whether the suspected failure position is abnormal, the embodiment of the application can obtain a checking report; the inspection report may indicate each suspected failure location, the process reason that each suspected failure location simulates, and whether each suspected failure location is abnormal. If the inspection report indicates that the suspected failure position is abnormal after the process reason is simulated, the risk of the suspected failure position being abnormal under the process problem corresponding to the process reason can be confirmed.

In an optional implementation, the embodiment of the application may form the failure analysis result of the chip according to the suspected failure position where the failure abnormality is indicated by the inspection report and the process reason simulated by the suspected failure position. That is, the failure analysis result of the chip may indicate the suspected failure location where the failure abnormality occurs and the process reason for simulating the suspected failure location, so as to avoid introducing the process defect where the failure abnormality occurs at the suspected failure location in the production, manufacturing and design links of the chip.

In another optional implementation, the embodiment of the application may combine the local failure analysis result of the chip and the suspected failure position of the failure abnormality indicated by the inspection report, and the process reason of the simulation of the suspected failure position, to generate the failure analysis result of the chip. That is, the failure analysis result of the chip can indicate the local failure position of the chip with failure abnormality, the process reason corresponding to the local failure position, the suspected failure position with failure abnormality in the inspection report, and the process reason simulated by the suspected failure position, thereby providing the failure analysis result combining the preliminary failure analysis and eFA layout inspection, and enabling the failure analysis result to be more comprehensive and detailed.

In a further optional implementation, in the case that the inspection report passes the accuracy verification and/or the rationality verification, the embodiment of the application may generate the failure analysis result of the chip according to the inspection report. For example, embodiments of the present application may verify the accuracy of an inspection report after the inspection report is obtained; in the case where the inspection report passes the accuracy verification, step S150 is executed again. For another example, embodiments of the present application may verify the rationality of an inspection report after the inspection report is obtained; in the case where the inspection report passes the rationality verification, step S150 is executed again. For another example, the embodiment of the application can verify the accuracy and the rationality of the inspection report after obtaining the inspection report; in the case where the inspection report passes the accuracy verification and the rationality verification, step S150 is executed again.

In alternative implementations, verifying the accuracy of the inspection report may be performed by testing, simulation, or the like, e.g., comparing the inspection report to test results and/or simulation results, thereby confirming that the inspection report passes accuracy verification if the inspection report matches the test results and/or simulation results. The inspection report is obtained through the eFA layout inspection process of chip inspection tools such as LVS, DRC and the like, and the inspection report can indicate suspected failure positions with failure abnormality and process reasons for simulating the suspected failure positions; based on the suspected failure position and the process reason of the failure abnormality indicated by the inspection report, whether the suspected failure position is corresponding to the failure abnormality or not can be verified from the angles of testing, simulation and the like under the condition that the process reason exists, and the accuracy of the inspection report is further verified from multiple dimensions. There are various ways to verify the accuracy of the inspection report, and the embodiments of the present application are not limited.

In an optional implementation, according to the suspected failure position of the failure exception indicated by the inspection report, the embodiment of the application may perform Failure Analysis (FA) processing on the chip to verify the rationality of the inspection report; for example, after the design corresponding to the elimination process reason is judged, whether the failure abnormality of the suspected failure position disappears is judged, so as to judge the rationality of the inspection report.

Therefore, the embodiment of the application can promote the coverage of failure analysis on the chip by comprehensively and detailed investigation on the local failure position and the process reason of the failure abnormality of the chip actually and the suspected failure position and the process reason of the failure abnormality risk of the chip, provide more comprehensive direction and evidence for the improvement of the chip in the production, manufacture and design links, and provide a basis for improving the yield of the chip and reducing the probability of the failure abnormality of the chip.

As an alternative implementation, after determining the suspected failure location of the chip, the suspected failure location of the chip may be a location between suspected metal layers in the vertical space of the chip. Aiming at the vertical space of a chip, the embodiment of the application can utilize the LVS tool to check the chip layout, so that the embodiment of the application can newly add check codes in the code file of the LVS tool, express the design corresponding to the technological reasons among the suspected metal layers through the newly added check codes, and check whether failure abnormality occurs among the suspected metal layers by utilizing the LVS tool to obtain a check report; for example, a new check code is added to the code file of the LVS tool to add a connection relationship between the suspected metal layers suspected of having a short circuit, and the LVS tool is used to check whether a short circuit occurs between the suspected metal layers.

By way of example, FIG. 3A illustrates an exemplary diagram of chip layout inspection using an LVS tool, as shown in FIG. 3A, with GDS (Graphic Data System, graphics System data) being a layout data file of a chip, the GDS may be inspected by the LVS tool to effect the layout inspection of the chip; the LVSDECK is a parameter configuration file of the LVS tool, and a code file of the LVS tool is recorded; the code file of the LVS tool can be modified by modifying the LVSDECK; therefore, the embodiment of the application can realize the new addition of the check code in the code file of the LVS tool by modifying the LVSDECK, and express the design corresponding to the technological reasons among the suspected metal layers through the new addition of the check code; furthermore, by using the LVS tool for modifying the LVSDECK to check the GDS, whether failure abnormality occurs after the design corresponding to the simulation process reason among the suspected metal layers is checked in the layout checking process of the chip.

As another alternative implementation, the suspected failure location of the chip may be a location between suspected metal patterns in the horizontal space of the chip, or a location of a suspected metal pattern, that is, the suspected failure location is located inside the metal layer. For the horizontal space of the chip, the embodiment of the application can utilize the DRC tool to check the chip layout, so that the embodiment of the application can modify the rule critical value of the metal layer in the code file of the DRC tool to simulate the process reason among the metal patterns in the metal layer or simulate the process reason among the metal patterns in the metal layer.

By way of example, FIG. 3B illustrates an exemplary diagram of chip layout inspection using a DRC tool, as shown in FIG. 3B, DRC DECK being a parameter profile of the DRC tool, recorded with a code file of the DRC tool; modifying the code file of the DRC tool can be accomplished by modifying DRC DECK; thus, the embodiment of the application can realize the modification of the rule critical value of the metal layer in the code file of the DRC tool by modifying the DRC DECK; further, by inspecting the GDS using the DRC tool for modifying DRC DECK, it is possible to check whether or not failure abnormality occurs between metal patterns inside the metal layer or after the metal patterns simulate the design corresponding to the process cause during the layout inspection of the chip.

In a further alternative implementation, if the data volume involved in chip layout inspection is large, the chip layout data can be simplified, so that the data volume of chip layout inspection by chip inspection tools such as LVS, DRC and the like is reduced, and the processing efficiency is improved. For example, before step S140 is performed (i.e., before the step of checking whether the suspected failure location simulation process cause occurs or not after the step of checking whether the suspected failure location simulation process cause occurs), the chip layout data may be reduced to obtain reduced chip layout data in the embodiment of the present application; thus, step S140 may be performed based on the reduced chip layout data (i.e., checking whether a failure abnormality occurs after simulating the process cause at the suspected failure location, which may be performed based on the reduced chip layout data).

As an optional implementation, when the chip layout data is reduced, a part of the chip layout data which is not related to the suspected failure position may be deleted. For example, in the embodiment of the present application, a metal layer in the chip layout data that is not related to the suspected failure position may be deleted, and a circuit layout portion in the chip layout data that is not related to the suspected failure position may be deleted; the portion of the chip layout data that is not related to the suspected failure location may be considered as a portion of the chip layout data that is not included in the suspected failure object.

As an optional implementation, the embodiment of the application can divide the chip layout data into a plurality of sub-layout data (namely divide the large chip layout data into a plurality of small sub-layout data), and further perform chip layout inspection on each sub-layout data so as to reduce the data quantity when chip inspection tools such as LVS, DRC and the like perform one-time inspection.

In an alternative implementation example, deleting the part irrelevant to the suspected failure position in the chip layout data and dividing the chip layout data into a plurality of sub-layout data can be combined for use, and one of the sub-layout data can be selected for use, so that the effect of simplifying the chip layout data can be achieved.

By way of example, FIG. 4A illustrates an example diagram of inspecting a reduced chip layout using an LVS tool, and in conjunction with the illustrations of FIGS. 3A and 4A, the GDS may implement a reduced GDS by deleting portions that are not related to suspected failure locations and/or dividing into a plurality of sub-layout data; thus, after modifying the LVSDECK, the reduced GDS may be inspected using an LVS tool that modifies the LVS DECK.

By way of example, FIG. 4B illustrates an example diagram of inspecting a reduced chip layout using a DRC tool, and in connection with the illustrations of FIGS. 3B and 4B, the GDS may implement a reduced GDS by deleting portions that are not related to suspected failure locations and/or dividing into a plurality of sub-layout data; thus, after modifying DRC DECK, the reduced GDS may be inspected with a DRC tool that modifies DRC DECK.

In a further alternative implementation, embodiments of the present application may further verify the accuracy of the inspection report after the inspection report is obtained. Optionally, the embodiment of the application can verify the accuracy of the inspection report through testing, simulation and other modes.

As an optional implementation, the test may be, for example, an abnormal failure test, and in the embodiment of the present application, a design corresponding to a process reason may be introduced at a suspected failure location, and whether a failure abnormality actually occurs at the suspected failure location is tested, so as to obtain a test result. Thus, the inspection report may be compared with the test result, and in the case where the inspection report matches the test result, the inspection report is considered to pass the verification of the accuracy of the test result. For example, if the suspected failure position and the process reason indicated by the inspection report and the suspected failure position and the process reason are matched with the test result, the inspection report is considered to pass the verification of the accuracy of the test result.

In one example, an abnormal failure test such as a Short test, a Open test, a functional test, or the like. For example, assuming that the inspection report indicates that the position between the metal layer M1 and the metal layer M2 is the position between suspected metal layers with short circuits, and the process reason is that the thickness of the isolation layer between the metal layer M1 and the metal layer M2 is insufficient, the embodiment of the present application may perform the short circuit test on the metal layer M1 and the metal layer M2; for example, in the short circuit test, a connection layer may be introduced between the metal layer M1 and the metal layer M2, and whether a short circuit actually occurs between the metal layer M1 and the metal layer M2 is tested, so as to obtain a short circuit test result. If the short circuit test result indicates that a short circuit actually occurs between the metal layer M1 and the metal layer M2, it is considered that the short circuit test result matches the inspection report.

Alternatively, the test tools used to perform the test (e.g., an abnormal failure test) may include, but are not limited to: ATE (Automatic Test Equipment, integrated circuit automatic test equipment) test system, test source table, etc., embodiments of the present application are not limited.

As an optional implementation, the simulation may be to perform electrical characteristic simulation corresponding to the process reason at the suspected failure position by using a simulation tool, and simulate whether the suspected failure position is abnormal in failure, so as to obtain a simulation result. Thus, the inspection report can be compared with the simulation result, and in the case that the inspection report is matched with the simulation result, the inspection report is considered to pass the verification of the accuracy of the simulation result. For example, if the suspected failure position and the process reason indicated by the inspection report and having failure abnormality are matched with the simulation result, the inspection report is considered to pass the verification of the accuracy of the simulation result.

In one example, assuming that the inspection report indicates that the position between the metal layer M1 and the metal layer M2 is a position between suspected metal layers where a short circuit exists, and that the process reason is that the thickness of the isolation layer between the metal layer M1 and the metal layer M2 is insufficient, the embodiment of the present application may simulate the connection layer between the metal layer M1 and the metal layer M2 by using a simulation tool, so as to perform corresponding electrical characteristic simulation between the metal layer M1 and the metal layer M2, and simulate whether the metal layer M1 and the metal layer M2 are shorted, to obtain a simulation result. If the simulation result indicates that a short circuit occurs between the metal layer M1 and the metal layer M2, the simulation result is considered to be matched with the inspection report. By way of example, fig. 5 is a graph exemplarily showing a comparison example of simulation results, as shown in fig. 5, in which a solid line in fig. 5 represents a simulation curve of current and voltage after an electrical characteristic simulation is introduced between the metal layer M1 and the metal layer M2 (for example, a simulation curve of current and voltage after a connection layer is simulated between the metal layer M1 and the metal layer M2), and in which a broken line in fig. 5 represents a simulation curve of current and voltage before an electrical characteristic simulation is introduced between the metal layer M1 and the metal layer M2 (for example, a simulation curve of current and voltage before a connection layer is simulated between the metal layer M1 and the metal layer M2), it can be seen that a short circuit is presented between the metal layer M1 and the metal layer M2 after an electrical characteristic simulation is introduced between the metal layer M1 and the metal layer M2.

In an alternative implementation, if the inspection report in the embodiment of the present application matches the test result and/or the simulation result, the inspection report may be regarded as passing the accuracy verification. For example, embodiments of the present application may confirm that the inspection report passes accuracy verification when the inspection report matches both the test result and the simulation result. For example, based on the result of the eFA layout inspection reported by the inspection report, in the case that the simulation result, the eFA layout inspection result, and the test result are matched with each other, the embodiment of the present application may confirm that the result of the eFA layout inspection (i.e., the inspection report) passes the accuracy verification. Taking the chip PIN (PIN) short-circuit failure exception as an example, fig. 6 exemplarily shows an exemplary diagram in which a eFA layout inspection result, a simulation result, and a test result are matched with each other, which can be referred to.

In a further alternative implementation, embodiments of the present application may further verify the plausibility of the inspection report after it is obtained. Optionally, the inspection report may indicate a suspected failure location where a failure abnormality occurs and a corresponding process reason, so that the embodiment of the present application may perform actual FA processing based on the suspected failure location where the failure abnormality occurs and the corresponding process reason indicated by the inspection report. For example, the embodiment of the application can eliminate the design corresponding to the process reason at the suspected failure position of the chip and judge whether the failure abnormality at the suspected failure position of the chip is eliminated; if the suspected failure position of the chip is eliminated and the design corresponding to the process reason is eliminated, the failure abnormality of the suspected failure position is actually generated by the design corresponding to the process reason, and the inspection report is reasonable; thus, embodiments of the present application may confirm that the inspection report passes the plausibility verification.

In an alternative implementation, the embodiment of the application can verify the accuracy of the inspection report a priori, and after the inspection report passes the accuracy verification, the inspection report is verified to be reasonable; if the inspection report passes the plausibility verification, step S150 shown in fig. 1 (i.e., a failure analysis result of the chip is generated based on the inspection report) may be performed.

By way of example, taking the case of failure exception of the short circuit of the chip pin indicated by the inspection report as an example, the voltage and current conditions of the chip pin when the process cause indicated by the inspection report exists can be measured by testing, simulation or the like to verify whether the chip pin has the short circuit, and correspondingly, fig. 7A exemplarily shows an exemplary diagram of the current and the voltage of the short circuit of the chip pin, and as can be seen from fig. 7A, the tested, simulated voltage and current appear as the short circuit of the pin when the process cause indicated by the inspection report exists on the pin. For verifying the rationality of the inspection report, the design corresponding to the short-circuit area of the chip pin indicated by the inspection report may be eliminated, for example, FIB (Focused Ion Beam) is used to cut off the short-circuit area of the chip pin (the short-circuit area may correspond to the technological reason for the short-circuit of the chip pin indicated by the inspection report), and then the voltage and current conditions of the pin are measured; accordingly, fig. 7B is an exemplary diagram illustrating the current and the voltage after the chip pins are cut off the short-circuit area, and it can be seen from fig. 7B that the voltage and the current of the pins are recovered from the short-circuit after the pins are cut off the short-circuit area; therefore, the rationality of the inspection report indicating the occurrence of the short circuit of the chip pins and the corresponding process reasons can be verified.

In an alternative implementation, the failure analysis scheme of the chip provided by the embodiment of the application may involve a stage shown in fig. 8, so that accuracy and rationality are ensured on the basis of improving coverage of the failure analysis on the chip. Optionally, fig. 8 is an exemplary diagram illustrating a stage of failure analysis of a chip according to an embodiment of the present application, and as shown in fig. 8, the failure analysis of the chip may include the following stages.

In the preliminary failure analysis stage 801, the method can perform preliminary failure analysis on defective products or chips with abnormal failures, so as to obtain a local failure analysis result of the chips, wherein the local failure analysis result comprises local failure positions of the chips with abnormal failures and process reasons corresponding to the local failure positions.

eFA layout checking stage 802, in eFA layout checking stage 802, the embodiment of the application can automatically determine the suspected failure position of the chip according to the local failure position by writing a related program or script; modifying the checking rule of the suspected failure position in the code file of the chip checking tool so as to simulate the process reason at the suspected failure position; and further, performing chip layout inspection through a chip inspection tool to inspect whether the suspected failure position is abnormal or not, so as to obtain an inspection report. Furthermore, before chip layout inspection is performed, the chip layout data can be simplified, so that the data size of the chip layout inspection is reduced.

In the accuracy verification stage 803, the accuracy of the inspection report can be verified in a test, simulation or other mode; for example, the inspection report is subjected to data checking with the test result and the simulation result, and the accuracy of the inspection report is verified by judging whether the inspection report is matched with the test result and the simulation result.

In the rationality verification stage 804, the embodiment of the application may perform actual FA verification on the chip according to the indication of the inspection report, thereby verifying the rationality of the inspection report. Alternatively, the embodiment of the application may further verify the rationality of the inspection report if the inspection report passes the accuracy verification.

In the failure analysis result generation stage 805, the embodiment of the present application may generate a failure analysis result of the chip according to the inspection report, so as to provide comprehensive direction and evidence for improvement of the chip in the production, manufacturing and design links. Optionally, in the embodiment of the present application, after the inspection report passes through the accuracy verification and the rationality verification, a failure analysis result of the chip may be generated according to the inspection report.

An alternative implementation of the stages illustrated in fig. 8 may refer to the descriptions of the corresponding parts above, and will not be repeated here.

Optionally, in the failure analysis scheme provided in the embodiment of the present application, during chip production and manufacturing, failure analysis is performed on a defective chip or a chip with abnormal failure due to a process problem, and failure analysis is performed in a chip production and manufacturing link after chip design. Furthermore, based on the thought of the failure analysis scheme provided by the embodiment of the application, the embodiment of the application can improve the chip inspection process in the chip design stage, so that failure abnormality is avoided by design modification in advance in the chip design stage; that is, the embodiment of the application can avoid the similar failure abnormality of the failure analysis stage from happening again through the checking means in the chip design stage. As an alternative implementation, fig. 9 illustrates an alternative flowchart of a chip design method provided in an embodiment of the present application, where the method may be implemented by executing a computer device with chip design assistance software installed, and referring to fig. 9, the method flowchart may include the following steps.

In step S910, a staged design result of the chip is obtained.

The chip design has a plurality of design stages, and the embodiment of the application can obtain the staged design result of the chip after the chip finishes the design of the set design stage. The staged design result of the chip is, for example, the circuit netlist result after the chip completes the design stage of the circuit netlist, or the layout design result after the chip completes the layout design stage, etc.

In step S911, a chip inspection tool is invoked, and the chip inspection tool records a failure analysis result of the chip, where the failure analysis result indicates a chip position where there is a risk of failure abnormality of the chip, and a corresponding process reason.

After the staged design result of the chip is obtained, the chip inspection tool (such as LVS tool, DRC tool, etc.) based on failure analysis may be invoked, so that the chip design inspection is performed by using the chip inspection tool based on failure analysis, thereby checking whether the chip has failure abnormality at the chip position where the failure abnormality risk exists. In the embodiment of the application, the chip inspection tools such as the LVS tool and the DRC tool can record the failure analysis result of the chip, and the failure analysis result of the chip can be obtained according to the failure analysis method of the chip provided by the embodiment of the application. Alternative ways of obtaining failure analysis results for a chip may be found in the description of the corresponding parts above.

In an alternative implementation, the failure analysis result of the chip recorded by the chip inspection tool can indicate the chip position and the corresponding process reason of the chip with abnormal failure risk; the chip position where the chip has abnormal risk of failure may correspond to the suspected failure position in the inspection report that has been previously verified for accuracy and rationality. For example, after the foregoing inspection report passes the verification of accuracy and rationality, the embodiment of the present application may apply the suspected failure location and the corresponding process cause indicated by the inspection report where the failure exception occurs to the inspection process of chip design, so as to avoid the failure exception of the chip in advance in the chip design stage.

In step S912, using a chip inspection tool, checking whether a failure abnormality occurs in the chip position in the staged design result; if yes, go to step S913, if no, go to step S914.

The embodiment of the application can utilize chip inspection tools such as an LVS tool, a DRC tool and the like to inspect the staged design result of the chip in the stage of chip design, and utilize the chip position with failure abnormal risk and the corresponding process reason indicated by the failure analysis result during inspection.

If the chip position with the failure abnormality risk is checked, the subsequent chip production and manufacture are carried out according to the stage design result, and the chip position is at a high probability of the failure abnormality risk due to the process, and at the moment, the stage design result needs to be modified to avoid the risk.

If the periodic design result is checked at the chip position with failure abnormality risk and failure abnormality does not occur, the subsequent chip production and manufacturing are carried out according to the periodic design result, the chip is free from the risk of failure abnormality at the chip position with high probability, and the periodic design result can be confirmed to pass the check.

In step S913, the staged design result is modified according to the process reason corresponding to the chip position, and step S912 is returned.

When the chip position with the failure abnormality risk of the staged design result is in the failure abnormality, the embodiment of the application can modify the staged design result according to the process reason corresponding to the chip position so as to try to overcome the failure abnormality problem of the chip position. For the modified staged design result, the embodiment of the present application may return to step S912, and check again whether the modified staged design result has failure abnormality at the chip position, until the modified staged design result (possibly modified one or more times) does not have failure abnormality at the chip position, so that the design with failure abnormality risk in the staged design result may be repaired.

In step S914, it is confirmed that the staged design result passes the inspection.

It can be seen that the chip failure analysis result can be applied to the chip design checking link by the chip failure analysis method, so that the chip failure abnormality problem is avoided in the chip design stage in advance, and the chip design performance and the yield of production and manufacture are improved.

In the alternative implementation, the failure abnormality caused by the process reason of the chip can be overcome in the process links of the chip production and manufacture; if failure abnormality caused by process reasons cannot be overcome in the process links of chip production and manufacturing, the inspection flow of the chip design stage can be adjusted and the staged design result of the chip is guided to be modified in the chip design stage, so that the problem of failure abnormality is avoided in the chip design stage.

The scheme provided by the embodiment of the application can comprehensively and detailed check the local failure position and the process reason of failure abnormality of the chip actually and the suspected failure position and the process reason of failure abnormality risk of the chip, can promote the coverage of failure analysis on the chip, provides more comprehensive direction and evidence for the improvement of the chip in production, manufacture and design links, and provides a basis for improving the yield of the chip and reducing the probability of failure abnormality of the chip. Alternatively, the scheme provided by the embodiment of the application can be realized by programming a program or a script, and the failure analysis checking efficiency is higher. Furthermore, the embodiment of the application can apply the failure analysis result to the inspection process of chip stage design, so that the failure abnormality problem is avoided in advance in the chip design stage, and the chip design performance is improved.

The following describes a failure analysis apparatus for a chip provided in an embodiment of the present application, where the content of the failure analysis apparatus described below may be regarded as a functional module required to be set by a computer device to implement the failure analysis method provided in the embodiment of the present application. The following description may be referred to in correspondence with the above description.

As an optional implementation, fig. 10 is an optional block diagram schematically illustrating a failure analysis apparatus of a chip provided in an embodiment of the present application, as shown in fig. 10, where the apparatus may include:

the local result obtaining module 101 is configured to obtain a local failure analysis result of the chip, where the local failure analysis result includes a local failure position where a failure abnormality occurs in the chip, and a process reason corresponding to the failure abnormality occurring in the local failure position;

the suspected position determining module 102 is configured to determine a suspected failure position of the chip according to the local failure position, where the suspected failure position is a chip position suspected of having a failure abnormality due to a process reason;

a simulation module 103, configured to simulate a process reason at the suspected failure location;

the checking module 104 is configured to check whether a failure abnormality occurs after the suspected failure location simulates a process reason, and obtain a checking report;

And the result generating module 105 is used for generating a failure analysis result of the chip according to the inspection report.

Alternatively, the local result obtaining module 101, the suspected location determining module 102, the simulation module 103, and the result generating module 105 may be implemented by writing a program or script, and the inspection module 104 may be implemented by a chip inspection tool such as an LVS tool, a DRC tool, or the like.

Optionally, the simulation module 103 is configured to simulate, at the suspected failure location, the process reasons including:

modifying the checking rule of the suspected failure position in the code file of the chip checking tool to simulate the design corresponding to the technological reason at the suspected failure position; the chip checking tool is used for checking the layout of the chip.

Optionally, in one aspect, the simulating module 103 is configured to modify, in a code file of the chip inspection tool, an inspection rule of the suspected failure location, so as to simulate, at the suspected failure location, a design corresponding to the process reason, including:

in the code file of the chip inspection tool, the inspection code of the suspected failure position is newly added, and the newly added inspection code expresses that the suspected failure position has a design corresponding to the technological reason.

Optionally, the simulation module 103 is configured to add, in a code file of the chip inspection tool, an inspection code of a suspected failure location, and the added inspection code expresses that the suspected failure location has a design corresponding to a process reason, including:

If the suspected failure position is the position between the suspected metal layers, a check code between the suspected metal layers is newly added in a code file of the chip check tool, and the newly added check code expresses that the suspected metal layers have a connection relation corresponding to the technological reason;

and determining the positions among the suspected metal layers according to the positions among the local metal layers with abnormal failure of the chip.

Optionally, on the other hand, the simulating module 103, configured to modify, in a code file of the chip inspection tool, an inspection rule of a suspected failure location, so as to simulate, at the suspected failure location, a design corresponding to a process reason, includes:

and if the suspected failure position is the inside of the metal layer, modifying the rule critical value of the metal layer in the code file of the chip checking tool according to the process reason.

Optionally, the simulation module 103 is configured to modify, according to a process reason, a rule threshold of the metal layer in a code file of the chip inspection tool if the suspected failure location is inside the metal layer, where the rule threshold includes:

if the suspected failure position is the position between the suspected metal patterns or the position of the suspected metal patterns, modifying the rule critical value of the metal layer where the suspected metal patterns are positioned in the code file of the chip checking tool according to the process reason;

The positions of the suspected metal patterns are determined according to the positions of the local metal patterns with abnormal failure of the chip, and the positions of the suspected metal patterns are determined according to the positions of the local metal patterns with abnormal failure of the chip.

Optionally, the determining module 102 of the suspected location is configured to determine, according to the local failure location, a suspected failure location of the chip includes:

and searching a position corresponding to the position attribute of the local failure position in the chip according to the position attribute of the local failure position, and taking the position as a suspected failure position of the chip.

Optionally, the local failure location includes a local physical layer location; the suspected failure location includes: a suspected physical layer location; the location attribute of the local failure location includes: the local physical layer is located in a corresponding chip space and a physical layer type of the local physical layer;

the suspected location determining module 102 is configured to find, in the chip, a location corresponding to the location attribute of the local failure location according to the location attribute of the local failure location, where the suspected failure location as the chip includes:

and searching a position corresponding to the physical layer type of the local physical layer in the chip based on the chip space corresponding to the local physical layer position to obtain a suspected physical layer position.

Optionally, the local physical layer location includes any one of the following: positions among the partial metal layers, positions among the partial metal patterns and positions of the partial metal patterns; the suspected physical location comprises any one of the following: positions between the suspected metal layers, positions between the suspected metal patterns, and positions of the suspected metal patterns.

Optionally, the checking module 104 is configured to check whether a failure anomaly occurs after the suspected failure location simulates a process reason, and the obtaining the check report includes:

after simulating the process reason at the suspected failure position, performing chip layout inspection by using a chip inspection tool to inspect whether failure abnormality occurs at the suspected failure position, and obtaining an inspection report.

Alternatively, the inspection module 104 may obtain the inspection report through a Signoff tool.

In a further alternative implementation, as shown in connection with fig. 10, the apparatus may further include:

the simplifying module 106 is configured to, before the step of checking whether the suspected failure location simulation process cause has failed abnormally is executed by the checking module 104, thin the chip layout data to obtain thin chip layout data;

the checking module 104 performs the step of checking whether the suspected failure location simulates the process reason and then whether the failure abnormality occurs based on the simplified chip layout data.

Optionally, the simplifying module 106 is configured to perform simplification on the chip layout data, including:

deleting a part irrelevant to the suspected failure position in the chip layout data;

and/or dividing the chip layout data into a plurality of sub-layout data.

Optionally, the result generating module 105 is configured to generate, according to the inspection report, a failure analysis result of the chip, where the failure analysis result includes:

forming a failure analysis result of the chip according to the suspected failure position of failure abnormality indicated by the inspection report and the process reason simulated by the suspected failure position;

or forming a failure analysis result of the chip according to the local failure analysis result, the suspected failure position of the failure abnormality indicated by the inspection report and the process reason simulated by the suspected failure position.

an accuracy verification module 107, configured to verify the accuracy of the inspection report before the result generation module 105 performs the step of generating the failure analysis result of the chip according to the inspection report.

Optionally, the accuracy verification module 107 is configured to verify accuracy of the inspection report, including:

Comparing the inspection report with the test result and/or the simulation result;

if the inspection report is matched with the test result and/or the simulation result, confirming that the inspection report passes the accuracy verification;

the test result is obtained by introducing a design corresponding to a process reason into the suspected failure position and testing whether the suspected failure position is actually abnormal or not according to the suspected failure position which is indicated by the inspection report and is abnormal in failure; and aiming at the suspected failure position with failure abnormality indicated by the inspection report, performing electrical characteristic simulation corresponding to the process reason at the suspected failure position by a simulation tool, and performing simulation test on whether the suspected failure position has failure abnormality.

a rationality verification module 108, configured to verify the rationality of the inspection report before the result generation module 105 performs the step of generating the failure analysis result of the chip according to the inspection report.

Optionally, the rationality verification module 108 is configured to verify the rationality of the inspection report includes:

based on the suspected failure position of the failure abnormality indicated by the inspection report and the corresponding process reason, carrying out actual failure analysis processing to judge whether the failure abnormality of the suspected failure position is eliminated after the design corresponding to the process reason is eliminated;

If yes, confirming that the inspection report passes the rationality verification.

The following describes a chip design apparatus provided in the embodiments of the present application, where the content of the chip design apparatus described below may be regarded as a functional module that is required to be set by a computer device performing chip design (for example, a computer device in which chip design auxiliary software is installed) to implement the chip design method provided in the embodiments of the present application. The following description may be referred to in correspondence with the above description.

As an optional implementation, fig. 11 illustrates an optional block diagram of a chip design apparatus provided in an embodiment of the present application, as shown in fig. 11, where the apparatus may include:

the staged result obtaining module 011 is configured to obtain a staged design result of the chip;

a calling module 012, configured to call a chip inspection tool, where the chip inspection tool records a failure analysis result of a chip, where the failure analysis result indicates a chip position where a chip has a risk of failure abnormality and a corresponding process reason; the failure analysis result is obtained according to the failure analysis method of the chip provided by the embodiment of the application;

a design checking module 013 for checking whether the periodic design result is abnormal in failure at the chip position by using a chip checking tool;

And the design modification module 014 is configured to modify the staged design result according to the process reason corresponding to the chip position if the determination result of the design checking module is yes, until the modified staged design result does not generate failure exception at the chip position.

The embodiment of the application also provides a computer device, which can execute the failure analysis method of the chip or the chip design method. As an alternative implementation, fig. 12 illustrates an alternative block diagram of a computing device provided by an embodiment of the present application, as shown in fig. 12, the computing device may include: at least one processor 1, at least one communication interface 2, at least one memory 3 and at least one communication bus 4.

In the embodiment of the present application, the number of the processor 1, the communication interface 2, the memory 3, and the communication bus 4 is at least one, and the processor 1, the communication interface 2, and the memory 3 complete communication with each other through the communication bus 4.

Alternatively, the communication interface 2 may be an interface of a communication module for performing network communication.

Alternatively, the processor 1 may be a CPU (central processing unit), GPU (Graphics Processing Unit, graphics processor), NPU (embedded neural network processor), FPGA (Field Programmable Gate Array ), TPU (tensor processing unit), AI chip, specific integrated circuit ASIC (Application Specific Integrated Circuit), or one or more integrated circuits configured to implement embodiments of the present application, or the like.

The memory 3 may comprise a high-speed RAM memory or may further comprise a non-volatile memory, such as at least one disk memory.

The memory 3 stores one or more computer executable instructions, and the processor 1 invokes the one or more computer executable instructions to execute the failure analysis method of the chip or the chip design method provided in the embodiment of the present application.

The embodiment of the application also provides a storage medium, which stores one or more computer executable instructions, and when the one or more computer executable instructions are executed, the failure analysis method of the chip or the chip design method provided by the embodiment of the application is realized.

The foregoing describes a number of embodiments provided by embodiments of the present application, and the various alternatives presented by the various embodiments may be combined, cross-referenced, with each other without conflict, extending beyond what is possible, all of which may be considered embodiments disclosed and disclosed by embodiments of the present application.

Although the embodiments of the present application are disclosed above, the present application is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention shall be defined by the appended claims.

Claims

1. A method of failure analysis of a chip, comprising:

simulating a process reason at the suspected failure position;

2. The method of claim 1, wherein simulating a process cause at the suspected failure location comprises:

3. The method of claim 2, wherein modifying the inspection rules for suspected failure locations in the code file of the chip inspection tool to simulate designs corresponding to process causes at the suspected failure locations comprises:

4. The method of claim 3, wherein the newly adding the inspection code for the suspected failure location in the code file of the chip inspection tool, and the newly adding the inspection code expressing that the suspected failure location has a design corresponding to a process cause comprises:

5. The method of claim 2, wherein modifying the inspection rules for suspected failure locations in the code file of the chip inspection tool to simulate designs corresponding to process causes at the suspected failure locations comprises:

6. The method of claim 5, wherein modifying the rule threshold of the metal layer in the code file of the chip inspection tool based on the process reason if the suspected failure location is inside the metal layer comprises:

7. The method of any of claims 1-6, wherein determining a suspected failure location of a chip based on the local failure location comprises:

8. The method of claim 7, wherein the local failure location comprises a local physical layer location; the suspected failure location includes: a suspected physical layer location; the location attribute of the local failure location includes: the local physical layer is located in a corresponding chip space and a physical layer type of the local physical layer;

Searching a position corresponding to the position attribute of the local failure position in the chip according to the position attribute of the local failure position, wherein the suspected failure position as the chip comprises:

9. The method of claim 8, wherein the local physical layer location comprises any one of: positions among the partial metal layers, positions among the partial metal patterns and positions of the partial metal patterns; the suspected physical location comprises any one of the following: positions between the suspected metal layers, positions between the suspected metal patterns, and positions of the suspected metal patterns.

10. The method of claim 1, wherein checking whether a failure anomaly has occurred after the suspected failure location simulates a process cause, the checking report comprising:

11. The method of claim 10, wherein the obtaining an inspection report comprises: inspection reports were obtained by the Signoff tool.

12. The method of claim 1, wherein prior to the step of checking whether a failure anomaly has occurred after the suspected failure location simulation process reason, the method further comprises:

simplifying the chip layout data to obtain simplified chip layout data; and checking whether failure abnormality occurs after simulating the process reason at the suspected failure position, and performing based on the simplified chip layout data.

13. The method of claim 12, wherein the compacting the chip layout data comprises:

and/or dividing the chip layout data into a plurality of sub-layout data.

14. The method of claim 1, wherein generating a failure analysis result of the chip based on the inspection report comprises:

forming a failure analysis result of the chip according to the suspected failure position with failure abnormality indicated by the inspection report and the process reason of the suspected failure position;

Or forming a failure analysis result of the chip according to the local failure analysis result, the suspected failure position with failure abnormality indicated by the inspection report and the process reason of the suspected failure position.

15. The method according to claim 1 or 14, wherein before performing the step of generating failure analysis results of the chip from the inspection report, the method further comprises:

and verifying the accuracy of the inspection report.

16. The method of claim 15, wherein said verifying the accuracy of the inspection report comprises:

17. The method according to claim 1 or 14, wherein before performing the step of generating failure analysis results of the chip from the inspection report, the method further comprises:

verifying the rationality of the inspection report.

18. The method of claim 17, wherein said verifying the plausibility of the inspection report comprises:

19. A chip design method, comprising:

acquiring a staged design result of the chip;

invoking a chip checking tool, wherein the chip checking tool records a failure analysis result of a chip, and the failure analysis result indicates the position of the chip with abnormal failure risk and a corresponding process reason; wherein the failure analysis result is obtained according to the failure analysis method of the chip of any one of claims 1 to 18;

20. A failure analysis apparatus for a chip, comprising:

21. A chip design apparatus, comprising:

the calling module is used for calling a chip checking tool, wherein the chip checking tool records a failure analysis result of a chip, and the failure analysis result indicates the position of the chip with abnormal failure risk and the corresponding technological reason; wherein the failure analysis result is obtained according to the failure analysis method of the chip of any one of claims 1 to 18;

22. A computer device comprising at least one memory storing one or more computer-executable instructions and at least one processor that invokes the one or more computer-executable instructions to perform the method of failure analysis of a chip as claimed in any one of claims 1 to 18 or the method of chip design as claimed in claim 19.

23. A storage medium storing one or more computer-executable instructions which, when executed, implement the method of failure analysis of a chip as claimed in any one of claims 1 to 18, or the method of chip design as claimed in claim 19.