JPH09321081A - Bonding property verification system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To lighten the burden of a worker and also, improve the design and verification efficiency by performing the verification of the layout at the same time with the verification of bonding property, based on the verification standard data, when performing the modification and edition of the position of each pad. SOLUTION: The verification of the layout is performed at the same time with the verification of the bonding property, based on the bonding property verification standard data 10 and the layout verification standard data 13, by means of a modification pad position bonding property verification means 2, for the layout design information requiring change when having modified and edited the position of each pad by a pad position modification and edition means 1. Next, the vertification result is displayed in real time by a verification result and modified pad position indicating means 3. Then, when the bonding property verification is finished for all pad positions, the pad position, the layout design information corresponding to it and the verification result are stored by a bonding property verification information storage means 4, and they are sent to a layout design process and a layout verification process.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout design / verification of a semiconductor integrated circuit, and more particularly to a bondability verification system used for verifying reliability of bonding at a pad position.

[0002]

2. Description of the Related Art In a conventional semiconductor integrated circuit layout design / verification process, a bondability verification operation is performed to confirm the reliability of bonding. The flow of the work will be described with reference to the flowchart of FIG.

As shown in the figure, the layout design / verification process of the semiconductor integrated circuit begins with a layout design for designing the layout of the entire semiconductor chip (step 60).
1), verification of the layout design of the next laid-out semiconductor chip, for example, whether the width of the figure itself is the standard value or more (internal inspection), and the distance between two or more figures is the standard value or more (enclosure inspection) The design rule inspection (DRC) for inspecting each of them, the layout line collation (LVS) for inspecting whether the logical connection relation and the layout design result match, the circuit connection state of the semiconductor integrated circuit, and the electrical characteristics such as wiring capacitance. Electrical characteristic inspection (ERC)
The layout verification (step 602) is executed.
If this layout verification passes, then the bonding reliability is verified (step 603). This bondability verification verifies whether the wire length (loop length), the wire entry angle of each wire with respect to each pad, and the like are included in the reference range.

If the result of the bondability verification is not within the range of the standard, that is, if the verification result fails, the operator determines the pad position designed in the layout design process based on the data of the verification result. Is empirically corrected, and the data of the entire semiconductor chip including the corrected data is returned to the initial layout design (step 60).
4, 601) and layout verification was performed again (step 602).

On the other hand, as a result of the bonding property verification, if the result is acceptable, a magnetic tape (M / T) and a mask storing the electron beam (EB) drawing data of the semiconductor chip are created (steps 605 and 606) and the assembly process is performed. Enter (step 607).

[0006]

However, when the result of the bondability verification is unsuccessful as described above, the operator empirically corrects the pad position, so that the layout verification after the correction is not always necessary. It does not always pass. Therefore, every time the layout verification fails, the work of steps 601 to 604 of FIG. 7, that is, the work of the layout design, the layout verification, and the bondability verification is repeated, and the design / verification efficiency deteriorates.
In addition, the burden on the operator has increased.

Therefore, an object of the present invention is to provide a bondability verification system which can reduce the burden on the operator and improve the design / verification efficiency.

[0008]

A bonding property verification system according to the present invention verifies the bonding reliability of each pad on a semiconductor chip that has completed a layout design process and a layout verification process, and a verification result is obtained. If the acceptance criteria are not satisfied, the pad position is corrected and the semiconductor chip is returned to the layout design process and layout verification process. Pad position correction / editing is performed to correct / edit the position of each pad on the semiconductor chip. Means and the layout design information that needs to be changed when the position of each pad is corrected / edited by the pad position correction / editing means. Based on the prepared bondability verification standard data and layout verification standard data, bondability verification and Corrected pad position bondability verification means for performing layout verification at some times, corrected pad position and verification result / corrected pad position display means for displaying the verification result by the corrected pad position bondability verification means in real time, and for all pad positions On the other hand, when the bondability verification is completed, it has a bondability verification information storage means for storing a pad position, layout design information corresponding to the pad position, and a verification result, and sending the result to the layout design process and the layout verification process.

As described above, when the operator corrects the pad position, the pad position and the bondability with respect to the pad position are verified, and the verification result is displayed in real time, so that the bondability verification efficiency is improved. Can be made. At the time of verifying the bondability, the layout information is changed and the layout information is verified at the same time as the pad position is corrected. Therefore, the layout verification does not fail again, so that the design efficiency can be improved.

In the bondability verification system according to the present invention, the correction pad position bondability verification means is
For each pad whose position has been changed by the pad position correction / editing means, the length of the wire connecting the pad and the lead wire corresponding to the pad, the length of the wire on the lead wire, and the semiconductor chip It is to verify whether or not the length of the wire and the penetration angle of the wire into the pad are within predetermined allowable ranges.

As described above, when the operator corrects the pad position, the pad position and the bondability with respect to the pad position are verified in real time, so that the bondability verification efficiency can be improved.

Further, the bonding property verification system according to the present invention determines the layout size of the semiconductor chip when the size of the entire semiconductor chip needs to be changed as a result of the verification by the correction pad position bonding property verification means. It is characterized by further comprising semiconductor chip size changing means for changing and outputting the changed size to the bonding property verification information storing means.

As described above, even when it is necessary to change the size of the entire semiconductor chip as a result of the correction of the pad position, the size of the entire semiconductor chip is changed in the process of verifying the bondability. The accompanying layout verification can be performed.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a bondability verification system according to the present invention will be described with reference to the block diagram of FIG.

The bonding property verification system of the present invention is
When the bondability verification is unsuccessful, the bondability verification is performed on the pad position correcting / editing means 1 for inputting the failed data and correcting the pad position and the corrected pad position. Correction pad position bondability verification means 2 for performing the above, and the coordinate position of the pad modified by the pad position modification / editing means 1 and the verification result / correction pad for displaying the verification result by the modified pad position bondability verification means 2 on the display 6. Position display means 3
And the information when the verification result by the corrected pad position bonding property verification means 2 is passed, for example, the pad position coordinates,
It has a bondability verification storage means 4 for inputting from the pad position correcting / editing means 1 and storing it.

Next, the outline of the verification procedure in this embodiment will be described with reference to the flowchart of FIG.

After layout design (step 201),
The layout is verified (step 202), and if the layout is unsuccessful, the process returns to the layout design (steps 202, 20).
1) If yes, the conventional bonding property verification is performed (step 203).

If the bondability verification fails, the operator corrects the corresponding pad position (step 2).
04). The corrected position of the pad is displayed on the spot on the display (step 205), the bondability verification and the layout verification accompanying the correction of the pad position are immediately performed, and the verification result is displayed on the spot. (Step 206).

If the bondability verification fails, the operator again corrects the corresponding pad position (steps 206 and 204). If the bondability verification is passed for all pads, the corrected pad position information is stored, and the process returns to the layout design process again (step 20).
7,201).

The layout verification in step 202 is not rejected because the layout verification is already performed in step 206 together with the bondability verification, and thus the step is not rejected.
The bonding property verification of No. 3 is passed as it is, and the process proceeds to the process of EB M / T creation, mask creation, and assembly (steps 208 to 210).

FIG. 3 shows a screen of the display 6 displayed by the verification result / correction pad position display means 3. As shown, the semiconductor chip 2 mounted on the bed 20
1. Each pad 22 on 1, a coordinate display 23 of each pad, an inner lead 23 corresponding to each pad 22, a wire 25 connecting each pad 22 and each inner lead 24.
And a tie bar 26 connecting each bed 20 are displayed. The operator corrects the position of the pad 22 on this screen.

In this way, when the operator specifies the pad position for correction, the specified pad position is highlighted on the screen, and when the pad position is moved, the pad position coordinates of the movement destination are displayed. Therefore, the positional relationship of the pads before and after the movement can be clearly understood.

Corrected pad position bondability verification means 2
Is stored in the pad position database 12 and the bondability verification reference data for each pad stored in advance in the bondability verification reference database 10, the frame inner lead shape data for each pad stored in the shape database 11. Based on the pad position data
The bond position is corrected by comparing the pad position corrected by the pad position correction / editing means 1, and whether or not the layout design information can be changed in accordance with the correction of the pad position is within the range of layout verification criteria. Verification is performed based on the layout verification reference data stored in the database 13.

Now, a part of the operation of the modified pad position bondability verification means 2 will be described with reference to the flowchart of FIG.

First, the corrected pad position bondability verification means 2 reads the coordinates of the pad (step 50).
1). Next, information about the lead wire connected to this pad is read (step 502). It is determined whether or not the length of the wire connecting the two, which is obtained from the coordinate of the pad and the lead wire information, falls within a predetermined range, that is, between the upper limit value and the lower limit value (step 503). If it is not within the range, the corrected bonding property verification is rejected and the pad position correction processing is performed (steps 510 and 51).
1). If it is within the range, the length of the wire on the lead wire is obtained, and it is judged whether or not it is larger than a predetermined value (step 5).
04). If it is not larger, the corrected bonding property verification is rejected and the pad position correction processing is performed (steps 510 and 511). If it is large, the length of the wire on the semiconductor chip is obtained, and it is determined whether it is within a predetermined range, that is, between the upper limit value and the lower limit value (step 50).
5). If it is not within the range, the corrected bondability verification is rejected and pad position correction processing is performed (steps 510 and 511). If it is within the range, the penetration angle of the wire into the pad is obtained, and it is judged whether it is smaller than a predetermined value (step 506). If it is not small, the corrected bondability verification is rejected and pad position correction processing is performed (steps 510 and 511). On the other hand, if it is smaller, the bondability verification is passed (step 50).
8) If there is a pad whose bondability verification has not been completed, the next pad position is designated (steps 509, 51).
2) Return to the beginning (step 501).

The operator continues to correct the pad position through the pad position correction / editing means 1 until the verification result is acceptable.

As described above, since the bondability verification is performed by also referring to the layout design information, the pad position can be corrected within the entire area of the semiconductor chip.

These bondability verification results are displayed in real time on the verification result / correction pad position display means 3 as verification values for each verification item, for example, for each loop length and each incoming line angle, and the overall verification result (pass / fail) is displayed. Pass) is also displayed. In this way, the bondability verification results of the correction pad position and the correction position are verified in real time.
It is displayed on the display 6 by the correction pad position display means 3 and is reported to the operator.

As a result, the operator can visually perform the work of correcting the pad position.

If the verification by the modified pad position bondability verification means 2 for all the pads is passed, the information on each pad position and the layout design information are stored in the bondability verification information storage means 4, and this information is stored. It is handed over again to the layout design process.

Since the layout verification has already been performed on this information by the corrected pad position bonding property verification means 2 as described above, the layout verification process does not fail again, and the bonding verification process also passes. .

Still another embodiment will be described with reference to the block diagram of FIG.

As shown in the figure, this embodiment is provided with a semiconductor chip size changing means 5 for changing the semiconductor chip size in addition to the above-mentioned embodiment.

The semiconductor chip size changing means 5 performs bonding verification on the corrected pad position,
When it is necessary to change the semiconductor chip size designed in the layout design process, the semiconductor chip size is changed. For example, when it is necessary to increase the size of the entire semiconductor chip, for example, only x2 in the lateral direction and y2 in the height direction.
When it is necessary to increase the size, the operator is urged to change the semiconductor chip size obtained by the proportional calculation on the verification result / correction pad position display means 3.

At this time, as shown in FIG. 6A, the verification result / correction pad position display means 3 causes the display 6 to be displayed.
In the upper window 30 for changing the semiconductor chip size, an area 1 for displaying the semiconductor chip size, a button 32 for indicating coordinates, a change execution button 33, and a change cancel button 34 are displayed, and the operator Select this button to perform the work. As shown in FIG. 6B, the semiconductor chip image 42 before the change and the semiconductor chip image 41 after the change are displayed on the display 6.

The changed semiconductor chip size is passed to the layout design process together with the information on each pad position.

As described above, since the semiconductor chip size changing means 5 can change the semiconductor chip size in the layout step in the bonding property verification step, the design / verification efficiency can be improved.

[0038]

According to the present invention, it is possible to provide a bonding property verification system which can reduce the burden on the operator and improve the design / verification efficiency.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a bondability verification system of the present invention.

FIG. 2 is a flowchart showing the operation of the embodiment of the bonding property verification system of the present invention.

FIG. 3 is a diagram showing a display screen in which a pad position is corrected.

FIG. 4 is a flowchart for explaining a bondability verification operation.

FIG. 5 is a block diagram showing another embodiment of the bonding property verification system of the present invention.

FIG. 6 is a diagram showing a display screen when changing a semiconductor chip size and images before and after the change.

FIG. 7 is a flowchart showing a conventional bonding property verification work.

[Explanation of symbols]

 1 Pad position correction / editing means 2 Corrected pad position Bondability verification means 3 Verification result / corrected pad position display means 4 Bondability verification storage means 5 Semiconductor chip size changing means 6 Display 10 Bondability verification reference database 11 Shape database 12 Pad position Database 13 Layout verification standard database

Claims (3)

[Claims] 1. The reliability of bonding is verified for each pad on the semiconductor chip that has completed the layout design process and layout verification process, and if the verification result does not satisfy the acceptance criteria, the pad position is corrected. Then, in the bondability verification system for returning the semiconductor chip to the layout design process and the layout verification process, pad position correction / editing means for correcting / editing the position of each pad on the semiconductor chip, and this pad position correction / editing means When the position of each pad is corrected / edited by, the pad position and the layout design information that needs to be changed in accordance with the correction / editing of the pad position are prepared in advance with the bondability verification reference data and the layout. Layout verification is performed at the same time as bondability verification based on verification standard data. Positive pad position bondability verification means, verification result / corrected pad position display means for displaying the corrected pad position and the verification result by the corrected pad position bondability verification means in real time, and the bondability for all pad positions When the verification is completed, a bondability verification system having the pad position, the layout design information corresponding to the pad position, and the bondability verification information storage means for storing the verification result and sending it to the layout design process and the layout verification process. . 2. The correction pad position bondability verification means, for each pad whose position has been changed by the pad position correction / editing means, length of a wire connecting the pad and a lead wire corresponding to the pad. Now, it is verified whether or not the length of the wire on the lead wire, the length of the wire on the semiconductor chip, and the angle of penetration of the wire into the pad are within predetermined allowable ranges. The bonding property verification system according to claim 1, wherein the bonding property verification system is a product. 3. If the size of the entire semiconductor chip needs to be changed as a result of verification by the correction pad position bonding property verification means, the size of the semiconductor chip in layout is changed, and the size is changed. The semiconductor chip size changing means for outputting the size to the bonding property verification information storage means is further provided.
Alternatively, the bondability verification system according to claim 2.