CN101339571A - VLSI layout planning centralized constrain implementing method - Google Patents
VLSI layout planning centralized constrain implementing method Download PDFInfo
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- CN101339571A CN101339571A CNA2007100477044A CN200710047704A CN101339571A CN 101339571 A CN101339571 A CN 101339571A CN A2007100477044 A CNA2007100477044 A CN A2007100477044A CN 200710047704 A CN200710047704 A CN 200710047704A CN 101339571 A CN101339571 A CN 101339571A
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Abstract
The invention belongs to a technical field of an integrated circuit computer aided design, in particular to the implementation method of centralized constraint in VLSI layout planning. The method is combined with B<*> -tree representation, simulated annealing algorithm and linear programming algorithm. The steps comprise that a constrained sub-tree is constructed according to constraint, each sub-tree is connected so as to form a permissible initial layout, and the simulated annealing algorithm is adopted to optimize such factors as areas, and the like; the constraint condition of linear programming is obtained from the initial layout, a linear programming matrix is constructed, a linear programming function is called for solving the linear programming matrix, compressing operation and soft module adjustment are carried out, and finally the result of optimizing the layout is obtained. The method is used for realizing the constraint that a plurality of modules need to be centralized and placed in a plane layout, and also is used for realizing the centralized constraint on the basis of a plurality of divisions or a whole division.
Description
Technical field
The invention belongs to the integrated circuit CAD technical field, be specifically related to geometrical constraint implementation method in a kind of allocation plan, realized the concentrated constraint in the allocation plan.
Background technology
Along with the continuous expansion of integrated circuit scale, what the layout of integrated circuit became becomes increasingly complex, thereby the research of integrated circuit floor planning algorithm has been subjected to extensive attention in recent years.Layout is the ten minutes critical step in large scale integrated circuit (VLSI) design, and it has material impact to finishing smoothly of back design effort, has determined area of chip size and performance quality [1] to a certain extent.And along with the continuous increase of VLSI design scale and complexity, layout also no longer is the optimization to chip area and signal link length, but need just as early as possible multiple constraints such as geometric position, time delay, voltage drop, electric power network and power dissipation density be taken into account at layout stage, reduce the reparation difficulty of constraint violation in the design process of back.Increase design closure, shorten design time [2].
In the current chip design, the grading design of stratification is used widely, and the application of intellecture property (IP) nuclear is more prevalent, becomes more and more important in the current chip design based on SOC (system on a chip) (SOC) design of IP kernel and macroblock (Macro Block).And along with number of modules among Module Division number or the SOC increases increase with constraint, the manual layout of rule of thumb being carried out by the slip-stick artist was more and more difficult in the past, be difficult to satisfy simultaneously various constraint requirements, therefore realize that BBL (Building Block Layout) the allocation plan problem of macroblock autoplacement has obtained extensive studies
Summary of the invention
It is single to the objective of the invention is to be to propose a kind of consideration, the layout planning method of a plurality of or whole concentrated constraint.
The realization that the present invention proposes concentrates the constraint plane layout planning method at B
*-tree[3] expression carry out, concentrate the subtree of constraint to divide the basic operation relevant by correspondence, and the method that adopts simulated annealing and linear programming to combine with subtree, realized the plane figure of satisfied concentrated constraint requirements.
(1): the definition of BBL constrained layout
In the BBL allocation plan problem, input be one group of sequence of modules that comprises area, net table link information and various constraint conditions, need realize finally obtaining the layout area minimum satisfying under all constraint condition situations, line is the shortest.
The BBL allocation plan problem of belt restraining can be described below:
Input is the set B of being made up of a macroblock={ b
1, b
2..., b
n, each module b wherein
iComprise following three category informations:
(1) module geological information: corresponding to the length (h of i module
i), wide (w
i), area (a
i), according to module length breadth ratio (τ
i) the variable die piece (the module length and width immobilize) that is divided into whether, soft mode piece (module area is constant, and length breadth ratio can be adjusted within the specific limits) also can be the module of other non-rectangles;
(2) second classes are module gauze information: corresponding to each module connection end sequence { P
1, P
2... P
mAnd the relative position of each port in module, and with the link information of other modules;
(3) the 3rd classes are module constraint and relevant information, and we will be described in detail below for constraint.
And output requires the corresponding total area (A of layout result
Total) minimum, (W) is the shortest for line length, satisfies each constraint condition simultaneously;
At traditional B BL allocation plan problem optimization aim normally area and line length, objective function is Minimize (α * Atotal+ β * W), α wherein, and β is respectively and optimizes the weight allocation coefficient.But along with the continuous increase of VLSI scale, increasing constraint need take in layout, to accelerate design closure, reduces iterations.
The related notion of our list of references [4] is two kinds with constraint definition in the BBL layout, and a kind of is geometrical constraint, and another kind of is that characteristic retrains, and is defined as follows:
Geometrical constraint: comprise to position in integral layout of each module and global shape, module, the requirement of geometric relationships such as relativeness between the module.For example retrain (alignment constraint), boundary constraint (boundaryconstraint) and concentrate constraint (clustering constraint) etc. in abutting connection with constraint (abutment constraint), alignment between the frame of chip restriction (fixed outline), module position (location range), the module.
The characteristic constraint: be the requirement of module particular community to layout, as power dissipation density requirement, voltage drop requirement, clock characteristic requirement and the test request etc. of module, these all can form constraint to the layout structure of module.The constraint of this class is also more and more important with being increased in the layout of VLSI scale and complexity, and the performance quality of final chip is had material impact.
Layout can be divided into permission (admissible) layout and non-permission (non-admissible) layout according to retraining whether in layout structure, to be met.
(2): consider to concentrate the BBL layout of constraint to realize
In the VLSI layout, usually consider that some factor need be with the concentrated placement of some modules, for example annexation is tight between the certain module, relates to critical path [5] [6] etc.In addition because the continuous increase of integrated circuit scale also requires some certain functional modules to concentrate placement in the grade classification design; In relating to clock SOC design for a long time, also usually the module of identical clock is concentrated placement [7] for the ease of the clock trees wiring, therefore bypass concrete constraint, realize that in the BBL layout concentrated constraint in general sense is significant.
Concentrate the definition of constrained layout (clustering constraint floorplan) problem: for one group of given macroblock, require certain module placement adjacent to one another in final layout wherein, close on the grouping number of placement module as required and whether cover whole modules and can will concentrate constraint to be divided three classes:
Single constraint: only have the one group of module that need close on placement
A plurality of constraints: have many these generic modules of group;
Whole constraint: constraint relates to all modules.
The realization that the present invention proposes concentrates the placement algorithm of constraint to be based on B
*-tree[3] the expression realization.Analyze the B of layout structure
*-tree represents that (as Fig. 1, shown in 2) can find, passes through B
*-tree is easy to judge the neighbouring relations between the respective modules.As at horizontal B
*Among-the tree (shown in Figure 1), the left submodule of node closes on module corresponding to the right side, adjacent block above right son is corresponding.And B
*The subtree that is made of part of nodes wherein among the-tree can realize concentrating the layout of constraint in layout, and for example we are with the horizontal B of Fig. 1
*-tree such as Fig. 3 (a) divide, in the corresponding layout in each dividing subset all corresponding modules realized concentrated constraint (shown in Fig. 3 (b)).
Based on this point, we have proposed to concentrate the corresponding subtree of constraint to divide the whole B that constitutes by each
*The algorithm of the CCFP layout that-tree finishes.
The present invention propose based on B
*The CCFP algorithm of-tree, basic thought is at first to construct an initial layout structure that satisfies constraint, in the basic operation of layout search, limit the operation that may cause constraint violation then, remain the layout structure of permission, saved the transfer process that non-permission layout represents that the permission layout is represented so on the one hand, penalty term need do not increased in objective function on the other hand, the convergence reduction of avoiding so causing.
In order to remain the permission layout in the optimizing process, the present invention is at original B
*The associative operation that has proposed on-tree basic operation the basis between the subtree is finished the global optimization operation.The change in location of analyzing between the subtree can find to have following two kinds: the 1. variation of relativeness between the subtree; 2. the variation of two subtree link positions, we propose to consider the B of subtree division in view of the above
*The basic operation of-tree is:
(1) rotary manipulation: exchange the length and width of certain module,
(2) work as exchange, deletion and to insert basic operation all be at the internal node operation of same subtree the time promptly exchanges two nodes or deletion of node and insertion node all when same subtree is carried out, and this generic operation only carries out at node.
(3) relate to two nodes not in same subtree the time when operation, then need to finish associative operation according to following judgement:
At swap operation: father node and the leaf node of root node that when one of them node is leaf node and the corresponding subtree of another one node exchange wherein corresponding leaf node and the whole subtree of another node correspondence in same subtree; Otherwise exchange the position of the corresponding subtree of two nodes, finish by the operation of subtree root node
Insert operation at deletion: delete corresponding subtree, connect the integrality that other subtrees keep tree simultaneously, chosen position is placed and is inserted in inserting subtree.
The operation that the consideration subtree that the present invention will propose is divided is placed in the fast simulated annealing algorithm (Fast-SA) [8], compresses operation and the adjustment of soft mode piece by linear programming (LP) [9] then, thereby realizes whole placement algorithm.Total algorithm is described below:
1.: construct each constraint subtree according to constraint requirements, connect each subtree and constitute the initial layout that allows;
2.: according to top basic operation (1)～(3) that allow layout of not destroying, adopt simulated annealing that factors such as area are optimized, each module is used as the processing of die piece in the optimizing process;
3.: obtain the constraint condition that initial layout is judged linear programming according to 2 steps, construct linear planning matrix;
4.: call the linear programming function separate the linear programming matrix compress the operation and the adjustment of soft mode piece;
5.: record layout result, output relevant information.
Description of drawings
Fig. 1 is B
*-tree level is represented synoptic diagram.
Fig. 2 is B
*-tree vertically represents synoptic diagram.
Fig. 3 realizes concerning synoptic diagram for dividing subtree with constraint.
Fig. 4 is that layout standard testing use-case ami33 considers the whole resultant test layout result of constraint of concentrating.
Fig. 5 is that layout standard testing use-case ami49 considers the whole resultant test layout result of constraint of concentrating.
Embodiment
1., read the layout input information, store area, length and width, type, line and the constraint information of each module;
2., the initial layout that allows according to the requirement structure of concentrating constraint: at first the module that each constraint is related to is connected to subtree, and the module that does not relate to constraint is divided into subtree separately, then each subtree is connected and composed whole B
*-tree.；
3., adopt simulated annealing that overall factors such as area are optimized.
Basic operation is rotation in the simulated annealing, exchange, deletion and insertion.Method of operating is: (1) rotary manipulation: the length and width that exchange certain module.(2) work as exchange, deletion is inserted basic operation and all is at the internal node operation of same subtree the time, promptly exchanges two nodes or deletion of node and insertion node all when same subtree is carried out, and this generic operation only carries out at node.(3) relate to two nodes not in same subtree the time when operation, then need to finish associative operation according to following judgement:＜1 at swap operation: father node and the leaf node of root node that when one of them node is leaf node and the corresponding subtree of another one node exchange wherein corresponding leaf node and the whole subtree of another node correspondence in same subtree; Otherwise exchange the position of the corresponding subtree of two nodes.＜2〉insert operation at deletion: delete corresponding subtree, connect the integrality that other subtrees keep tree simultaneously, chosen position is placed and is inserted in inserting subtree.
Each module length breadth ratio is not adjusted in the optimizing process, all is used as the die piece and handles.The temperature of simulated annealing wherein, controlled variable such as iterations can be according to the time of finding the solution and the requirement of finding the solution quality are adjusted.Initial annealing temperature in the simulated annealing that adopts in the present invention's experiment is 1, ending annealing temperature is 0.6, the iterative search number of times is 300*N (wherein N is the test case number of modules) under each temperature, when no longer convergence or stop further search when having reached final temperature of search, get that the optimal location result exported as this step in the search;
4., obtain the constraint condition that initial layout is summarized linear programming according to 3 steps.
Wherein optimization aim is not change total area minimum under the original relative position condition, and objective function is Minimize ... f=λ
1H
c+ λ
2W
c, λ wherein
1, λ
2Be respectively simulated annealing layout result Aspect Ratio, h
c, w
cLength and width for layout.
The variable of linear programming is the position x of all modules
i, y
iWith length and width h
i, the length and width h of w and total arrangement
c, w
cLinear programming constraint condition mainly contains four kinds of constraints and forms: the range lambda of＜1〉module self length breadth ratio
Min＜h
i/ w
i＜λ
Max＜2〉position constraint between the module: x
i+ w
i＜=x
jAnd y
i+ h
i＜=y
j＜3〉layout range constraint: x
i+ w
i＜=w
cAnd y
i+ h
i＜=h
c＜4〉parameter area constraint: x
i, y
i, w
i, h
i, w
c, h
c＞=0;
5., obtain using mathematical tool Matlab built-in function that optimum solution is asked in linear programming after the objective function of linear programming and the constraint condition, be met numerical value (each module position x of all parameters when area is optimum under all constraint conditions
i, y
i, length and width h
i, w and overall length and width h
c, w
c);
6., record layout result, output relevant information, obtain the final optimization pass layout result.
Test findings:
The present invention adopts the ami33 of MCNC general in the placement algorithm in the world and ami49 as test case in the test.Consider area and link information that each module only is provided among ami33 and the aim49 simultaneously, the present invention adopts random device that all modules are divided as concentrating constraint.Because this random division and original link information are also inconsistent, thereby gauze information is left in the basket in test of the present invention, only consider area and concentrate the realization that retrains.But this does not influence us and considers to concentrate constraint to realize the validation verification of layout method.We become 5 to concentrate constraint (original test case information and constraint division information are shown in table one, table two) each test case random division in the test.
The former test case information of table 1:MCNC:
| MCNC standard testing circuit | Number of modules | The gauze number | Each module area and (mm 2) |
| ami33 | 33 | 123 | 1.16 |
| ami49 | 49 | 408 | 35.45 |
Table 2: the constraint information of increase
| MCNC standard testing circuit | ami33 | ami49 |
| The |
5 | 5 |
| |
3，10，11，16，29，38 | 3，10，11，16，29 |
| |
0，12，14，15，19，20，26，27， 31，32，41，46，47 | 0，12，14，15，19，20，26， 27，31，32 |
| |
1，8，13，17，18，22，24，25， 30，35，36，42， | 1，8，13，17，18，22，24， 25，30 |
| |
6，7，23，28，33，40，43，44， 48 | 6，7，23，28 |
| |
2，4，5，9，21，34，37，39，45 | 2，4，5，9，21 |
Placement algorithm of the present invention realizes that by the C++ programming wherein step (5) is to find the solution by calling Matlab software among the VC++, and test condition of the present invention is 2.4GHz Core2 Intel PC, internal memory 2G.
Test findings such as table 3, accompanying drawing 4 and shown in Figure 5 can be known and see, considers to concentrate in the layout of constraint in the present invention, each concentrates constraint to be realized preferably, has overcome that all constraints are the result of rectangle in the document [7], has improved area utilization
Table 3: the related data that ten tests obtain:
As shown in table 4, and the test figure that test case Ami49 provides under the identical condition in the document [9] is relatively, the present invention all makes moderate progress on time and area utilization, and and do not consider to concentrate the b of constraint
*-treeb represents that area-optimized this algorithm of comparison only slightly increases at area with on the time, so this algorithm is that effectively comparative result is as shown in table 2:
Table 2: comparative result
List of references:
[1] Xu Nin, Hong Xianlong, Dong Sheqin.BBL placement algorithm research [J].Computer-aided design (CAD) and graphics journal, 2004,18 volumes, the 09th phase: pp1216～1219
[2] Ceng Hong.The physical Design research [master thesis] of VLSI (very large scale integrated circuit) under the deep-submicron.Shanghai: Fudan University, 2005
【3】Yun-Chih Chang；Yao-Wen Chang；Guang-Ming Wu；Shu-Wei Wu；B
*-trees：a newrepresentation for non-slicing floorplans[C].Design Automation Conference，2000.Proceedings2000.37
th June 5-9，2000 Page(s)：458-463
[4] Wang Jinmin, Wang Yuxin looks into and builds.The classification and the expression of location problem constraint.Computer-aided design (CAD) and graphics journal, 2000, the 05th phase: 349～354
【5】Yuen，W.S.；Young，E.F.Y.；Slicing floorplan with clustering constraint[J].Computer-AidedDesign of Integrated Circuits and Systems，IEEE Transactions on Volume 22，Issue 5，May 2003Page(s)：652-658
【6】Chrzanowska-Jeske，M.；Benyi Wang；Greenwood，G.；Floorplanning withperformance-based clustering[C].Circuits and Systems，2003.ISCAS′03.Proceedings of the2003 International Symposium on Volume 4，25-28 May 2003 Page(s)：IV-724-IV-727 vol.4
【7】Changhong Zhao，Jian Chen，Xiaofang Zhou et al.Floorplanning Algorithm for multipleclock domains.Proceedings of the 4th WSEAS/IASME Int.Conf.on System Science andSimulation in Engineering，Tenerife，Spain，December 16-18，2005(pp.156-162)
【8】Tung-Chieh Chen；Yao-Wen Chang；Modern floorplanning based on B/sup*/-tree and fastsimulated annealing[J].Computer-Aided Design of Integrated Circuits and Systems，IEEETransactions on Volume 25，Issue 4，April 2006 Page(s)：637-650
【9】Changhong Zhao，Jian Chen，Xiaofang Zhou，Ming’e Jing，Floorplanning Method Basedon Liner Programming[J].WSEAS Transaction on computers，Issue 11，Vol 5，Nov 2006：2874-2880
Claims (1)
1, concentrate the implementation method of constraint in a kind of VLSI allocation plan, it is characterized in that concrete steps are as follows:
(1) initial layout that allows according to the requirement structure of concentrating constraint: at first the module that each constraint is related to is connected to subtree, and the module that does not relate to constraint is divided into subtree separately, then each subtree is connected and composed whole B*-tree;
(2) adopt simulated annealing that overall factor is optimized:
Basic operation is rotation, exchange, deletion and insertion in the simulated annealing, and method of operating is:
1. rotary manipulation: the length and width that exchange certain module;
2. when exchange, deletion is inserted basic operation and all is at the internal node operation of same subtree the time, promptly exchanges two nodes or deletion of node and insertion node all when same subtree is carried out, and this generic operation only carries out at node;
3. relate to two nodes not in same subtree the time when operation, then need to finish associative operation according to following judgement:＜1 at swap operation: father node and the leaf node of root node that when one of them node is leaf node and the corresponding subtree of another one node exchange wherein corresponding leaf node and the whole subtree of another node correspondence in same subtree; Otherwise exchange the position of the corresponding subtree of two nodes;＜2〉insert operation at deletion: delete corresponding subtree, connect the integrality that other subtrees keep tree simultaneously, chosen position is placed and is inserted in inserting subtree;
Each module length breadth ratio is not adjusted in the optimizing process, all is used as the die piece and handles, and wherein controlled variable such as the temperature of simulated annealing, iterations can be according to the time of finding the solution and the requirement of finding the solution quality are adjusted; When no longer convergence or stop further search when having reached final temperature of search, get that the optimal location result exported as this step in the search;
(3) obtain the constraint condition that initial layout is summarized linear programming according to (2) step;
Wherein optimization aim is not change total area minimum under the original relative position condition, and objective function is:
Minimize…f＝λ
1·h
c+λ
2·w
c，
λ wherein
1, λ
2Dividing X is not simulated annealing layout result Aspect Ratio, h
c, w
cLength and width for layout;
The variable of linear programming is the position x of all modules
i, y
iWith length and width h
i, the length and width h of w and total arrangement
c, w
c
The described linear programming constraint condition of summarizing has four kinds: the range lambda of＜1〉module self length breadth ratio
Min＜h
i/ w
i＜λ
Max
＜2〉position constraint between the module: x
i+ w
i＜=x
jAnd y
i+ h
i＜=y
j＜3〉layout range constraint: x
i+ w
i＜=w
cAnd y
i+ h
i＜=h
c＜4〉parameter area constraint: x
i, y
i, w
i, h
i, w
c, h
c＞=0;
(4) obtain using mathematical tool Matlab built-in function that optimum solution is asked in linear programming after the objective function of linear programming and the constraint condition, be met the numerical value of all parameters when area is optimum under all constraint conditions: each module position x
i, y
i, length and width h
i, w and overall length and width h
c, w
c
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