CN1964189A - A device and method to eliminate signal burr - Google Patents
A device and method to eliminate signal burr Download PDFInfo
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Abstract
The disclosed device for eliminating signal burr includes a delay sampling circuit and a no-burr signal generator. Wherein, the relative method comprises: determining the delay level according to the maximal width of target burr to delay interface signal; taking logic ADD and logic OR operation to all delayed signal to obtain final signal. This invention has wide application range.
Description
Technical field
The present invention relates to the signal processing technology field, be specifically related to a kind of apparatus and method of eliminate signal burr.
Background technology
The progress of semiconductor technology makes that the electronic system operating frequency is more and more higher, and it is more and more to be integrated in the radio frequency on identical platform even the on-chip integration system (SoC), analog-and digital-member.Thereby the interface signal that causes chip more and more is vulnerable to disturb, and produces burr.So-called burr is exactly the signal of width less than the minimum widith of definition.How to eliminate burr and become the most general problem in the chip interface module design.
Fig. 1 has provided the process schematic diagram that burr produces, and as shown in Figure 1, generates input signal behind the input circuit of the output signal of chip 1 through output circuit, signal transmssion line and the chip 2 of chip 1, and is often jagged on this input signal.
The generation approach of burr mainly contains following three kinds:
Approach is jagged once, signal itself.As shown in Figure 1, when output signal 1,2 by register output, and when exporting, often just jagged in the output signal 1,2 by combinational logic.
When transmitting, approach two, signal produce burr on signal transmssion line.As shown in Figure 1, the radio noise source can induce burr on signal transmssion line, and perhaps the signal cross-talk between the signal transmssion line also can produce burr, or the like.
Approach three, signal also may produce burr after input circuit is handled.As shown in Figure 1, if be input to the rising edge of signal of chip 2 or the trailing edge duration is long as: reach the microsecond level, then the input signal 1,2 of input circuit output may produce burr near input circuit threshold value thresholding.
Fig. 2 has provided near signal produces burr input circuit threshold value thresholding schematic diagram, and as shown in Figure 2, Vin is the signal that is input to input circuit, and Vout is the signal of input circuit output, and Vht is the high level thresholding, when Vin＞=Vht, and Vout=1; Vlt is the low level thresholding, when Vin＜=Vlt, and Vout=0; And when Vht＞Vin＞Vlt, then Vout can not obtain stable numerical value, may also may be l for 0, thereby produce burr.As can be seen: have 3 burrs among Fig. 2.
Burr in the signal tends to cause the misoperation of subsequent logic, therefore, and the burr in the necessary erasure signal.The approach and the subsequent conditioning circuit characteristic separately that produce according to burr have a lot of burr removing methods.Wherein, at the approach that burr produces, following three kinds of methods of eliminating burr are arranged usually:
1), can require signal to export, and not export by combinational logic by register at approach one;
2) at approach two, can be when system design, the intensity and the distance of control source of radio-frequency interference, crosstalking between the control signal wire, or the like;
3), can on input circuit, add Schmidt's comparator at approach three.
If can not control each approach that burr produces, then need special circuit to eliminate burr.According to the different requirements of subsequent conditioning circuit to input signal, different burr removing methods is often arranged, for example:
1) synchronous as if requiring input signal and output signal, can only be concerned about that then clock is along near burr removal;
2) if subsequent conditioning circuit only is concerned about the rising edge or the trailing edge of the signal that is input to self, then can remove the burr on rising edge or the trailing edge specially;
3) if subsequent conditioning circuit is if only to the level signal sensitivity of input, then can adopt the method deburring of voting by a show of hands.
The main deficiency of the method for the above deburring is that every kind of method all is only applicable to specific application scenarios, is not a general burr removing method, and adaptive surface is narrower.
Summary of the invention
The invention provides a kind of apparatus and method of eliminate signal burr, to enlarge the range of application that burr is eliminated.
Technical scheme of the present invention is achieved in that
A kind of device of eliminate signal burr comprises: signal delay sample circuit and no burr signal generative circuit, wherein:
The signal delay sample circuit is used to receive the interface signal of waiting to eliminate burr, determines to postpone progression, according to the delay progression of determining this interface signal is postponed to handle, and the inhibit signal that delayed processing is obtained is input to no burr signal generative circuit;
No burr signal generative circuit is used for the inhibit signals at different levels of input are carried out logical AND operation and logic OR operation respectively, obtains carrot-free signal according to logic OR operating result and logical AND operating result.
Described signal delay sample circuit comprises: N+m latch, and, m is a natural number, N is the Breadth Maximum of waiting the to eliminate burr values that number obtains that round up after divided by Tclk-q, wherein, Tclk-q is the clock end of latch moment that effective edge occurs to the duration between the moment that the output of latch changes, wherein:
The data input pin of described each latch connects the significant level of described interface signal, and the interface signal of burr is eliminated in the clock end reception of first order latch, and reset terminal is by an inverter and wait that the interface signal of eliminating burr joins; The output of the clock termination previous stage latch of level latch after the second level and the second level, reset terminal joins by the output of an inverter and previous stage latch;
The output of the m+1～N+m level latch joins with no burr signal generative circuit.
Described no burr signal generative circuit comprises: with door or door and latch, wherein:
Be connected with the wherein one-level inhibit signal of signal delay sample circuit output respectively with each input of door;
Or each input of door is connected with the wherein one-level inhibit signal of signal delay sample circuit output respectively;
Or the output of door and the clock end of described latch join, and joins with the output of the door reset terminal by an inverter and described latch, and the data input pin of described latch connects the significant level of described interface signal.
Described latch is a d type flip flop.
A kind of method of eliminate signal burr comprises:
A, basis wait to eliminate the Breadth Maximum of burr, determine to postpone progression, treat the interface signal of eliminating burr according to this delay progression and postpone to handle;
B, the inhibit signals at different levels that delayed processing is obtained are carried out logical AND operation and logic OR operation respectively, obtain carrot-free signal according to logical AND operating result and logic OR operating result.
The described definite delay progression of steps A comprises:
M＝N+m，
Wherein, the delay progression of M for determining; N is the Breadth Maximum of waiting the to eliminate burr values that number obtains that round up after divided by Tclk-q, and wherein, Tclk-q is the clock end of latch moment that effective edge occurs to the duration between the moment that the output of latch changes; M is a natural number.
Described m is the arbitrary value between 0～10.
Described step B comprises:
The m+1～N+m level inhibit signal is carried out logical AND operation and logic OR operation respectively, when trailing edge appears in the logic OR operating result, determine that no burr signal begins to descend; When rising edge appears in the logical AND operating result, determine that burr signal begins to rise; When the logic OR operating result trailing edge and logical AND operating result do not occur and rising edge do not occur, determine that no burr signal remains unchanged.
Compared with prior art, the present invention is at first according to the Breadth Maximum of waiting to eliminate burr, determine to postpone progression, treating the interface signal of eliminating burr according to this delay progression postpones to handle, the inhibit signals at different levels that delayed processing is obtained are carried out logical AND operation respectively and logic OR is operated then, according to the be eliminated signal of burr of logical AND operating result and logic OR operating result.The present invention can remove wide accommodation for the burr that various approach produce.
Description of drawings
The process schematic diagram that Fig. 1 produces for burr;
Fig. 2 is near the schematic diagram that produces burr input circuit threshold value thresholding;
The installation drawing of the eliminate signal burr that Fig. 3 provides for the embodiment of the invention;
Fig. 4 is the oscillogram that embodiment of the invention burr is eliminated.
Embodiment
The present invention is further described in more detail below in conjunction with drawings and the specific embodiments.
The installation drawing of the burr in the erasure signal that Fig. 3 provides for the embodiment of the invention, as shown in Figure 3, it mainly comprises: signal delay sample circuit and no burr signal generative circuit, wherein:
Signal delay sample circuit: be used for the interface signal of eliminating burr of waiting of input is carried out N+m level delay processing, the delay duration of adjacent two-stage equals Tclk-q, will postpone to handle the m+1～m+N level inhibit signal that obtains through the m+1～N+m level and output to no burr signal generative circuit.
Here, Tclk-q is that the clock end of latch occurs effectively along promptly: the duration between the moment that the moment of rising edge or trailing edge to the output of latch changes; N is the Breadth Maximum of burr the to be eliminated values that number obtains that round up after divided by Tclk-q; M is a natural number, and m gets the value between 0～10 usually.The preceding m level latch operation of carrying out in the signal delay sample circuit is in order to eliminate the metastable state of interface signal.In the embodiment shown in fig. 3, N=3, m=2.
Particularly, if the original levels of interface signal is a high level, then effective edge of latch is a trailing edge; If the original levels of interface signal is a low level, then effective edge of latch is a rising edge.
No burr signal generative circuit: be used for the inhibit signal of the m+1～N+m level of receiving signal delayed sample circuit output, respectively this m+1～N+m level inhibit signal carried out logical AND operation and logic OR operation; And when trailing edge appears in the logic OR operating result, the no burr signal of determining final output begins to descend, when rising edge appears in the logical AND operating result, determine that no burr signal begins to rise, when the logic OR operating result trailing edge and logical AND operating result do not occur and rising edge do not occur, determine that no burr signal remains unchanged.
Below be example with Fig. 3, the concrete composition of signal delay sample circuit and no burr signal generative circuit is elaborated:
The signal delay sample circuit is made up of N+m latch, and wherein, N is the Breadth Maximum of burr the to be eliminated values that number obtains that round up after divided by Tclk-q; M is a natural number, and m gets the value between 0～10 usually.In Fig. 3, latch is a d type flip flop, and set N=3, m=2, then the signal delay sample circuit is by 5 d type flip flops: D1～D5 forms, wherein, D1～D2 is for removing the metastable state latch, and the significant level of interface signal is a low level among setting Fig. 3, and then effective edge of latch is a trailing edge, wherein:
The data input pin of each latch is all received the significant level of interface signal, and as shown in Figure 3, the data input pin of each d type flip flop is all received low level; First order latch as: the clock end of the D1 among Fig. 3 is received interface signal, and first order latch links to each other with interface signal by an inverter as: the reset terminal of the D1 among Fig. 3; The clock end of the latch that the second level and the second level are later links to each other with the output of previous stage latch, as: the clock end of the D2～D5 among Fig. 3 links to each other with the output of previous stage d type flip flop, the reset terminal of the latch that the second level and the second level are later links to each other by the output of an inverter and previous stage latch, as: the reset terminal of the D2～D5 among Fig. 3 links to each other by the output of an inverter and previous stage d type flip flop; The output of the m+1～N+m level latch links to each other with no burr signal generative circuit respectively, as: the output of the D3～D5 among Fig. 3 links to each other with no burr signal generative circuit respectively.
Here, the significant level of interface signal is determined in the following manner: if the original levels of interface signal is a high level, then its significant level is a low level; If the original levels of interface signal is a low level, then its significant level is a high level.
No burr signal generative circuit by with door or the door and latch form, in Fig. 3, latch is d type flip flop D6, wherein:
Link to each other with the output of the m+1～N+m level latch of signal delay sample circuit respectively with N input of door, as shown in Figure 3, link to each other with the output of d type flip flop D3～D5 in the signal delay sample circuit respectively with three inputs of door; Equally, or N input of door link to each other with the output of the m+1～N+m level latch of signal delay sample circuit respectively, as shown in Figure 3, or three inputs link to each other with the output of d type flip flop D3～D5 in the signal delay sample circuit equally respectively; The data input pin of latch is received the significant level of interface signal, as shown in Figure 3, the data input pin of trigger D6 is received low level, latch as: the clock end of the D6 among Fig. 3 with or the output of door link to each other, latch as: the reset terminal of the D6 among Fig. 3 passes through an inverter and links to each other with the output of door.
If the significant level of interface signal is a low level, below provide the course of work of signal delay sample circuit:
The basic composition unit of signal delay sample circuit is: latch.The course of work of each latch is: when trailing edge appearred in the input signal of clock end, this trailing edge drove the level-low level of latches data input pin, and then, behind the Tclk-q duration, trailing edge appears in the output of this latch; When rising edge appearred in the input signal of clock end, this high level became low level through behind the inverter, and latch carries out asynchronous low level and resets, and then, behind the Tclk-q duration, rising edge appears in the output of latch.
Below provide the course of work of no burr signal generative circuit:
With door the inhibit signals at different levels of signal delay sample circuit output are carried out the logical AND operation, or door carries out the logic OR operation to the inhibit signals at different levels of signal delay sample circuit output;
When trailing edge appearred in the output of logic sum gate, this trailing edge drove the data input pin level-low level of the latches self in the no burr signal generative circuit, and then, behind the Tclk-q duration, trailing edge appears in the output of latch;
When rising edge appearred in the output of logical AND gate, this high level became low level behind inverter, and latch carries out asynchronous low level and resets, and then, behind the Tclk-q duration, rising edge appears in the output of latch;
When rising edge did not appear in the output that trailing edge and logical AND gate do not occur when the output of logic sum gate, behind the Tclk-q duration, the output of latch trailing edge neither can occur, also rising edge can not occur, but remains unchanged.
With Fig. 3 is example, Fig. 4 provided the output signal of the interface signal that needs deburring, each d type flip flop D1～D5, with the elimination of the output signal of the output signal of door or door and d type flip flop D6 output the waveform schematic diagram of signal of burr, wherein, the significant level of interface signal is a low level, as shown in Figure 4, as can be seen: the burr in the interface signal all is removed.
Latch among the present invention also can use the element beyond the d type flip flop to replace, as long as this element can be realized the delayed latch to signal.
In the present invention, for the latch that adopts 130 nanometer technology conditions, the Tclk-q duration was 0.2 nanosecond, and at this moment, the manageable highest frequency of waiting to eliminate the signal of burr is 1.67GHz.
The above only is process of the present invention and method embodiment, in order to restriction the present invention, all any modifications of being made within the spirit and principles in the present invention, is not equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (8)
1, a kind of device of eliminate signal burr is characterized in that, comprising: signal delay sample circuit and no burr signal generative circuit, wherein:
The signal delay sample circuit is used to receive the interface signal of waiting to eliminate burr, determines to postpone progression, according to the delay progression of determining this interface signal is postponed to handle, and the inhibit signal that delayed processing is obtained is input to no burr signal generative circuit;
No burr signal generative circuit is used for the inhibit signals at different levels of input are carried out logical AND operation and logic OR operation respectively, obtains carrot-free signal according to logic OR operating result and logical AND operating result.
2, device as claimed in claim 1, it is characterized in that, described signal delay sample circuit comprises: N+m latch, and, m is a natural number, and N is the Breadth Maximum of waiting the to eliminate burr values that number obtains that round up after divided by Tclk-q, wherein, Tclk-q is the clock end of latch moment that effective edge occurs to the duration between the moment that the output of latch changes, wherein:
The data input pin of described each latch connects the significant level of described interface signal, and the interface signal of burr is eliminated in the clock end reception of first order latch, and reset terminal is by an inverter and wait that the interface signal of eliminating burr joins; The output of the clock termination previous stage latch of level latch after the second level and the second level, reset terminal joins by the output of an inverter and previous stage latch;
The output of the m+1～N+m level latch joins with no burr signal generative circuit.
3, device as claimed in claim 1 or 2 is characterized in that, described no burr signal generative circuit comprises: with door or door and latch, wherein:
Be connected with the wherein one-level inhibit signal of signal delay sample circuit output respectively with each input of door;
Or each input of door is connected with the wherein one-level inhibit signal of signal delay sample circuit output respectively;
Or the output of door and the clock end of described latch join, and joins with the output of the door reset terminal by an inverter and described latch, and the data input pin of described latch connects the significant level of described interface signal.
4, device as claimed in claim 1 is characterized in that, described latch is a d type flip flop.
5, a kind of method of eliminate signal burr is characterized in that, comprising:
A, basis wait to eliminate the Breadth Maximum of burr, determine to postpone progression, treat the interface signal of eliminating burr according to this delay progression and postpone to handle;
B, the inhibit signals at different levels that delayed processing is obtained are carried out logical AND operation and logic OR operation respectively, obtain carrot-free signal according to logical AND operating result and logic OR operating result.
6, method as claimed in claim 5 is characterized in that, the described definite delay progression of steps A comprises:
M＝N+m，
Wherein, the delay progression of M for determining; N is the Breadth Maximum of waiting the to eliminate burr values that number obtains that round up after divided by Tclk-q, and wherein, Tclk-q is the clock end of latch moment that effective edge occurs to the duration between the moment that the output of latch changes; M is a natural number.
7, method as claimed in claim 6 is characterized in that, described m is the arbitrary value between 0～10.
8, as claim 5 or 6 described methods, it is characterized in that described step B comprises:
The m+1～N+m level inhibit signal is carried out logical AND operation and logic OR operation respectively, when trailing edge appears in the logic OR operating result, determine that no burr signal begins to descend; When rising edge appears in the logical AND operating result, determine that burr signal begins to rise; When the logic OR operating result trailing edge and logical AND operating result do not occur and rising edge do not occur, determine that no burr signal remains unchanged.
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| CNB2006101609224A CN100508391C (en) | 2006-12-01 | 2006-12-01 | A device and method to eliminate signal burr |
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| CN102594305A (en) * | 2011-01-17 | 2012-07-18 | 上海华虹集成电路有限责任公司 | Digital burr filtering circuit for clock pins of smart card |
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