CN112364582A - Improved method, system and device for verifying tri-state gate circuit - Google Patents
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Abstract
The invention discloses an improved method for verifying a tri-state gate circuit, which comprises the following steps: dividing logic cones of the reference circuit and the tri-state gate enable end input circuit of the implementation circuit; matching the comparison points according to the matching rule; establishing a reference circuit and an MITER for realizing a comparison point of a logic cone of the circuit; converting the circuit file after the mitter into a conjunctive normal form which can be processed by an SAT algorithm for verification; if the verification result shows that the two circuits are equivalent, the enabling end is assumed to be effective, otherwise, the inequivalent circuits are directly output. The invention is an improved version based on the traditional scheme, can avoid the problem that the enable end of the tri-state gate in the original scheme is not equivalent, and can improve the verification accuracy of the tri-state gate by combining the scheme and the traditional scheme. Through a series of steps of logic cone division, comparison point matching, SAT verification and the like of the enabling end circuit, the hypothesis before the verification of the tri-state gate can be completely supplemented, and the verification scheme of the original tri-state gate circuit is perfected.
Description
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to an improved method, system and device for verifying a tri-state gate circuit.
Background
With the development of information technology and the increase of data transmission amount, bidirectional bus transmission in very large scale integrated circuits plays an increasingly important role, and is generally used for data transmission, such as: data transfer between the CPU and memory and input and output interfaces and is therefore widely used in processor integrated circuits. Since the basic gate circuit constituting the multi-path bidirectional bus transmission includes a tri-state gate in addition to a basic circuit such as an nand gate, the tri-state gate circuit is considered when verifying the equivalence of the bidirectional bus transmission circuit.
The basic principle of the tri-state gate is: when the enable end of the tri-state gate is in an effective state, the output end and the input end are kept consistent; when the enable end of the tri-state gate is invalid, the output end always keeps a high-impedance state no matter a high level or a low level is input. The main scheme for verifying tri-state gates at present is: assuming the enable is valid, the tri-state gate is verified as a buffer. However, this assumption is made on the premise that the enable terminal circuit is equivalent, otherwise, this assumption is not true, as shown in fig. 1, when the CPU (a terminal) transfers data to the memory (B terminal), it needs to enable the enable terminal of the tri-state gate T1, and disable the enable terminal of the tri-state gate T2; when data transmission is not needed, the T1 and T2 enabled terminals are required to be invalid. In this case, if T1 and T2 are simultaneously assumed to be valid, a data transmission collision occurs, which does not match the circuit actual situation.
In addition, when the bus is transmitting, the truth table relationship between its inputs and the T1 and T2 enables is shown in Table one:
truth table relationship between input and enable terminals when the first enable terminal is equivalent
In this case, assuming that the enable of T1 is valid, it can be inferred that the Input must be 0 at Input1 and 1 at Input2, and the same reasoning holds for T2, i.e. the enable of a tri-state gate is valid and the Input to the circuit is a set of defined correspondences. However, the circuit shown in fig. 2 can be seen from the truth table (table two):
when the enable terminal of the second table is not equivalent, the truth table relationship between the input terminal and the enable terminal
When the enable of T1 is asserted, the inputs may be Input1 is 0 and Input2 is 1 or Input1 is 1 and Input2 is 0, i.e. the enable of a tri-state gate is asserted and the inputs of the circuit are not a certain set of correspondences. In this case, assuming that the enable terminal is enabled and then verified, it is equivalent to consider the Input1 and Input2 Input circuits of fig. 1 and 2 to be equivalent, but obviously these are two completely different circuits, so it is not feasible to verify under this premise.
Therefore, a need exists for an improved method, system, and apparatus for tri-state gate verification that addresses the above-mentioned problems.
Disclosure of Invention
In view of the above, the present invention provides an improved method, system and apparatus for tri-state gate verification to solve the above-mentioned problems in the background art.
In order to achieve the purpose, the invention provides the following technical scheme: an improved method for tri-state gate circuit verification, the method comprising:
dividing logic cones of the reference circuit and the tri-state gate enable end input circuit of the implementation circuit;
matching the comparison points according to the matching rule;
establishing a reference circuit and an MITER for realizing a comparison point of a logic cone of the circuit;
converting the circuit file after the mitter into a conjunctive normal form which can be processed by an SAT algorithm for verification; if the verification result shows that the two circuits are equivalent, the enabling end is assumed to be effective, otherwise, the inequivalent circuits are directly output.
Further, the performing logic cone segmentation includes the following steps:
backtracking scanning is started from an output port as a cone top until a last comparison point is met to form a logic cone;
and taking the cone bottom of the logic cone as the cone top of the next logic cone, and scanning the next logic cone until the whole circuit is divided into logic cone sub-circuits.
Further, the comparing point matching according to the matching rule specifically includes:
and matching the comparison points of the logic cones in the reference circuit and the implementation circuit according to a certain rule, and carrying out the next verification only on the logic cones which are matched consistently.
Furthermore, the matching rules comprise precise name matching, name filtering and comprehensive use of a plurality of rules for matching together, and finally the logic cone matching is consistent.
Further, the designator for establishing the comparison point of the reference circuit and the logic cone of the implementation circuit is specifically:
and connecting the matched reference circuit with the logic cone vertex of the implementation circuit by using an exclusive-OR gate.
Further, the step of converting the circuit file after the MITTER into a conjunctive norm that can be processed by the SAT algorithm includes the following steps:
the input is connected with the input in an OR operation;
a plurality of inputs form a clause through OR operation;
clauses are connected with each other through operations;
the plurality of clauses form the whole conjunctive expression through the AND operation.
An improved system for tri-state gate circuit verification, the system comprising:
the dividing unit is used for dividing the logic cone of the reference circuit and the tri-state gate enable end input circuit of the implementation circuit;
the matching unit is used for matching the comparison points according to the matching rule;
the MITER unit is used for establishing a reference circuit and realizing the MITER of a comparison point of the logic cone of the circuit;
the verification unit is used for converting the circuit file after the MITTER into a conjunctive normal form which can be processed by an SAT algorithm for verification;
and the judging unit is used for judging the verification result, if the verification result shows that the two circuits are equivalent, the enabling end is assumed to be effective, and otherwise, the inequivalent circuits are directly output.
An improved apparatus for tri-state gate verification, the apparatus comprising at least one processor and at least one memory;
the memory stores a computer program that performs the above-described method, and the processor calls the computer program in the memory to perform the above-described method.
The invention has the technical effects and advantages that:
the invention is an improved version based on the traditional scheme, can avoid the problem that the enable end of the tri-state gate in the original scheme is not equivalent, and can improve the verification accuracy of the tri-state gate by combining the scheme and the traditional scheme. Compared with the direct hypothesis verification in the traditional scheme, the scheme can completely supplement the hypothesis before verifying the tri-state gate by a series of steps of logic cone division, comparison point matching, SAT verification and the like of the enabling end circuit, perfects the verification scheme of the original tri-state gate circuit, is easy to realize, and can be conveniently applied to an electronic design automation tool.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without creative efforts.
FIG. 1 shows an equivalent schematic diagram of a prior art tri-state gate enable end circuit;
FIG. 2 illustrates an equivalent schematic diagram of a prior art tri-state gate enable side circuit;
FIG. 3 shows a flow diagram of an improved method for verification of a tri-state gate circuit of an embodiment of the present invention;
FIG. 4 shows a logic cone circuit schematic of an embodiment of the present invention;
FIG. 5 illustrates a schematic diagram of the miter circuit of an embodiment of the present invention;
FIG. 6 is a schematic diagram illustrating logical partitioning of a reference circuit and an implementation circuit according to an embodiment of the present invention;
FIG. 7 illustrates a designator diagram of a logic cone of a reference circuit and an implementation circuit in accordance with an embodiment of the present invention;
fig. 8 is a schematic diagram of a conjunctive normal form obtained through variant derivation according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention provides an improved method for verifying a tri-state gate circuit, which comprises the following five steps as an example as shown in FIG. 3:
the first step is as follows: dividing logic cones of the reference circuit and the tri-state gate enable end input circuit of the implementation circuit;
the second step is that: matching the comparison points according to the matching rule;
the third step: establishing a reference circuit and an MITER for realizing a comparison point of a logic cone of the circuit;
the fourth step: converting the circuit file after the mitter into a conjunctive normal form which can be processed by an SAT algorithm for verification;
the fifth step: if the verification result shows that the two circuits are equivalent, the enabling end is assumed to be effective, the tri-state gate is used as a buffer to verify the logic cone built by the tri-state gate again, and otherwise, the inequivalent circuits are directly output.
In the verification method, the problem that an input circuit is not equivalent under the condition that an enabling end is assumed to be effective in the traditional scheme can be solved by using the logic cone segmentation, and the memory overhead of the system can be reduced by using the SAT algorithm to solve the conjunctive and conjunctive norm, so that the verification process is ensured to be carried out smoothly.
In the embodiment of the present invention, a logic cone refers to a circuit included between a certain comparison point in a circuit and a previous comparison point when the comparison point is reached. The comparison point for starting backtracking is called the cone top, and the comparison point for stopping backtracking is called the cone bottom. In the verification problem of the tri-state gate, the vertex is the enable terminal of the tri-state gate, and the bottom is all input ports to the enable terminal of the tri-state gate, as shown in fig. 4. The logic cone segmentation process comprises the following steps: and backtracking scanning is started from an output port serving as a cone top, backtracking is stopped until a last comparison point is met, the part of the circuit of the cone is the logic cone, then the cone bottom of the logic cone is used as the cone top of the next logic cone, and scanning of the next logic cone is carried out until the whole circuit is divided into logic cone sub-circuits, so that the verification of the whole circuit can be decomposed into superposition of the verification of each logic cone.
In the embodiment of the invention, the comparison point matching refers to that after the reference circuit and the implementation circuit respectively carry out logic cone segmentation, the comparison points of each logic cone in the two circuits are matched according to a certain rule, and the logic cones which are matched in a consistent way can be subjected to the next verification. The common matching rules comprise accurate name matching, name filtering and the like, and a plurality of rules can be comprehensively used for matching together during matching, so that the logic cone matching is consistent finally.
In the embodiment of the present invention, the mitter refers to connecting the matched reference circuit and the logic cone vertex of the implementation circuit by using an exclusive or gate, as shown in fig. 5, in the case of the same input, if the combination of a group of inputs makes the output "1", it means that the two circuits are not equivalent, and conversely, if the final output of the circuit after trying the combination of all the inputs is "0", it proves that the two circuits are equivalent.
In the embodiment of the present invention, the SAT technique refers to solving the boolean satisfiability problem, and solving the boolean satisfiability problem refers to: attempting to find a combination of a set of boolean variables such that the entire expression results in a "1" indicates that the problem is satisfied, and if an exhaustive list of all combinations does not find a solution that the problem is not satisfied, which corresponds to the meaning in the circuit: if the circuit file after miter can find a group of input combinations so that the output is 1, the two circuits are not equivalent, otherwise, the two circuits are equivalent. The SAT technology is an algorithm for trying to find an unsatisfiable boolean variable combination, and a problem to be processed by the algorithm is presented in a conjunctive normal form, and the conjunctive normal form is specifically expressed as follows: variables are connected with each other through OR operation, a plurality of variables form a clause through OR operation, clauses are connected with each other through OR operation, and a plurality of clauses form the whole conjunctive normal form through AND operation. Such as: for such a conjunctive normal form: (a V is advanced just C) inverted V (| V, after), there is the combination of a set of variable: a is 1, b is 0, c is 1, making the equation "1", then this conjunctive normal form is satisfied, its set of solutions is: a =1, b =0, c = 1.
Illustratively, the scheme of the embodiment of the present invention will be described in detail by taking the tri-state gate circuit for verifying bidirectional bus transmission as an example.
Dividing the logic structures of the reference circuit and the implementation circuit according to the structure of the logic cone, as shown in fig. 6, obtaining the comparison points of the enable end circuits of the tri-state gates respectively, and then matching the obtained comparison points of the logic cone, where the purpose of this step is to specify the logic cone to be compared between the two circuits, and the following process is the circuit designatorer, as shown in fig. 7: connecting the tops of the two logic cones through an exclusive-or gate, adding the same Input port to the bottom of the logic cones, and then converting a Conjunctive Normal Form (CNF) file to a miter circuit, where in this embodiment, the circuit expression after the miter is Out = (| _ Input1 ^ Input2) | (Input1 | _ Input2), and the conjunctive normal form can be obtained through conversion deformation: out = Input1 ^ Input2, it is clear that when Input1=1 and Input2=0, Out is 1, which is then satisfactory for the problem, but not equivalent for the two circuits, thus directly outputting the circuits in the logic cone that are not equivalent; for the circuit of fig. 8, a conjunctive normal form is obtained through deformation derivation, and then the problem can be solved through analysis, that is, the two circuits are equivalent, and then the assumption of the enabling end of the tri-state gate is verified effectively by adopting the original scheme.
The present invention also provides an improved system for tri-state gate circuit verification, the system comprising:
the dividing unit is used for dividing the logic cone of the reference circuit and the tri-state gate enable end input circuit of the implementation circuit;
the matching unit is used for matching the comparison points according to the matching rule;
the MITER unit is used for establishing a reference circuit and realizing the MITER of a comparison point of the logic cone of the circuit;
the verification unit is used for converting the circuit file after the MITTER into a conjunctive normal form which can be processed by an SAT algorithm for verification;
and the judging unit is used for judging the verification result, if the verification result shows that the two circuits are equivalent, the enabling end is assumed to be effective, and otherwise, the inequivalent circuits are directly output.
The present invention also provides an improved apparatus for tri-state gate verification, the apparatus comprising at least one processor and at least one memory;
the memory stores a computer program that performs the above-described method, and the processor calls the computer program in the memory to perform the above-described method.
The embodiment of the invention is an improved version based on the traditional scheme, can avoid the problem that the enabling end of the tri-state gate in the original scheme is not equivalent, and can improve the verification accuracy of the tri-state gate by combining the scheme and the traditional scheme. Compared with the direct hypothesis verification in the traditional scheme, the scheme can completely supplement the hypothesis before verifying the tri-state gate by a series of steps of logic cone division, comparison point matching, SAT verification and the like of the enabling end circuit, perfects the verification scheme of the original tri-state gate circuit, is easy to realize, and can be conveniently applied to an electronic design automation tool.
Although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (8)
1. An improved method for tri-state gate verification, the method comprising:
dividing logic cones of the reference circuit and the tri-state gate enable end input circuit of the implementation circuit;
matching the comparison points according to the matching rule;
establishing a reference circuit and an MITER for realizing a comparison point of a logic cone of the circuit;
converting the circuit file after the mitter into a conjunctive normal form which can be processed by an SAT algorithm for verification; if the verification result shows that the two circuits are equivalent, the enabling end is assumed to be effective, otherwise, the inequivalent circuits are directly output.
2. The improved method for verification of tri-state gate circuits as claimed in claim 1 wherein said performing logic cone splitting comprises the steps of:
backtracking scanning is started from an output port as a cone top until a last comparison point is met to form a logic cone;
and taking the cone bottom of the logic cone as the cone top of the next logic cone, and scanning the next logic cone until the whole circuit is divided into logic cone sub-circuits.
3. The improved method for verification of tri-state gate circuits as claimed in claim 2 wherein said matching comparison points according to matching rules is specifically:
and matching the comparison points of the logic cones in the reference circuit and the implementation circuit according to a certain rule, and carrying out the next verification only on the logic cones which are matched consistently.
4. The improved method for verification of tri-state gate circuits as claimed in claim 3 wherein said matching rules include exact name matching, name filtering, and using multiple rules together for matching, eventually achieving consistent logic cone matching.
5. The improved method for verification of a tri-state gate circuit as claimed in claim 1, wherein the designatorer for establishing the comparison point of the reference circuit and the logic cone of the implementation circuit is specifically:
and connecting the matched reference circuit with the logic cone vertex of the implementation circuit by using an exclusive-OR gate.
6. The improved method for tri-state gate verification as claimed in claim 1 wherein the step of converting the circuit file after mitter to a conjunctive norm processable by the SAT algorithm comprises the steps of:
the input is connected with the input in an OR operation;
a plurality of inputs form a clause through OR operation;
clauses are connected with each other through operations;
the plurality of clauses form the whole conjunctive expression through the AND operation.
7. An improved system for tri-state gate verification, the system comprising:
the dividing unit is used for dividing the logic cone of the reference circuit and the tri-state gate enable end input circuit of the implementation circuit;
the matching unit is used for matching the comparison points according to the matching rule;
the MITER unit is used for establishing a reference circuit and realizing the MITER of a comparison point of the logic cone of the circuit;
the verification unit is used for converting the circuit file after the MITTER into a conjunctive normal form which can be processed by an SAT algorithm for verification;
and the judging unit is used for judging the verification result, if the verification result shows that the two circuits are equivalent, the enabling end is assumed to be effective, and otherwise, the inequivalent circuits are directly output.
8. An improved apparatus for tri-state gate verification, the apparatus comprising at least one processor and at least one memory;
the memory stores a computer program for performing the method of any of claims 1-6, and the processor calls the computer program in the memory to perform the method of any of claims 1-6.
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| WO2023272424A1 (en) * | 2021-06-28 | 2023-01-05 | 华为技术有限公司 | Circuit verification method and apparatus based on automatic test pattern generation |
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