CN1560769A - Cmbined circuit equipment checking method based on satisfiability - Google Patents
Cmbined circuit equipment checking method based on satisfiability Download PDFInfo
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Abstract
The invention relates to designing and testing technology field of very large scale integrating circuit, namely equivalence testing method. The method uses satisfiability arithmetic as the engine, tests the whole circuit design, the method has two segments, the first segment is to determine the candidate equal signal in the two circuits, and through the circuits structure analysis, carries on static sift to the candidate equal signal, the second segment is to realize gain satisfiability method through clause group, and tests the equivalence of the candidate signal. The main character of the invention is: 1) selects the candidate equal signal in the circuit through circuit structure analysis, selects the cut or centralized equal signal dynamically in the process of test, and guarantees the signal is independent from each other. 2) Realizes the satisfiability arithmetic through grouping the clause saves the calculating resources, upgrades the arithmetic performance and the processing ability.
Description
Technical field
The present invention relates to the design verification technical field of VLSI (very large scale integrated circuit), particularly a kind of formalization verification method of combinational circuit equivalence checking method, the especially combinational circuit based on satisfiability.It screens candidate's equivalent signal of circuit inside by circuit structural analysis, and utilizes increment satisfiability algorithm to improve the performance of combinational circuit equivalence checking method, has greatly improved the processing power of method.
Background technology
Along with the increase day by day of integrated circuit (IC) design scale and complexity, the functional verification of system has become the bottleneck of whole design cycle.Simulation is the most frequently used function verification method.Yet for current large-scale, somewhat complex design, use simulation to need a large amount of working times separately, and be incomplete method, the design mistake at some edge is difficult to detect.At present, formal verification method has developed into the important supplement of simulation verification method gradually.The formal verification method is the function correctness that proves design by mathematical method, and it does not need to produce test and excitation, and 100% function coverage can be provided again, can save a large amount of proving times, shortens the whole design cycle.The formal verification method roughly can be divided three classes: equivalence checking, model testing, theorem proving.The formal approach of at present using morely in the electronic design automation tool of reality is an equivalence checking, promptly verifies two function equivalences between the multi-form design, and this is the main contents that the present invention relates to.In the integrated circuit (IC) design flow process, equivalence checking can be used to verify the function equivalence between register transfer level (RTL) model and gate-level model, gate-level model and gate-level model, RTL model and the RTL model, thereby find design mistake as early as possible, guarantee the design function correctness in each stage on stream.
In the large scale integrated chip design of reality, contain a large amount of storage element (trigger), frequent based on the classic method of finite state machine traversal owing to state space leads to the failure too greatly.Therefore the equivalence checking instrument of most of reality often uses the method for combined authentication to verify large-scale sequential circuit, promptly at first construct a mapping between each register or the latch, thereby sequential circuit is resolved into the composite module of a plurality of correspondences, then whether corresponding each composite module of checking is of equal value, if each composite module is all of equal value, entire circuit is exactly a function equivalence so.Therefore, we can say that combined authentication is one of core of form equivalence checking.Yet when chip-scale was too big, the formal verification method was still unsatisfactory, and the blast of overtime or internal memory is failed because of algorithm sometimes, how to improve algorithm performance and processing power is still urgent problem.
At present combination equivalence checking method great majority are be main engine with y-bend decision diagram (BDD), other method then be mainly used to deduce inner equivalent signal or eliminate and judge by accident.In fact, many efficient, practical programs have appearred in the research that deepens continuously along with to the SAT algorithm, and the SAT algorithm possesses the advantage that some BDD lack, if we can make full use of these advantages, might construct more strong, equivalence checking method flexibly fully.The present invention proposes a kind of combinational circuit increment equivalence checking method, the technology below this method has absorbed in this piece document based on satisfiability:
“Verification?of?Large?Synthesized?Designs，”Daniel?Brand，In?Proceedings?of?International?Conference?on?Computer-aidedDesign，pp.534-537，1993。
Above-mentioned document has proposed the circuit dividing method based on substitutability, utilizes the structural similarity of circuit inside, the function equivalence of two circuit of increment ground checking.The substitutability here is to produce (ATPG) instrument by automatic test to derive, and reduce candidate's equivalent signal table with traditional failure simulation method, computational complexity is higher, and greatly depends on the structural similarity that is verified circuit, for some real design failure probably.Show by a large amount of experiments,, will have a strong impact on algorithm performance, must screen by certain didactic strategy if candidate's equivalent signal is too many.In addition, when deriving inner equivalence, need make full use of known relation of equivalence, and prevent that proof procedure from becoming too complicated backward.The present invention has used the method for innovation to solve the problems referred to above, has greatly improved the performance and the processing power of algorithm, and can be conveniently used in the design automation tool.Therefore, has higher utility.
Summary of the invention
The present invention proposes a kind of combinational circuit equivalence checking method based on satisfiability.It is to utilize the circuit inner structure similarity, is engine with the satisfiability algorithm, the function equivalence of two circuit of increment ground checking.For principle and the innovation part of further illustrating method, at first introduce basic concepts.Satisfiability problem is meant and finds a variable assignments to make that given Boolean function is satiable, or proves that such assignment does not exist.In order to solve conveniently, the SAT problem is usually used conjunctive normal form (CNF) formula.The set that the CNF formula is made up of some clauses, each clause in the set is extracting by some variablees or their negative (being called literal) formation.The CNF formula of logical circuit is the set that the CNF formula of each constitutes, and the CNF formula of each is easy to derive.As one with a door a=bc, can be expressed as that (a) (c+ ﹁ is (﹁ b+ ﹁ c+a) a), and it comprises three clauses for b+ ﹁.Equivalence checking is meant, under the one-to-one relationship situation between known two circuit input and the output, verifies that their output function (Boolean function) is a function equivalence.Sometimes also be referred to as logic checking or boolean relatively.Might as well use function F (X) expression standard circuit, and realize circuit with G (X) expression, be example with single output circuit, in order to verify F (X)=G (X), a very natural idea is only to need the XOR value of two circuit outputs of proof to be fixed as 0, i.e. F (X) G (X)=0.As shown in Figure 1, claim in the list of references of front that this structure is miter.Usually in the design cycle, two circuit that are in different phase may comprise many structural similarities, therefore, can utilize these similaritys to simplify the miter structure, thereby improve the performance of algorithm.For example, as shown in Figure 2, suppose that f and g are respectively from standard with a pair of candidate's equivalent signal in realizing, and be proved to be certain equivalence.In the subsequent authentication process, can replace f so, thereby simplify the miter structure, as shown in Figure 3 with g.Here the equivalence of f and g also is by similar method validation, verifies that promptly their XOR value is fixed as 0.
A large amount of experiments show, if candidate's equivalent signal all can have a strong impact on the performance of algorithm to too much or very little.In addition, if directly use the equivalence that traditional atpg tool is verified M signal, for large-scale design, the working time that needs are a large amount of.The present invention is intended to by certain strategy candidate signal be screened, and reduces the unnecessary candidate signal of a part, avoids frequently calling of satisfiability program; In order fully to use known inside equivalence, use increment satisfiability algorithm to improve algorithm performance.Experiment shows, the method that the present invention proposes than in the past most methods fast.Because in the integrated circuit (IC) design flow process, the many structural similarities of normal reservation between the different editions of design, simultaneously, increasingly mature to the research of satisfiability algorithm both at home and abroad at present, many routine packages have efficiently appearred, the method that the present invention proposes can integrate with these routine packages easily, therefore has broad application prospects.
The invention technical scheme
A kind of combinational circuit equivalence checking method based on satisfiability, described method has two stages, phase one is candidate's equivalent signal of determining two circuit inside, and pass through circuit structural analysis, candidate's equivalent signal is made static filtering, subordinate phase is to divide into groups to realize increment satisfiability method by the clause, and verifies the equivalence of every pair of candidate signal.
Phase one is to determine candidate's equivalent signal, and by circuit structural analysis, candidate signal is made static filtering, and its concrete steps are as follows:
The first step: the method for parallel stochastic simulation of use or name-matches is found out candidate's equivalent signal of two circuit inside, every response characteristic (signature) two signals identical or name-matches (one from the standard circuit, and another is from realizing circuit) are used as a pair of candidate's equivalent signal;
Second step: candidate's equivalent signal is carried out static filtering, if the fan-in number of certain signal is less than 2 in the standard circuit, it is right to delete these corresponding all candidate signals of signal institute so, in addition, if the original input number that certain candidate signal b of signal a relies in the standard circuit is more than a, it is right to delete this candidate signal so.
Subordinate phase is to divide into groups to realize increment satisfiability method by the clause, and the equivalence of checking candidate signal, and its concrete steps are as follows:
1) in the proof procedure phase one candidate signal is made screening after, construct the CNF formula of whole realization circuit, as permanent clause's group;
2) Dynamic Selection is divided cut set, verifies the equivalence of every pair of candidate signal, has dependence if cut apart concentrated signal, be that certain signal is the fan-out signal of other signal, concentrate this signal of deletion from cutting apart so, in addition, select the many signals of fan-in number to enter as far as possible and cut apart set;
3) divide into groups to realize increment satisfiability algorithm by clause to the CNF formula, after a pair of signal of checking is equivalence, with the equivalent signal in the Signal permuting standard circuit of realizing in the circuit, for representing known relation of equivalence, increase corresponding CNF clause to permanent clause's group, CNF formula in the standard circuit then is dynamically to construct (as other clause's group), and can increase and decrease as required.
The format circuit that the method that the present invention proposes is handled is gate level netlist (logical circuit), in fact, for the description of register transfer level, all is by certain means generally in the business tool at present, converts thereof into gate level netlist, verifies again.Describe the embodiment of this method below in detail, Fig. 4 has provided the overall procedure of this method.
Description of drawings
Fig. 1 has provided the miter structural model of checking two circuit (standard and realization) function equivalences.
Fig. 2 is the synoptic diagram of checking internal candidates equivalent signal.
Fig. 3 has described the process of corresponding equivalent signal in the Signal permuting standard of using in realizing.
Fig. 4 has described the overall procedure of the method for the present invention's proposition.
Fig. 5 has provided a simple example, i.e. standard circuit and realization circuit.
Fig. 6 has described the process that displacement based on equivalent signal comes two circuit that proof diagram 5 provides.
Embodiment
The implication of each label is as follows in the accompanying drawing:
1: corresponding square frame is represented the design specifications circuit.
2: XOR gate.
3: corresponding square frame representative realizes circuit.
4: with door.
5: or door.
6: not gate.
In addition, in the accompanying drawing 4, S1, S2, S3, S4, S5 correspond respectively to five steps in the technological invention scheme.
In the accompanying drawing 1, (1) is to represent the design specifications circuit.(3) be that representative realizes circuit.In order to verify the signal equivalence of two correspondences, only these two signals need be connected to an XOR gate (2), the output that proves this XOR gate then is fixed as 0 fault and can not surveys.It should be noted that when using the satisfiability proof of algorithm, do not need to realize this connection physically, and just construct corresponding C NF formula clause.
In the accompanying drawing 2, in order to verify the equivalence of two candidate signals, the XOR value that needs to use these two signals of satisfiability proof of algorithm is fixed as 0.As previously described, same needs to increase corresponding C NF formula clause.
In the accompanying drawing 3, by the continuous displacement of inner equivalent signal, the miter structure becomes more and more simpler, thus make the subsequent authentication process more simplify, easier.
Accompanying drawing 4 has been described the overall procedure of the method for the present invention's proposition, and the first step is carried out classification to two circuit and handled; Second step was determined candidate's equivalent signal of two circuit; The 3rd step was screened candidate's equivalent signal by circuit structural analysis; The 4th step was verified the equivalence of each candidate's equivalent signal according to the fan-in priority ranking; Final step checks whether each is of equal value to the original output signal of candidate.Concrete steps are as follows:
S1: two circuit that are verified are carried out classification handle.Original input signal is the 0th grade, and other non-arbitrarily original input signal a is classified as l (a)= b{max (l (b))+1, and b is the fan-in signal of a }.Then, all circuit signals are pressed place classification series arrangement from small to large.
S2: find out two internal candidates equivalent signal that are verified circuit (standard and realization).At first use identical random vector that two circuit are made Parallel Simulation simultaneously, store the response characteristic of each circuit signal.To the ordering traversal of each signal in the standard circuit by the S1 step, for arbitrary signal a, if realize that certain the signal b in the circuit is identical with signal a name-matches or analog response feature, signal b is candidate's equivalent signal of signal a so then.Note, may in realizing circuit, have candidate's equivalent signal that a plurality of signals are a.In addition, in this step, do not have corresponding candidate's equivalent signal if find certain original output signal, illustrated that so two circuit are non-equivalences, algorithm so far finishes.
S3: candidate's equivalent signal that previous step obtains is carried out static filtering.Each signal in the traversal standard circuit, carry out following circuit structural analysis:
1), from candidate list, deletes all so and comprise candidate's equivalent signal of signal a (except the original output signal) if the fan-in number of signal a is less than 2.
2) if the original input number that certain candidate signal of signal a relies on is more than a, it is right to delete this candidate signal so.
S4:, call each equivalence of increment satisfiability proof of algorithm to candidate signal by the preferential order of fan-in.This step is the core procedure of our method, and this method has been used two main policies: Dynamic Selection is cut apart set, the right equivalence of increment checking candidate signal; The satisfiability algorithm that divides into groups to realize increment by the clause.Detailed process is as follows:
2) make conjunctive normal form (CNF) formula of realizing circuit,, avoid the CNF formula of repetitive construct same signal as permanent clause's group.
2) dynamically adjust candidate's equivalent signal of cutting apart in the set.(a b), supposes that a is the signal in the standard circuit, and b is the signal of realizing in the circuit for every pair of candidate signal.The CNF formula of structure a b is done depth-first search for the fan-in logic cone of a, and till running into original input or known equivalent signal, we are referred to as these signals and are one and cut apart set.Note, in the described in front permanent clause's group of the CNF clause of b, do not need repetitive construct.Based on the above-mentioned set of cutting apart, if the CNF formula that obtains can not satisfy, a and b are of equal value so.Otherwise we need further determine whether erroneous judgement.At this moment continue depth-first search to cutting apart concentrated signal, repeat the process of above-mentioned structure CNF formula.Under the worst situation, may cut apart the concentrated original input signal that only comprises.For the generation of avoiding judging by accident as far as possible, concentrated in cutting apart of obtaining at every turn, if certain signal is the fan-out signal of another signal, so this signal is concentrated deletion from cutting apart.That is to say that it is separate will guaranteeing to cut apart concentrated each signal.
3) equivalence of every pair of candidate signal of use increment satisfiability proof of algorithm.If a pair of candidate signal a and b are of equal value, replace a with b so.At this moment to increase the clause of corresponding expression relation of equivalence, and add permanent clause's group.At last, the CNF clause of deleted representation signal a and a b group, and other candidate signal corresponding with a is to verifying again.Verify remaining every pair of candidate's equivalent signal then.
S5: check that whether of equal value each to original output signal, if, two circuit equivalences then, otherwise non-equivalence.
Accompanying drawing 5 has provided an example, i.e. two simple circuit, and both unique differences are the type differences of original out gate.Be or door (5) to realize that in the circuit then be XOR gate (2) in the standard circuit.
Our algorithm is described with a simple example below.As shown in Figure 5, need checking standard circuit and realize the circuit equivalence, promptly output signal a1 and a2 are of equal value, and unique difference of these two circuit is type differences of two out gates, promptly in the standard circuit be one or, and realize that in the circuit be an XOR gate.At first,, use Parallel Simulation usually, compare response characteristic then, can obtain four couples of candidates' equivalent signal for pick up speed by a spot of stochastic simulation: (u1, u2), (s1, s2), (t1, t2), (a1, a2) }.In this example, there is not the candidate signal of name-matches right.Then candidate signal is screened, by static check, with candidate signal to (u1, u2) deletion.Be by the fan-in priority ranking at last, the right equivalence of each candidate signal of checking remainder successively, the CNF formula of the whole realization circuit of structure earlier.In fact, the fan-in priority ranking is exactly by signal place classification order from small to large.(s1 is s2) with (t1, equivalence t2) (process of structure CNF formula is omitted) is replaced s1 with s2 then, and replaced t1 with t2, and the CNF formula of deleted representation s1 and t1, as shown in Figure 6 to be easy to checking.We verify that the output signal candidate is to (o represents the XOR of a1 and a2 for a1, equivalence a2) here now.Earlier according to cut apart s2, t2} verify that we can obtain following CNF formula:
φ1＝(﹁s2+a1)(﹁t2+a1)(s2+t2+﹁a1)(s2+﹁t2+a2)(﹁s2+t2+a2)(s2+t2+﹁a2)(﹁s2+﹁t2+﹁a2)
(a1+﹁a2+o)(﹁a1+a2+o)(al+a2+﹁o)(﹁a1+﹁a2+﹁o)o
In above-mentioned formula, first line display CNF formula of signal a1 and a2, the CNF formula of the second line display signal o, last unitary clause represent that making the value of xor output signal o is 1.Be very easy to find, { s2=1, t2=1} make that above-mentioned formula is satiable to assignment, and promptly { s2, t2} infer that (a1 a2) is non-equivalence according to cutting apart.At this moment, we also need further judge whether to belong to erroneous judgement.According to the method described above, will cut apart that { s2, t2} continue to launch backward, are { x1, x2, x3} up to minute cut set.Therefore also to construct following CNF formula φ 2:
φ2＝(﹁s2+x1)(﹁s2+x2)(s1+﹁x2+﹁x1)(x2+u2)(﹁x2+﹁u2)
(x3+﹁t2)(u2+﹁t2)(t2+﹁x3+﹁u2)
In formula φ 2, first line display CNF formula of signal s2 and u2 correspondence, the CNF formula of the second line display signal t2, we solve CNF formula φ 1 φ 2 now, i.e. the CNF formula of being made up of jointly above-mentioned two formula.Be not difficult to find that φ 1 φ 2 is unsatisfiable.This just proves that signal a1 and a2 are of equal value, thereby has eliminated erroneous judgement.In fact, we just know that from circuit structural analysis { s2=1, t2=1} sets up assignment never.So just proved standard and realized that circuit is a function equivalence.
Concentrate choosing of signal about cutting apart, also will illustrate situation how to avoid coherent signal, because this situation often has.In the above example, suppose we do not delete candidate signal to (u1, u2), and verify its be real equivalence to after, will divide cut set { when s2, t2} launch backward, can run into branch cut set { x1, x2, x3, u2} so.Because u2 is the fan-out signal of x2, promptly the two is not independently, may cause erroneous judgement.So should erasure signal u2, be { x1, x2, x3} thereby also obtain the branch cut set.
The present invention proposes a kind of combinational circuit equivalence checking method based on satisfiability.This method avoids proof procedure frequently to call the satisfiability program by the static filtering to candidate's equivalent signal.If candidate signal is too many, will influence the performance of algorithm.In proof procedure, dynamically select to divide the equivalent signal of cut set, it is separate to guarantee to cut apart concentrated signal.In addition, this method has realized increment satisfiability algorithm by the clause is divided into groups, thereby further improves the performance of algorithm.Experimental result shows that this method is faster than most of classic method speed.Because tradition is very difficult based on the large-scale sequential circuit of method validation of finite state machine traversal, and the formal verification method of combinational circuit can directly apply in the design verification of large scale integrated circuit.Therefore, the method that the present invention proposes realizes simple, can be integrated into easily in the electronic design automation tool, has very strong practical value.
The present invention relates to VLSI (very large scale integrated circuit) designs checking, particularly the formal verification method of combinational circuit---equivalence checking method.This method is to be engine with the satisfiability algorithm, the design of increment ground checking entire circuit, its principal feature is: 1) by circuit structural analysis candidate's equivalent signal of circuit inside is screened, then dynamically select to cut apart concentrated equivalent signal in proof procedure, it is separate guaranteeing to cut apart concentrated signal.2) by the clause is divided into groups, realize the satisfiability algorithm of increment, save computational resource, improve algorithm performance and processing power.
Claims (5)
1, a kind of combinational circuit equivalence checking method based on satisfiability, it is characterized in that, described method has two stages, phase one is candidate's equivalent signal of determining two circuit inside, and pass through circuit structural analysis, candidate's equivalent signal is made static filtering, and subordinate phase is to divide into groups to realize increment satisfiability method by the clause, and verifies the equivalence of every pair of candidate signal.
2, the combinational circuit equivalence checking method based on satisfiability according to claim 1 is characterized in that, the phase one is to determine candidate's equivalent signal, and by circuit structural analysis, candidate signal is made static filtering, and its concrete steps are as follows:
The first step: the method for parallel stochastic simulation of use or name-matches is found out candidate's equivalent signal of two circuit inside, and every response characteristic two signals identical or name-matches are used as a pair of candidate's equivalent signal;
Second step: candidate's equivalent signal is carried out static filtering, if the fan-in number of certain signal is less than 2 in the standard circuit, it is right to delete these corresponding all candidate signals of signal institute so, in addition, if the original input number that certain candidate signal b of signal a relies in the standard circuit is more than a, it is right to delete this candidate signal so.
3, the combinational circuit equivalence checking method based on satisfiability according to claim 1 is characterized in that, subordinate phase is to divide into groups to realize increment satisfiability method by the clause, and the equivalence of checking candidate signal, and its concrete steps are as follows:
1) in the proof procedure phase one candidate signal is made screening after, construct the CNF formula of whole realization circuit, as permanent clause's group;
2) Dynamic Selection is divided cut set, verifies the equivalence of every pair of candidate signal, has dependence if cut apart concentrated signal, be that certain signal is the fan-out signal of other signal, concentrate this signal of deletion from cutting apart so, in addition, select the many signals of fan-in number to enter as far as possible and cut apart set;
3) divide into groups to realize increment satisfiability algorithm by clause to the CNF formula, after a pair of signal of checking is equivalence, with the equivalent signal in the Signal permuting standard circuit of realizing in the circuit, for representing known relation of equivalence, increase corresponding CNF clause to permanent clause's group, CNF formula in the standard circuit then is dynamically to construct, and can increase and decrease as required.
4, the combinational circuit equivalence checking method based on satisfiability according to claim 1 is characterized in that its concrete steps are as follows:
S1: two circuit that are verified are carried out classification handle;
S2: find out two internal candidates equivalent signal that are verified circuit;
S3: candidate's equivalent signal that previous step obtains is carried out static filtering;
S4:, call each equivalence of increment satisfiability proof of algorithm to candidate signal by the preferential order of fan-in;
S5: check that whether of equal value each to original output signal, if, two circuit equivalences then, otherwise non-equivalence.
5, according to the described combinational circuit equivalence checking method of claim 4 based on satisfiability, it is characterized in that, step S4: by the preferential order of fan-in, call each equivalence of increment satisfiability proof of algorithm to candidate signal, Dynamic Selection is cut apart set, the right equivalence of increment checking candidate signal; Divide into groups to realize the satisfiability algorithm of increment by the clause, detailed process is as follows:
1) structure is realized conjunctive normal form (CNF) formula of circuit, as permanent clause's group, avoids the CNF formula of repetitive construct same signal;
2) dynamically adjust candidate's equivalent signal of cutting apart in the set;
3) equivalence of every pair of candidate signal of use increment satisfiability proof of algorithm.
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2004
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| CN103399982A (en) * | 2013-07-04 | 2013-11-20 | 北京航空航天大学 | Digital hardware circuit logical error diagnosis mechanism |
| CN111797588A (en) * | 2020-07-03 | 2020-10-20 | 国微集团(深圳)有限公司 | Formal verification comparison point matching method, system, processor and memory |
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| CN111539182A (en) * | 2020-07-08 | 2020-08-14 | 成都奥卡思微电科技有限公司 | Grading method for equivalent verification of combinational logic circuit |
| CN111539182B (en) * | 2020-07-08 | 2020-10-09 | 成都奥卡思微电科技有限公司 | Grading method for equivalent verification of combinational logic circuit |
| CN112257366A (en) * | 2020-10-13 | 2021-01-22 | 国微集团(深圳)有限公司 | CNF generation method and system for equivalence verification |
| WO2022077645A1 (en) * | 2020-10-13 | 2022-04-21 | 国微集团(深圳)有限公司 | Cnf generation method and system for equivalence checking |
| CN112364582A (en) * | 2020-11-30 | 2021-02-12 | 国微集团(深圳)有限公司 | Improved method, system and device for verifying tri-state gate circuit |
| WO2023272424A1 (en) * | 2021-06-28 | 2023-01-05 | 华为技术有限公司 | Circuit verification method and apparatus based on automatic test pattern generation |
| CN115062570A (en) * | 2022-07-25 | 2022-09-16 | 阿里巴巴（中国）有限公司 | Formal verification method, device and equipment and computer storage medium |
| CN115062570B (en) * | 2022-07-25 | 2022-11-15 | 阿里巴巴（中国）有限公司 | Formal verification method, device and equipment and computer storage medium |
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