CN103399982A - Digital hardware circuit logical error diagnosis mechanism - Google Patents
Digital hardware circuit logical error diagnosis mechanism Download PDFInfo
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- CN103399982A CN103399982A CN2013102780272A CN201310278027A CN103399982A CN 103399982 A CN103399982 A CN 103399982A CN 2013102780272 A CN2013102780272 A CN 2013102780272A CN 201310278027 A CN201310278027 A CN 201310278027A CN 103399982 A CN103399982 A CN 103399982A
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Abstract
The invention discloses an improved digital hardware circuit diagnosis mechanism. According to the digital hardware circuit diagnosis mechanism, an equivalence checking method based on satiable increment is applied to error diagnosis, certain candidate areas are excluded by means of similarity of internal structures of candidate areas, and then processing speed of error checking is improved. According to the digital hardware circuit diagnosis mechanism, the stability and reliability of design are systematically improved by means of the combination of various formalized methods such as the increment equivalence checking method, a logic simulation method and a Boolean satisfiability method.
Description
Technical field
The present invention relates to a kind of formalization verification method that belongs to the digital hardware circuit, particularly a kind of digital hardware circuit logic error diagnosis mechanism.
Background technology
The digital hardware circuit needs constantly test and test in design process.Whether the checkout procedure design meets given standard, in case the instruments of inspection is found design mistake, just need to carry out design error diagnosis and debugging, in order to obtain a right version that meets design specifications.When the instruments of inspection finds that design specifications and practical function are when inconsistent, need to carry out error diagnosis, namely identify or dwindle as much as possible suspicious zone errors in the design realization, then by specific algorithm, reducing as much as possible potential zone errors, namely candidate region.
Existing error diagnosis method can be divided into two large classes: based on the diagnostic method of error model and the diagnostic method of inerrancy model.If by the diagnosis inference method, divide, can be divided into diagnostic method and formalization diagnostic method based on simulation.Error diagnosis method based on simulation depends on the many test vectors that can distinguish standard and realization, and these vectors can be random vector, the gate leve fault testing vectors that produces, and can be also the differentiation vector that the equivalence checking instrument produces.According to these vectorial analog results, potential zone errors are dwindled step by step or are compressed.Although the method based on simulation is not accurate enough, its processing power is very strong, is very suitable for the diagnosis of large-scale design.Most of formalization methods are based on the BDD(binary decision diagram, Binary Decision Diagram) algorithm, these class methods try to find out, and those most possibly cause the circuit signal of output error, by the mistake in comprehensive (re-synthesize) can correct whole realization to these signals.Yet, based on the algorithm of BDD, may cause the internal memory blast, thereby processing power is limited.Also someone has proposed the error diagnosis method based on fault simulation, and this method is more accurate than the method based on simulation, and its computational complexity is again far below the formalization method based on BDD, and can be generalized in the sequential circuit error diagnosis that contains a plurality of mistakes.In recent years, due to the maturation gradually of satisfiability algorithm, someone has proposed the error diagnosis algorithm based on SAT.People have more research to the error diagnosis method based on simulation, and these class methods have extensibility preferably, can process large circuit, but not accurate enough.Great majority, based on the formalization diagnostic methods of BDD, are subject to the shortcoming of BDD, although identification error zone more exactly, its processing power is very limited,, need to compromise at aspects such as accuracy and processing poweies for this reason.Correlative study in recent years mainly contains: based on the diagnostic method of fault simulation, based on the diagnostic method of SAT (Boolean satisfiability, Boolean satisfiability) with based on the error diagnosis method of regional model.
Summary of the invention
The purpose of this invention is to provide a kind of better digital hardware circuit diagnostics mechanism, by being applied in the error diagnosis process based on satiable increment equivalence checking method, utilize the similarity of candidate region inner structure, get rid of some candidate regions, improve the processing speed of bug check.By being got up, systematically improve the various ways method synthesis such as increment equivalence checking method, logic simulation and Boolean satisfiability stability and the reliability of design.
The present invention is a kind of diagnosis mechanism of digital hardware circuit logic mistake, it is characterized in that comprising following steps:
Step 1: filter candidate region
According to the internal features of candidate's zone errors, utilize structural similarity to remove selectively some candidate regions.From the candidate region of selecting, finding zone of equal value right, zone that namely may be of equal value is right, can adopt the method for topological sorting, namely by the preferential order sequence of fan-in, the inside equivalence of deriving out before can making like this can be used for the equivalence derivation of back, namely by equivalent region, replaces to simplify the miter circuit.The core procedure of the method is, utilizes the incremental satisfiability algorithm, by topological sorting, verifies successively the equivalence of all candidate regions or proves that they are non-equivalences.If a regional f is verified zone that does not comprise mistake, at sign x of this region division, this sign is output as 1, another candidate region is g, the output in g zone and x are connected to an XOR gate y above, if node y perseverance is O, illustrate that its corresponding CNF formula is unsatisfiable, f and g are of equal value so, can be the g zone from candidate list, deleting.Use the candidate region that the method can a fast filtering part.
Step 2: stochastic simulation
Use the method for stochastic simulation, simultaneously two circuit are carried out to stochastic simulation, then compare the response characteristic of each node in two circuit, have the node of same characteristic features or opposite feature as both candidate nodes, add in a candidate list.Obtain the performance that how much has a strong impact on algorithm of candidate's node, if candidate's node is too many, can cause frequently calling of SAT program, if candidate's node very little, may cause miter too large because lacking the displacement of node of equal value, the SAT program can't normally be moved.And if candidate's node very little, also may miss the zone that some may comprise mistake.
Step 3: get rid of candidate's node
Employing is got rid of candidate's node based on the method for SAT, the discovery region exterior is wrong, this zone is excluded so, algorithm finishes, if do not find that the outside of candidate region is wrong, the Boolean comparison that calls so SAT checks, at this moment candidate region can be used as to a black box, and represent with two Boolean variables the circuit signal that each is affected by black box output, then construct corresponding CNF formula.If this formula is satiable, illustrate that so there is mistake in this region exterior, can be it from the list of candidate region, deleting, otherwise it is retained in the table of candidate region.
The advantage of the diagnosis mechanism of digital hardware circuit logic mistake of the present invention is:
1. will be applied in bug check based on satiable increment equivalence checking method, utilize the similarity of candidate region inner structure, get rid of some candidate regions, improve the processing speed of bug check.
2. the various ways method synthesis such as increment equivalence checking method, logic simulation and Boolean satisfiability are got up systematically to improve stability and the reliability of design.
The accompanying drawing explanation
Fig. 1 is the selection course of candidate region of equal value, checking f(f, g) whether be a parity price node.
Fig. 2 error diagnosis flow process.
Embodiment
The present invention is a kind of diagnosis mechanism of digital hardware circuit logic mistake, comprises following treatment step:
Step 1: filter candidate region
According to the internal features of candidate's zone errors, utilize structural similarity to remove selectively some candidate regions.From the candidate region of selecting, finding zone of equal value right, zone that namely may be of equal value is right, can adopt the method for topological sorting, namely by the preferential order sequence of fan-in, the inside equivalence of deriving out before can making like this can be used for the equivalence derivation of back, namely by equivalent region, replaces to simplify the miter circuit.The core procedure of the method is, utilizes the incremental satisfiability algorithm, by topological sorting, verifies successively the equivalence of all candidate regions or proves that they are non-equivalences.If a regional f is verified zone that does not comprise mistake, at sign x of this region division, this sign is output as 1, another candidate region is g, the output in g zone and x are connected to an XOR gate y above, if node y perseverance is O, illustrate that its corresponding CNF formula is unsatisfiable, f and g are of equal value so, can be the g zone from candidate list, deleting.Use the candidate region that the method can a fast filtering part, as shown in Figure 1.
Step 2: stochastic simulation
Use the method for stochastic simulation, simultaneously two circuit are carried out to stochastic simulation, then compare the response characteristic of each node in two circuit, have the node of same characteristic features or opposite feature as both candidate nodes, add in a candidate list.Obtain the performance that how much has a strong impact on algorithm of candidate's node, if candidate's node is too many, can cause frequently calling of SAT program, if candidate's node very little, may cause miter too large because lacking the displacement of node of equal value, the SAT program can't normally be moved.And if candidate's node very little, also may miss the zone that some may comprise mistake.
Step 3: get rid of candidate's node
Employing is got rid of candidate's node based on the method for SAT, if find that region exterior is wrong, this zone is excluded so, algorithm finishes, if do not find that the outside of candidate region is wrong, the Boolean comparison that calls so SAT checks, at this moment candidate region can be used as to a black box, and represent with two Boolean variables the circuit signal that each is affected by black box output, then construct corresponding CNF formula.If this formula is satiable, illustrate that so there is mistake in this region exterior, can be it from the list of candidate region, deleting, otherwise it is retained in the table of candidate region.Concrete process flow diagram as shown in Figure 2.
Claims (2)
1. digital hardware circuit logic error diagnosis method it is characterized in that realizing like this:
Step 1: filter candidate region
According to the internal features of candidate's zone errors, utilize structural similarity to remove selectively some candidate regions.From the candidate region of selecting, finding zone of equal value right, zone that namely may be of equal value is right, can adopt the method for topological sorting, namely by the preferential order sequence of fan-in, the inside equivalence of deriving out before can making like this can be used for the equivalence derivation of back, namely by equivalent region, replaces to simplify the miter circuit.The core procedure of the method is, utilizes the incremental satisfiability algorithm, by topological sorting, verifies successively the equivalence of all candidate regions or proves that they are non-equivalences.If a regional f is verified zone that does not comprise mistake, at sign x of this region division, this sign is output as 1, another candidate region is g, the output in g zone and x are connected to an XOR gate y above, if node y perseverance is 0, illustrate that its corresponding CNF formula is unsatisfiable, f and g are of equal value so, can be the g zone from candidate list, deleting.Use the candidate region that the method can a fast filtering part.
Step 2: stochastic simulation
Use the method for stochastic simulation, simultaneously two circuit are carried out to stochastic simulation, then compare the response characteristic of each node in two circuit, have the node of same characteristic features or opposite feature as both candidate nodes, add in a candidate list.Obtain the performance that how much has a strong impact on algorithm of candidate's node, if candidate's node is too many, can cause frequently calling of SAT program, if candidate's node very little, may cause miter too large because lacking the displacement of node of equal value, the SAT program can't normally be moved.And if candidate's node very little, also may miss the zone that some may comprise mistake.
Step 3: get rid of candidate's node
Employing is got rid of candidate's node based on the method for SAT, the discovery region exterior is wrong, this zone is excluded so, algorithm finishes, if do not find that the outside of candidate region is wrong, the Boolean comparison that calls so SAT checks, at this moment candidate region can be used as to a black box, and represent with two Boolean variables the circuit signal that each is affected by black box output, then construct corresponding CNF formula.If this formula is satiable, illustrate that so there is mistake in this region exterior, can be it from the list of candidate region, deleting, otherwise it is retained in the table of candidate region.
2. digital hardware circuit logic error diagnosis method according to claim 1 is characterized in that:
By being applied in the error diagnosis process based on satiable increment equivalence checking method, utilize the similarity of candidate region inner structure, get rid of some candidate regions, improve the processing speed of bug check.By being got up, systematically improve the various ways method synthesis such as increment equivalence checking method, logic simulation and Boolean satisfiability stability and the reliability of design.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105740206A (en) * | 2014-12-10 | 2016-07-06 | 何安平 | SAT automatic integrated solver based on FPGA |
| CN112257366A (en) * | 2020-10-13 | 2021-01-22 | 国微集团(深圳)有限公司 | CNF generation method and system for equivalence verification |
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| US6651234B2 (en) * | 2001-04-06 | 2003-11-18 | Nec Corporation | Partition-based decision heuristics for SAT and image computation using SAT and BDDs |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105740206A (en) * | 2014-12-10 | 2016-07-06 | 何安平 | SAT automatic integrated solver based on FPGA |
| CN105740206B (en) * | 2014-12-10 | 2018-11-16 | 何安平 | SAT automatic integratedization solver based on FPGA |
| CN112257366A (en) * | 2020-10-13 | 2021-01-22 | 国微集团(深圳)有限公司 | CNF generation method and system for equivalence verification |
| CN112257366B (en) * | 2020-10-13 | 2024-05-07 | 深圳国微芯科技有限公司 | CNF generation method and system for equivalence verification |
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