CN207475516U - A kind of delay circuit for pulse pattern generator - Google Patents
A kind of delay circuit for pulse pattern generator Download PDFInfo
- Publication number
- CN207475516U CN207475516U CN201721709554.4U CN201721709554U CN207475516U CN 207475516 U CN207475516 U CN 207475516U CN 201721709554 U CN201721709554 U CN 201721709554U CN 207475516 U CN207475516 U CN 207475516U
- Authority
- CN
- China
- Prior art keywords
- trigger
- delay
- differential signal
- delay chip
- pattern generator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Pulse Circuits (AREA)
Abstract
The utility model discloses a kind of delay circuit for pulse pattern generator, including the first delay chip, the second delay chip, third delay chip, the first trigger, the second trigger and third trigger；Wherein, the first delay chip carries out externally input first differential signal delay process, and the first differential signal the first trigger of feeding carries out the processing that narrows by treated；Second delay chip and third delay chip successively carry out externally input second differential signal delay process, and second signal the second trigger of feeding carries out the processing that narrows by treated；The first differential signal and the second differential signal that first trigger and the second trigger handle it respectively are sent into third trigger and carry out set or reset processing, and export pulse or dipulse.Therefore, when the delay circuit of the utility model is applied to pulse pattern generator, the performance of pulse pattern generator can be improved.
Description
Technical field
The utility model is related to electronic circuit technology fields, more particularly to a kind of deferred telegram for pulse pattern generator
Road.
Background technology
In the prior art, pulse pattern generator can not only generate simple pulse, burst and continuous impulse stream, pattern energy
Power can also generate data-signal, and this multifunctionality is the key that digital device test application, therefore, pulse pattern generator
It is widely used in the testing fields such as radar, satellite navigation, electronic countermeasure, electronic communication and aerospace.And pulse pattern is sent out
The structure of raw device generally includes clock and generates part, memory and logical gate, signal shape control section.And in order to adapt to higher
Test request it is necessary to improve the performance of pulse pattern generator, then must be to each structure division in pulse pattern generator
It optimizes.
Utility model content
The purpose of this utility model is that：A kind of delay circuit for pulse pattern generator is provided, arteries and veins can be improved
Rush the performance of pattern generator.
In order to realize above-mentioned purpose of utility model, the utility model provides following technical scheme：
A kind of delay circuit for pulse pattern generator, including the first delay chip, the second delay chip, third
Delay chip, the first trigger, the second trigger and third trigger；Wherein,
First delay chip carries out externally input first differential signal delay process, and will treated first
Differential signal is sent into first trigger and carries out the processing that narrows；Second delay chip and the third delay chip are successively
Carry out delay process to externally input second differential signal, and will treated second signal be sent into second trigger into
The capable processing that narrows；The first differential signal and the second difference that first trigger and second trigger handle it respectively
Signal is sent into the third trigger and carries out set or reset processing, and exports pulse or dipulse.
Compared with prior art, the beneficial effects of the utility model：
The utility model for pulse pattern generator delay circuit include the first delay chip, the second delay chip,
Third delay chip, the first trigger, the second trigger and third trigger；Wherein, the first delay chip is to externally input
First differential signal carries out delay process, and the first differential signal the first trigger of feeding carries out the processing that narrows by treated；
Second delay chip and third delay chip successively carry out externally input second differential signal delay process, and will be after processing
Second signal be sent into the second trigger carry out the processing that narrows；First trigger and the second trigger it is handled respectively first
Differential signal and the second differential signal are sent into third trigger and carry out set or reset processing, and export pulse or dipulse.
Therefore, when the delay circuit of the utility model is applied to pulse pattern generator, the performance of pulse pattern generator can be improved.
Description of the drawings：
Fig. 1 is the structure diagram of the utility model；
Fig. 2 is first delay chip of the utility model and the circuit diagram of the first trigger；
Fig. 3 is second delay chip of the utility model and the circuit diagram of third delay chip；
Fig. 4 is the third delay chip of the utility model and the circuit diagram of the second trigger；
Fig. 5 is the circuit diagram of first trigger of the utility model, the second trigger and third trigger.
Specific embodiment
The utility model is described in further detail with reference to test example and specific embodiment.It but should not be by this
The range for being interpreted as the above-mentioned theme of the utility model is only limitted to following embodiment, all to be realized based on the utility model content
Technology belongs to the scope of the utility model.
The structure diagram of the utility model as shown in Figure 1；Wherein, the utility model be used for pulse pattern generator
Delay circuit include the first delay chip, the second delay chip, third delay chip, the first trigger, the second trigger and
Third trigger；Wherein, the first delay chip carries out externally input first differential signal delay process, and by treated
First differential signal is sent into the first trigger and carries out the processing that narrows；Second delay chip and third delay chip are successively to external defeated
The second differential signal entered carries out delay process, and second signal the second trigger of feeding carries out the processing that narrows by treated；
The first differential signal and the second differential signal that first trigger and the second trigger handle it respectively are sent into third trigger
Set or reset processing are carried out, and exports pulse or dipulse.Therefore, the delay circuit of the utility model is applied to pulse code
During type generator, the performance of pulse pattern generator can be improved.
First delay chip of the utility model with reference to shown in Fig. 2~5 and the circuit diagram of the first trigger, the second delay
Chip is touched with the circuit diagram of third delay chip, the circuit diagram of third delay chip and the second trigger, the first trigger, second
Send out the circuit diagram of device and third trigger.
Claims (1)
1. a kind of delay circuit for pulse pattern generator, which is characterized in that including the first delay chip, the second delay core
Piece, third delay chip, the first trigger, the second trigger and third trigger；Wherein,
First delay chip carries out externally input first differential signal delay process, and will treated the first difference
Signal is sent into first trigger and carries out the processing that narrows；Second delay chip and the third delay chip are external successively
Second differential signal of portion's input carries out delay process, and the second trigger progress of second signal feeding is narrow by treated
Change is handled；The first differential signal and the second differential signal that first trigger and second trigger handle it respectively
It is sent into the third trigger and carries out set or reset processing, and export pulse or dipulse.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721709554.4U CN207475516U (en) | 2017-12-08 | 2017-12-08 | A kind of delay circuit for pulse pattern generator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721709554.4U CN207475516U (en) | 2017-12-08 | 2017-12-08 | A kind of delay circuit for pulse pattern generator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN207475516U true CN207475516U (en) | 2018-06-08 |
Family
ID=62257900
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201721709554.4U Active CN207475516U (en) | 2017-12-08 | 2017-12-08 | A kind of delay circuit for pulse pattern generator |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN207475516U (en) |
-
2017
- 2017-12-08 CN CN201721709554.4U patent/CN207475516U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100508391C (en) | A device and method to eliminate signal burr | |
| Patel et al. | VHDL implementation of UART with status register | |
| CN104935311B (en) | A kind of data signal isolator and corresponding pulsewidth decoding method | |
| CN104242934B (en) | The disparate step SAR ADC metastable state and eliminate circuits of band redundant digit and method | |
| CN103490749B (en) | A kind of high speed ultra-narrow pulse digital synthesis device | |
| CN103870421A (en) | FPGA (Field Programmable Gate Array) based serial interface and PWM (Pulse Width Modulation) combined application IP (Intellectual Property) core | |
| CN207475516U (en) | A kind of delay circuit for pulse pattern generator | |
| ATE523010T1 (en) | BIDIRECTIONAL WIRELESS SIGNAL TRANSMISSION OF SERIAL DATA BETWEEN AN ELECTRONIC DEVICE AND AN ELECTRICITY METER | |
| CN108540128B (en) | Clock frequency dividing circuit and frequency dividing method thereof | |
| CN103605626B (en) | A kind of Single wire Serial Bus agreement and change-over circuit | |
| CN105406839B (en) | A kind of circuit and electronic device | |
| CN102467674B (en) | Ultrahigh-frequency label FMO (Fast Moving Object) encoding digital signal circuit and implementation method thereof | |
| CN104980130A (en) | FPGA-based OSERDES2 square wave rise time changing method | |
| CN102854916A (en) | Method for achieving accurate clock synchronization of USB (universal serial bus) device | |
| CN201654763U (en) | Bit stream generator of true random | |
| CN206077357U (en) | A kind of encoder scaling down processing circuit based on CPLD | |
| CN103618549A (en) | Circuit structure capable of restraining sparkle and metastability of high-speed comparator | |
| CN203276255U (en) | Competition risky generator and system | |
| CN203119852U (en) | Pulse-generating circuit | |
| CN109660231A (en) | A kind of high-precision low-power consumption clock generation method | |
| CN101795137A (en) | Method for adjusting wave form of Manchester code | |
| WO2009128921A3 (en) | Method and apparatus for producing a metastable flip flop | |
| CN207475513U (en) | A kind of impulse amplitude control circuit | |
| CN110224715A (en) | Digital isolator based on miniature transformer | |
| CN106201950B (en) | Method for SOC asynchronous clock domain signal interface |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |