CN203217573U - Circuit structure for repairing violation retention time - Google Patents
Circuit structure for repairing violation retention time Download PDFInfo
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- CN203217573U CN203217573U CN 201320203028 CN201320203028U CN203217573U CN 203217573 U CN203217573 U CN 203217573U CN 201320203028 CN201320203028 CN 201320203028 CN 201320203028 U CN201320203028 U CN 201320203028U CN 203217573 U CN203217573 U CN 203217573U
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- circuit
- violation
- retention time
- timing path
- repairing
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Abstract
The utility model discloses a circuit structure for repairing violation retention time. The circuit structure comprises at least one timing path circuit which starts from a first register and ends up with a second register, wherein a high standard unit utilization ratio area is formed in a rectangular area between the two registers. The timing path circuit is routed by bypassing the high standard unit utilization ratio area, so that delay is increased through a used lengthened wire, the violation retention time is repaired, the high standard unit utilization ratio can be prevented from being increased under the condition of the high standard unit utilization ratio, the chip area is saved, the power consumption is reduced, and timing closure is facilitated.
Description
[technical field]
The utility model relates to electronic applications, particularly for repairing the circuit structure of retention time in violation of rules and regulations.
[background technology]
For repairing timing path through the standard block high usage mode of violation retention time, traditional solution is: the timing path that can not satisfy the time limit requirement to the retention time, terminal point register circuit on this timing path is inserted delay circuit, to reach the requirement of thresholding retention time, this kind mode is placed on the delay logic physical location in the standard block high usage zone, though improved utilization factor, increased near the difficulty of circuit trace.
Specifically can join shown in Figure 1A, be the structural representation of ifq circuit, this ifq circuit comprises 1 timing path, be register 1 to the path (abbreviating path 1 as) of register 2, comprise combinational circuit 1 in the path 1, under temporal constraint, as find that path 1 has in violation of rules and regulations, needs to increase by 4 nanoseconds.When therefore repair in path 1 in violation of rules and regulations to the ifq circuit retention time shown in Fig. 2 A, existing scheme is the terminal point register 2 to this paths, in path 1, increase delay circuit 1, delay circuit 2, delay circuit 3 and delay circuit 4, specifically as shown in Figure 1B.Above-mentioned each 1 nanosecond of delay circuit delays wherein, because cabling is short, calculations of can ignoring of the delay on the line length increased the delay of 4 nanoseconds in the circuit after then repairing, thereby made path 1 satisfy the retention time requirement of timing path.
Yet, such scheme is owing to be the delay of considering independently on the path 1, and consider to add the standard block physical location utilization factor situation of delay circuit 1 to the delay circuit 4, therefore cabling through regional standard unit by using rate than higher situation under, can cause cabling resource anxiety, can't normally wind the line, the subsequent authentication flow process is long, the time that iterates is also long and influence production time of chip.
[utility model content]
The purpose of this utility model is to provide a kind of circuit structure of retention time in violation of rules and regulations of repairing, and causes cabling resource anxiety in order to solve prior art, can't normally wind the line, the subsequent authentication flow process is long, iterate also long technical matters of time.
For solving the problems of the technologies described above, the utility model provides the circuit structure of a kind of repairing standard unit high usage violation retention time, this circuit comprises at least one timing path circuit, this timing path circuit is from register, end at register, be provided with standard block high usage zone in the rectangular area between two registers, this timing path circuit trace is through getting around this standard block high usage zone.
According to above-mentioned principal character, this timing path circuit also is provided with a combinational circuit between two registers.
According to above-mentioned principal character, this timing path circuit also is provided with delay circuit behind combinational circuit.
According to above-mentioned principal character, this delay circuit is provided with two.
According to above-mentioned principal character, the delay duration of the circuit devcie on the timing path circuit is greater than default thresholding.
Compared with prior art, the utility model is by getting around the timing path circuit in standard block high usage zone, do not change the circuit devcie in this zone, owing to reduced the change to standard block high usage zone, utilize the delay of line length also to reduce the delay circuit that increases simultaneously, reach and keep the cabling resource simultaneously and repair retention time violation effect, thereby the effect that realizes saving the cabling resource, saves the standard block high usage, saves power consumption and saving cost, also little to the traditional process change simultaneously, be conducive to placement-and-routing more.
[description of drawings]
Figure 1A is the structural representation of ifq circuit;
Figure 1B repairs timing path through the standard block high usage electrical block diagram of violation retention time;
Fig. 2 is the structural representation of the retention time of enforcement the utility model technology repairing circuit in violation of rules and regulations;
[embodiment]
For making the purpose of this utility model, technical scheme and advantage clearer, below in conjunction with accompanying drawing each embodiment of the present utility model is explained in detail.Yet, persons of ordinary skill in the art may appreciate that in various embodiments of the present utility model, in order to make the reader understand the application better many ins and outs have been proposed.But, even without these ins and outs with based on many variations and the modification of following each embodiment, also can realize the every claim of the utility model technical scheme required for protection.
Implement the circuit structure of reparation violation retention time of the present utility model as shown in Figure 2, this circuit structure comprises at least one timing path circuit of being made up of register and logical circuit, and starting point and the terminal point of timing path circuit are register.During concrete enforcement, wherein the timing path circuit is: register 1-combinational circuit 1-delay circuit 1-delay circuit 2-register 2.Wherein, be provided with standard block high usage zone in the rectangular area between two registers.In the present embodiment, the delay duration of the circuit devcie on the timing path circuit is greater than default thresholding, and this default thresholding can arrange according to the maintenance duration of each timing path, meets the demands as long as can guarantee the retention time of each timing path circuit.
That is to say, be by increasing the delay circuit logic in the present embodiment, make that the delay of circuit increases on the timing path circuit, to satisfy the retention time demand of timing path circuit, if reduce circuit delay on the path, holding time problem in violation of rules and regulations then may appear.Standard block high usage zone in the rectangular area between two registers then will get around this zone, does not increase this regional standard block utilization factor.Therefore, the implement repairing standard of the present utility model unit high usage circuit structure of retention time in violation of rules and regulations, standard block high usage zone does not increase utilization factor, saved should the zone standard block utilize resource.Can reach the change that has reduced standard block high usage zone thus, utilize the delay of line length also to reduce the delay circuit that increases simultaneously, reach and keep the cabling resource simultaneously and repair retention time effect in violation of rules and regulations.Thereby the cabling resource is saved in realization, saves the standard block high usage, saves power consumption, saves the effect of cost, and is also little to the traditional process change simultaneously, is conducive to placement-and-routing more.
Contrast Figure 1A and Fig. 2 are as can be known, the delay of 4 nanoseconds is arranged as need, then in circuit shown in Figure 2, add 1 nanosecond delay circuit 1,1 nanosecond delay circuit 2, walk around two standard block high usage zones in the rectangular area between the register again, cabling has increased by 2 nanoseconds owing to elongated, so delay circuit 1+ delay circuit 2+ walks wire delay=4 nanoseconds, thereby satisfies the requirement of retention time in violation of rules and regulations.
This shows, in the present embodiment, owing to need not the standard block high usage zone in the rectangular area between two registers is changed, therefore reduced the cabling resource that needs optimization, by to increasing delay circuit 1 and delay circuit 2, and utilize delay on the line length, reached the effect of improving the retention time path simultaneously.Thereby the effect that realization is saved the cabling resource, saved the standard block high usage, saves power consumption and save cost is also little to the traditional process change simultaneously, is conducive to placement-and-routing more.
What deserves to be mentioned is that in actual applications, after circuit optimization is finished, can further analyze according to the static timing report of the logical circuit after optimizing, the retention time of ifs circuit does not have in violation of rules and regulations, then need not to optimize again; If this retention time in violation of rules and regulations circuit still have in violation of rules and regulations, continue by increasing delay circuit or increasing combinational circuit or changing the relative position of combinational circuit, up to there not being holding time situation in violation of rules and regulations.
Persons of ordinary skill in the art may appreciate that the respective embodiments described above are to realize specific embodiment of the utility model, and in actual applications, can do various changes to it in the form and details, and do not depart from spirit and scope of the present utility model.
Claims (5)
1. repair the circuit structure of retention time in violation of rules and regulations for one kind, this circuit comprises at least one timing path circuit, this timing path circuit is from register, end at register, be provided with standard block high usage zone in the rectangular area between two registers, this timing path circuit trace is through getting around this standard block high usage zone.
2. the circuit structure of retention time in violation of rules and regulations of repairing as claimed in claim 1, it is characterized in that: this timing path circuit also is provided with a combinational circuit between two registers.
3. the circuit structure of retention time in violation of rules and regulations of repairing as claimed in claim 2, it is characterized in that: this timing path circuit also is provided with delay circuit behind combinational circuit.
4. the circuit structure of retention time in violation of rules and regulations of repairing as claimed in claim 3, it is characterized in that: this delay circuit is provided with two.
5. the circuit structure of retention time in violation of rules and regulations of repairing as claimed in claim 4, it is characterized in that: the delay duration of the circuit devcie on the timing path circuit is greater than default thresholding.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320203028 CN203217573U (en) | 2013-04-18 | 2013-04-18 | Circuit structure for repairing violation retention time |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320203028 CN203217573U (en) | 2013-04-18 | 2013-04-18 | Circuit structure for repairing violation retention time |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203217573U true CN203217573U (en) | 2013-09-25 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201320203028 Expired - Lifetime CN203217573U (en) | 2013-04-18 | 2013-04-18 | Circuit structure for repairing violation retention time |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203217573U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111931453A (en) * | 2020-07-15 | 2020-11-13 | 深圳市紫光同创电子有限公司 | Data path repairing method, FPGA circuit and FPGA circuit design device |
| CN111931452A (en) * | 2020-07-15 | 2020-11-13 | 深圳市紫光同创电子有限公司 | Data path repairing method, FPGA circuit and FPGA circuit design device |
-
2013
- 2013-04-18 CN CN 201320203028 patent/CN203217573U/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111931453A (en) * | 2020-07-15 | 2020-11-13 | 深圳市紫光同创电子有限公司 | Data path repairing method, FPGA circuit and FPGA circuit design device |
| CN111931452A (en) * | 2020-07-15 | 2020-11-13 | 深圳市紫光同创电子有限公司 | Data path repairing method, FPGA circuit and FPGA circuit design device |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C56 | Change in the name or address of the patentee | ||
| CP02 | Change in the address of a patent holder |
Address after: 201702, Qingpu District, Shanghai, Shanghai Qing Ping highway 1362, 1, 1, C District, room 133 Patentee after: SHANGHAI HWACHIP SEMICONDUCTOR CO.,LTD. Address before: 4, building 3, building 88, 201203 Darwin Road, Shanghai, Pudong New Area Patentee before: SHANGHAI HWACHIP SEMICONDUCTOR CO.,LTD. |
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| TR01 | Transfer of patent right |
Effective date of registration: 20211119 Address after: 100193 room 118, 1f, building B 18, yard 8, Dongbeiwang West Road, Haidian District, Beijing Patentee after: Beijing Huali Zhifei Technology Co.,Ltd. Address before: 201702 room 133, Zone C, floor 1, building 1, No. 1362, Huqingping highway, Qingpu District, Shanghai Patentee before: SHANGHAI HWACHIP SEMICONDUCTOR CO.,LTD. |
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| TR01 | Transfer of patent right | ||
| CX01 | Expiry of patent term |
Granted publication date: 20130925 |
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| CX01 | Expiry of patent term |