CN101303711A - Gating clock for on-site programmable gate array and implementing method thereof - Google Patents
Gating clock for on-site programmable gate array and implementing method thereof Download PDFInfo
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- CN101303711A CN101303711A CNA2008101164696A CN200810116469A CN101303711A CN 101303711 A CN101303711 A CN 101303711A CN A2008101164696 A CNA2008101164696 A CN A2008101164696A CN 200810116469 A CN200810116469 A CN 200810116469A CN 101303711 A CN101303711 A CN 101303711A
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Abstract
The invention provides a gated clock in a field programmable gate array and a realizing method thereof; the gated clock includes a plurality of triggers, and a global clock cache multi-route selector the output end of which is connected with the clock input ends of the triggers; the global clock cache multi-route selector is used for leading the input of the clock input ends of the triggers to be a clock signal when a clock enabling signal is effective and leading the input of the clock input ends of the triggers to be zero when the clock enabling signal is ineffective. In the invention, a plurality of triggers are connected with the same BUFGMUX, thereby reducing the consumption of a plurality of areas. The gating mode is consistent with a real ASIC; the clock enabling signal is synchronous with the phase relation of the clock; when the enabling signal is ineffective, the actual clock inputted into the trigger is zero; therefore, more accurate evolution can be carried out on the power consumption; the demands of a clock tree in FPGA can be met; the invention is simple and practical.
Description
Technical field
The present invention relates to integrated circuit technique, particularly relate to gated clock and its implementation in a kind of field programmable gate array.
Background technology
In the modern integrated circuits design, the scale of chip and complexity all are being the increase of index.Especially in the design cycle of ASIC (Application Specific Intergrated Circuits, special IC), the time that checking and debugging are spent accounts for 70% of the overall design duration.In order to shorten the time cycle that checking spends, on the basis of traditional simulating, verifying, many new checking means have been emerged in large numbers, as assert the checking that checking, coverage rate drive, and the prototype verification technology based on FPGA (Field Programmable GateArray, field programmable gate array) of widespread use.The FPGA prototype verification is that chip is at the preceding most important proof procedure of flow (tape-out).Compare with simulation software, the ardware feature of FPGA can allow design and operation on higher frequency, can quicken emulation.On the other hand, can shorten the chip checking cycle in asic chip design concurrent designing peripheral circuit in early stage and application software.
But FPGA itself and ASIC have a lot of differences.Topmost difference is exactly the difference about clock.In the circuit design of ASIC, automatic placement and routing's instrument uses the method for dynamically building the clock buffer tree to solve the clock jitter problem, and its basic thought is exactly gate delay and the circuit delay between control clock source and the register.If with the clock end of all registers in the clock zone and the path between the clock source, comprise identical substantially clock buffer number and wire length, just can think approx that the time-delay of clock signal from the clock source to each register clock end equates, so the clock jitter between register can be ignored.
And because the production technology of FPGA, before dispatching from the factory, the line between the FPGA inner member is completely fixed.Simultaneously, FPGA has the line bigger characteristics of relative gate delay of delaying time, and causes FPGA not solve the clock jitter problem by the method for dynamically building the clock buffer tree.In fact, the clock trees structure of FPGA is solidificated in the middle of the chip in advance.
Just because of above difference, gated clock that can simple realization in ASIC needs individual processing in FPGA.Gated clock is one of main method that reduces power consumption.Gated clock adopts circuit as shown in Figure 1 to realize usually in ASIC.Clock and clock Enable Pin do " with " computing, the signal of generation is as the actual clock of trigger 101.Its principle of work is, when clock enables invalidly, then the clock signal of input trigger 101 is a low level, this moment trigger 101 no dynamic power consumptions, power consumption is fixed, and input signal equals output signal.
Existing systems majority when carrying out the FPGA prototype verification takes the following MUX that gate-control signal is changed to data terminal by clock end to realize.
Prior art with ASIC recently like FPGA gated clock solution as follows:
As shown in Figure 2, the circuit structure diagram of the gated clock of realizing for FPGA, when clock enables when effective, the input end of trigger 201 is normal clock input, when clock enables when invalid, data input pin be that the data of the trigger 201 of this moment are exported.
The gated clock that this MUX 202 realizes can satisfy the demand that clock trees makes up among the FPGA.But, in the process that realizes technical solution of the present invention, find that there is following defective at least in this structure:
At first, for the system that full chip all carries out gated clock, each trigger all needs to increase a MUX, has therefore increased the consumption of a lot of areas.
The second, this gate mode also has certain difference with real ASIC, and the phase relation of clock enable signal and clock itself can't be verified.This be because, in first moment that the clock enable signal changes, its real generation effect is in second moment after MUX 202 and trigger 201 delays, what just it really latched is not the input signal in first moment, but the output signal in second moment that the input signal in first moment obtains behind MUX 202 and trigger 201.
The 3rd, because this structure only is the gate scheme that has been similar to ASIC on the function, and therefore the actual clock of input trigger 201 can't be estimated on power consumption more accurately still in continuous upset.
Summary of the invention
The purpose of this invention is to provide the door control clock circuit in a kind of field programmable gate array, make the FPGA door control clock circuit of real simulated ASIC more, solve big, the accurate technical matters of estimating power consumption of the area occupied that the door control clock circuit of the ASIC of prior art simulation exists.
To achieve these goals, on the one hand, provide the gated clock in a kind of field programmable gate array, having comprised:
Trigger;
Global clock buffer memory MUX, output terminal connects the input end of clock of described trigger, be used for: at the clock enable signal when being effective, make described trigger input end of clock be input as clock signal, at described clock enable signal when being invalid, make described trigger input end of clock be input as zero.
Preferably, described gated clock, wherein, one road input signal of described MUX is described clock signal, the control signal of described MUX is described clock enable signal.
Preferably, described gated clock, wherein, described MUX is the two-way selector switch, and one road input grounding wherein.
Preferably, described gated clock, wherein, described trigger is at least two, and the input end of clock of each described trigger all connects the output terminal of described MUX.
Another aspect of the present invention provides a kind of field programmable gate array, comprises gated clock, and described gated clock comprises:
At least one trigger;
Global clock buffer memory MUX, output terminal connects the input end of clock of described trigger, be used for: at the clock enable signal when being effective, make described trigger input end of clock be input as clock signal, at described clock enable signal when being invalid, make described trigger input end of clock be input as zero.
Preferably, described field programmable gate array, wherein, one road input signal of described MUX is described clock signal, the control signal of described MUX is described clock enable signal.
Preferably, described field programmable gate array, wherein, described MUX is the two-way selector switch, and one tunnel input grounding wherein.
Another aspect of the present invention provides the method that realizes gated clock in a kind of programmable gate array at the scene, comprising:
Make clock signal and ground signalling be input to the input end of global clock buffer memory MUX;
Make the clock enable signal be input to the selecting side of described global clock buffer memory MUX;
When being effective, make described global clock buffer memory MUX export described clock signal at described clock enable signal to the input end of clock of trigger; At described clock enable signal when being invalid, make described trigger input end of clock be input as zero.
Another aspect of the present invention provides a kind of implementation method of field programmable gate array, it is characterized in that, comprising: make clock signal and ground signalling be input to the input end of global clock buffer memory MUX;
Make the clock enable signal be input to the selecting side of described global clock buffer memory MUX;
When being effective, make described global clock buffer memory MUX export described clock signal at described clock enable signal to the input end of clock of at least one trigger; At described clock enable signal when being invalid, make described at least one trigger input end of clock be input as zero.
There is following technique effect at least in the embodiment of the invention:
1) embodiment of the invention uses BUFGMUX to make up gated clock, finishes the control to clock, flexible utilization the resource among the FPGA, both satisfied FPGA clock internal tree demand, farthest satisfy the demand of design verification again.
2) for the system that full chip all carries out gated clock, a plurality of triggers all connect same BUFGMUX, have therefore reduced the consumption of a lot of areas.
3) the gate mode is consistent with real ASIC effect, the phase relation synchronised of clock enable signal and clock itself, and in first moment that the clock enable signal changes, what latch is the input signal in this first moment.
When 4) enable signal was invalid, the actual clock of input trigger was zero, therefore can estimate more accurately on power consumption.
5) all similar on effect and function with the ASIC of reality, can satisfy the demand of clock trees among the FPGA, simple and practical.
Description of drawings
Fig. 1 is for having the circuit structure diagram of the gated clock of realizing among the ASIC now;
Fig. 2 is the circuit structure diagram of the gated clock of existing FPGA realization;
The use BUFGMUX that Fig. 3 provides for the embodiment of the invention realizes the circuit structure diagram of the gated clock of FPGA;
The structural drawing of the gated clock network that constitutes with BUFGMUX that Fig. 4 provides for the embodiment of the invention.
Embodiment
For the purpose, technical scheme and the advantage that make the embodiment of the invention is clearer, specific embodiment is described in detail below in conjunction with accompanying drawing.
A kind of resource is arranged BUFGMUX (global clock buffer memory MUX) in FPGA, BUFGMUX is not simple clock buffer, and it is a MUX that has low clock jitter, high driving ability and have the selecting side.Use different primitive that BUFGMUX is carried out instantiation, BUFGMUX can constitute clock selector, Clock gating device or simple clock buffer.
Consider that FPGA has own unique clock resource, so the embodiment of the invention so that both satisfied FPGA clock internal tree demand, farthest satisfies the demand of design verification with flexible correct these resources of use again.
The use BUFGMUX that Fig. 3 provides for the embodiment of the invention realizes the circuit structure diagram of the gated clock of FPGA, and as shown in the figure, gated clock comprises: trigger 301; Selector switch 302 by the BUFGMUX realization, output terminal connects the input end of clock of described trigger, be used for: at the clock enable signal when being effective, make described trigger input end of clock be input as clock signal, at described clock enable signal when being invalid, make described trigger input end of clock be input as zero.
Wherein, one road input signal of selector switch 302 is described clock signal, and the control signal of selector switch 302 is described clock enable signal, and described selector switch is the two-way selector switch, and one road input grounding wherein.
The structural drawing of the gated clock network that constitutes with BUFGMUX that Fig. 4 provides for the embodiment of the invention.The clock end of the trigger 401 in FPGA increases the gated devices of BUFGMUX 402 as clock.When clock enables when effective, clock can enter the clock end of a plurality of triggers by BUFGMUX, and when clock enables when invalid, the clock end of described a plurality of triggers is input as 0, thereby has realized gated clock.Because the characteristic of BUFGMUX does not have short-time pulse waveform and disturbs appearance in the process of opening and turn-offing.
The corresponding above gated clock that constitutes by hardware unit, the embodiment of the invention also provides the method that realizes gated clock in a kind of programmable gate array at the scene, comprising:
Make clock signal and ground signalling be input to the input end of global clock buffer memory MUX;
Make the clock enable signal be input to the selecting side of described global clock buffer memory MUX;
When being effective, make described global clock buffer memory MUX export described clock signal at described clock enable signal to the input end of clock of trigger; At described clock enable signal when being invalid, make described trigger input end of clock be input as zero.
As from the foregoing, the embodiment of the invention has following advantage:
1) embodiment of the invention uses BUFGMUX to make up gated clock, finishes the control to clock, flexible utilization the resource among the FPGA, both satisfied FPGA clock internal tree demand, farthest satisfy the demand of design verification again.
2) for the system that full chip all carries out gated clock, a plurality of triggers all connect same BUFGMUX, have therefore reduced the consumption of a lot of areas.
3) the gate mode is consistent with real ASIC effect, the phase relation synchronised of clock enable signal and clock itself, and in first moment that the clock enable signal changes, what latch is the input signal in this first moment.
When 4) enable signal was invalid, the actual clock of input trigger was zero, therefore can estimate more accurately on power consumption.
5) all similar on effect and function with the ASIC of reality, can satisfy the demand of clock trees among the FPGA, simple and practical.
The above only is a preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (9)
1. the gated clock in the field programmable gate array is characterized in that, comprising:
Trigger;
Global clock buffer memory MUX, output terminal connects the input end of clock of described trigger, be used for: at the clock enable signal when being effective, make described trigger input end of clock be input as clock signal, at described clock enable signal when being invalid, make described trigger input end of clock be input as zero.
2. gated clock according to claim 1 is characterized in that, one road input signal of described MUX is described clock signal, and the control signal of described MUX is described clock enable signal.
3. gated clock according to claim 1 is characterized in that, described MUX is the two-way selector switch, and one road input grounding wherein.
4. according to claim 1,2 or 3 described gated clocks, it is characterized in that described trigger is at least two, and the input end of clock of each described trigger all connects the output terminal of described MUX.
5. a field programmable gate array is characterized in that, comprises gated clock, and described gated clock comprises:
At least one trigger;
Global clock buffer memory MUX, output terminal connects the input end of clock of described trigger, be used for: at the clock enable signal when being effective, make described trigger input end of clock be input as clock signal, at described clock enable signal when being invalid, make described trigger input end of clock be input as zero.
6. field programmable gate array according to claim 5 is characterized in that, one road input signal of described MUX is described clock signal, and the control signal of described MUX is described clock enable signal.
7. field programmable gate array according to claim 5 is characterized in that, described MUX is the two-way selector switch, and one tunnel input grounding wherein.
8. a method that realizes gated clock at the scene in the programmable gate array is characterized in that, comprising:
Make clock signal and ground signalling be input to the input end of global clock buffer memory MUX;
Make the clock enable signal be input to the selecting side of described global clock buffer memory MUX;
When being effective, make described global clock buffer memory MUX export described clock signal at described clock enable signal to the input end of clock of trigger; At described clock enable signal when being invalid, make described trigger input end of clock be input as zero.
9. the implementation method of a field programmable gate array is characterized in that, comprising:
Make clock signal and ground signalling be input to the input end of global clock buffer memory MUX;
Make the clock enable signal be input to the selecting side of described global clock buffer memory MUX;
When being effective, make described global clock buffer memory MUX export described clock signal at described clock enable signal to the input end of clock of at least one trigger; At described clock enable signal when being invalid, make described at least one trigger input end of clock be input as zero.
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| Application Number | Priority Date | Filing Date | Title |
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| CNA2008101164696A CN101303711A (en) | 2008-07-10 | 2008-07-10 | Gating clock for on-site programmable gate array and implementing method thereof |
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| CNA2008101164696A CN101303711A (en) | 2008-07-10 | 2008-07-10 | Gating clock for on-site programmable gate array and implementing method thereof |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102880744A (en) * | 2012-08-30 | 2013-01-16 | 西安欣创电子技术有限公司 | Logic time sequence unit and automatic design platform based on time sequence unit |
| CN103439648A (en) * | 2013-08-08 | 2013-12-11 | 北京华大信安科技有限公司 | Validation method, validation device and chip |
| CN105808824A (en) * | 2016-02-26 | 2016-07-27 | 浪潮(北京)电子信息产业有限公司 | ASIC (Application Specific Integrated Circuit) design clock network reconfiguring system and method |
| CN106484941A (en) * | 2015-08-28 | 2017-03-08 | 三星电子株式会社 | Method of designing integrated circuit and the integrated clock gating device integrated with trigger |
| CN108073253A (en) * | 2016-11-17 | 2018-05-25 | 法乐第(北京)网络科技有限公司 | The temprature control method of logical device |
| CN108763694A (en) * | 2018-05-18 | 2018-11-06 | 中国人民解放军空军装备研究院雷达与电子对抗研究所 | A kind of method and device reducing FPGA dynamic power consumptions |
| CN110412325A (en) * | 2019-08-08 | 2019-11-05 | 电子科技大学 | Wireless dummy oscillograph and its power consumption dynamic management approach |
| CN110705192A (en) * | 2019-09-20 | 2020-01-17 | 浪潮(北京)电子信息产业有限公司 | Output power consumption configuration circuit and system of FPGA and FPGA |
| CN115048887A (en) * | 2022-06-21 | 2022-09-13 | 深圳国微芯科技有限公司 | Processing method, verification method and storage medium of implementation circuit with gating clock |
-
2008
- 2008-07-10 CN CNA2008101164696A patent/CN101303711A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102880744A (en) * | 2012-08-30 | 2013-01-16 | 西安欣创电子技术有限公司 | Logic time sequence unit and automatic design platform based on time sequence unit |
| CN103439648A (en) * | 2013-08-08 | 2013-12-11 | 北京华大信安科技有限公司 | Validation method, validation device and chip |
| CN103439648B (en) * | 2013-08-08 | 2016-05-04 | 北京华大信安科技有限公司 | A kind of verification method, device and chip |
| CN106484941A (en) * | 2015-08-28 | 2017-03-08 | 三星电子株式会社 | Method of designing integrated circuit and the integrated clock gating device integrated with trigger |
| CN105808824A (en) * | 2016-02-26 | 2016-07-27 | 浪潮(北京)电子信息产业有限公司 | ASIC (Application Specific Integrated Circuit) design clock network reconfiguring system and method |
| CN108073253A (en) * | 2016-11-17 | 2018-05-25 | 法乐第(北京)网络科技有限公司 | The temprature control method of logical device |
| CN108763694A (en) * | 2018-05-18 | 2018-11-06 | 中国人民解放军空军装备研究院雷达与电子对抗研究所 | A kind of method and device reducing FPGA dynamic power consumptions |
| CN110412325A (en) * | 2019-08-08 | 2019-11-05 | 电子科技大学 | Wireless dummy oscillograph and its power consumption dynamic management approach |
| CN110705192A (en) * | 2019-09-20 | 2020-01-17 | 浪潮(北京)电子信息产业有限公司 | Output power consumption configuration circuit and system of FPGA and FPGA |
| CN110705192B (en) * | 2019-09-20 | 2022-03-22 | 浪潮(北京)电子信息产业有限公司 | Output power consumption configuration circuit and system of FPGA and FPGA |
| CN115048887A (en) * | 2022-06-21 | 2022-09-13 | 深圳国微芯科技有限公司 | Processing method, verification method and storage medium of implementation circuit with gating clock |
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