CN207720100U - A kind of CPLD dual-edge triggers circuit - Google Patents

Abstract

The utility model discloses a kind of CPLD dual-edge triggers circuits, it is mainly made of d type flip flop, data selector, NOT gate and XOR gate；D type flip flop is rising edge trigger circuit；XOR gate is two input XOR gates；The input terminal of the output end NAND gate of d type flip flop connects；The output end of NOT gate and the triggering end of d type flip flop connect；The output end of d type flip flop is also connect with the first input end of XOR gate；The output end of XOR gate is connected with the clock end of d type flip flop；Second input terminal of XOR gate is connected with the output end of data selector.The utility model can trigger overturning to two edges of clock pulses, be conducive to the utilization rate for improving clock, have the advantages that digital display circuit power consumption can be reduced.

Description

A kind of CPLD dual-edge triggers circuit

Technical field

The utility model is related to a kind of flip-flop circuit, specifically a kind of dual-edge trigger realized based on CPLD technologies Circuit belongs to hardware circuit design technical field.

Background technology

With being growing for digital circuitry scale, pursue system power dissipation low-power consumption become one it is universal Designer trends, it is well known that the main source of digital display circuit power consumption is the dynamic during each node potential saltus step in system Power consumption, it occupies the 70%~90% of entire power consumption, the reduction important in inhibiting of digital display circuit dynamic power consumption.Reduce dynamic work( Consumption again should be from the aspect of two：When reduce for realize the inoperative switch saltus step activity of logic function, block its to Circuit internal penetration achievees the purpose that low power dissipation design, here it is in low power dissipation design to inhibit its corresponding dynamic power consumption Redundancy-Restraining Technique mouth；Second is that each switch movable utilization rate of saltus step should be improved as possible, make each saltus step of clock signal, Even the front and back edge of saltus step can be to realize corresponding time sequence logic function service every time, to make needed for completion identity logic function Switch transition times reduce, with reach reduce switch activity amount, reduce the purpose of power consumption.The second way listed above is real Now reducing the basic principle of power consumption can be summarized as：In sequential logic system, the realization of logic function is to rely on clock pulses (CP) come what is realized, the clock pulses in sequential system is uniquely always in the signal of saltus step, is to be for the overturning of triggering trigger The main source of system dynamic power consumption, if the utilization rate of clock pulses can be improved, completing identical logic function can be reduced Clock pulses number also just reduces power consumption.It that is to say that we need a kind of sequential logic base unit in Design of Digital System, It can detect the rising edge and failing edge of clock signal simultaneously.

And in this typical large scale digital system circuit designs of CPLD, we realize number in the way of schematic diagram But the basic sequential logic basis for lacking the rising edge and failing edge that can detect clock signal simultaneously in this way when circuit system is single First (basic sequential logic unit generally includes trigger and latch), it is soft for example, by using common developing instrument QUARTUS Part, when designing circuit in the way of schematic diagram, as shown in Fig. 2, the trigger that can be called is single edge flip-flops, in figure Each trigger enumerated is rising edge triggering, and NOT gate can be added when failing edge triggering in clock end by needing to realize, but not It can realize rising edge and failing edge triggering.

To sum up, in CPLD schematic diagram development schemes, the saltus step of clock edge be not fully utilized clock utilization rate only Have 50%, if trigger can trigger overturning to two edges of clock pulses, so that it may which the utilization rate for greatly improving clock reaches To the purpose for reducing power consumption.

Utility model content

For deficiencies of the prior art, the purpose of this utility model is：There is provided one kind can be to clock pulses Two edges can trigger overturning, to improve the utilization rate of clock, achieve the purpose that reduce power consumption based on CPLD schematic diagrams The flip-flop circuit of design method.

To achieve the goals above, the utility model uses technical solution below.

A kind of CPLD dual-edge triggers circuit, it is characterised in that：It mainly by d type flip flop, data selector, NOT gate and XOR gate forms；The d type flip flop is rising edge trigger circuit；The XOR gate is two input XOR gates；

The output end of d type flip flop is connect with the input terminal of the NOT gate；The triggering of the output end and d type flip flop of the NOT gate End connection；

The output end of d type flip flop is also connect with the first input end of XOR gate；The output end of XOR gate and D triggers Clock end is connected；Second input terminal of XOR gate is connected with the output end of data selector；The data selector is 4 choosings 1st selected data input pin of 1 data selector, the data selector is connected with the signal output end of the 1st crystal oscillator, described 2nd selected data input pin of data selector is connected with the signal output end of the 2nd crystal oscillator, and the 3rd of the data selector the Selected data input pin is connected with the signal output end of the 3rd crystal oscillator, the 4th selected data input pin of the data selector and The signal output end of 4th crystal oscillator is connected；

The clock end of 1st, 2,3 ... N output triggers is connected with the output end of XOR gate；

The triggering ends of 1st, 2,3 ... N output triggers constitute multichannel dual-edge trigger circuit the 1st, 2,3 ... N triggerings End；

The output ends of 1st, 2,3 ... N output triggers constitute multichannel dual-edge trigger circuit the 1st, 2,3 ... N outputs End.

Further, the output trigger is rest-set flip-flop or T triggers.

Compared with prior art, the utility model has the following advantages that：The output end of d type flip flop passes through non-in the utility model Door is connect with the triggering end of d type flip flop；The output end of d type flip flop and the first input end of XOR gate connect, and the second of XOR gate Input terminal is as the port for receiving clock signal of system；When clock signal of system is sent into the second input terminal of XOR gate, XOR gate The second input terminal rising edge and failing edge correspond to the moment and rising edge can occur in the output end of XOR gate.So if by different Or the clock end of the output access output trigger of door can realize output trigger to being inputted from the second input terminal of XOR gate Two edges of clock pulses can trigger overturning, therefore the utility model circuit structure is applied in CPLD system developments just It is greatly improved the utilization rate of clock, reaches the advantageous effect for reducing power consumption.

In addition, the 4 of the utility model select 1 selector that can believe the output for 4 crystal oscillators being arranged on system circuit board It number is selected, the clock signal of different frequency is inputted for entire flip-flop circuit；The signal of XOR gate output can also be simultaneously It is sent into multiple and different output triggers, therefore the input clock signal of the utility model can flexibly select the letter of different frequency Number, the clock signal being selected can be used for different output triggers, this is provided more for the design of CPLD circuit systems Flexibility.

Description of the drawings

Fig. 1 is the utility model circuit structure diagram；

Flip-flop element common in being designed for CPLD Fig. 2；

Fig. 3 is bilateral along dock signal generation unit circuit main signal oscillogram in the utility model；

Fig. 4 is bilateral along the amplified oscillogram of dock signal generation unit circuit main signal in the utility model.

Specific implementation mode

The utility model is described in further detail with reference to the accompanying drawings and detailed description.

One, circuit composition and connection relation

CPLD (Complex Programmable Logic Devices), is the digital device come out from PAL and GAL device developments, opposite PAL and Scale is big for GAL devices, complicated, belongs to large scale integrated circuit range.Be a kind of user according to respective need and from The digital integrated electronic circuit of row constitutive logic function.Its basic design method is by Integrated Development software platform, with schematic diagram, firmly The methods of part description language generates corresponding file destination, code is transmitted in objective chip by download cable, realization is set The digital display circuit of meter.

The utility model is a kind of flip-flop circuit unit applied in CPLD exploitations.As shown in Fig. 2, usually being collected The trigger that can be called at exploitation software platform (such as 2 softwares of QUARTUS) is single edge flip-flops, is enumerated in Fig. 2 Each trigger is rising edge triggering, and NOT gate can be added when failing edge triggering in clock end by needing to realize, but can not achieve Rising edge and failing edge triggering.Therefore, in CPLD schematic diagram development schemes, when the saltus step of clock edge is not fully utilized The utilization rate of clock only has 50%, if trigger can trigger overturning to two edges of clock pulses, so that it may when greatly improving The utilization rate of clock achievees the purpose that reduce power consumption.Circuit structure provided by the utility model is the D using single edging trigger Trigger is that the circuit structure of core realizes double edge trigger, to improve clock utilization, reduces circuit system power consumption.

A kind of CPLD dual-edge triggers circuit, it is mainly made of d type flip flop, data selector, NOT gate and XOR gate；

1, d type flip flop, NOT gate and XOR gate constitute the bilateral along dock signal generation unit of the utility model；Physical circuit Composition is as follows with structure：

D type flip flop is rising edge trigger circuit, and XOR gate is two input XOR gates；D type flip flop and XOR gate are to use CPLD principle diagram design mode calling systems library carries what unit module was realized.

The output end of d type flip flop is connect with the input terminal of the NOT gate；The output end of NOT gate and the triggering end D of d type flip flop Connection；The output end Q of d type flip flop is also connect with the first input end of XOR gate；The output end of XOR gate and the clock of d type flip flop End is connected；Second input terminal of XOR gate is connected with the output end of data selector.

2, data selector constitutes input clock signal selecting unit；Data selector selects 1 data selector, data for 4 1st selected data input pin of selector is connected with the signal output end of the 1st crystal oscillator, the 2nd selected data of data selector Input terminal is connected the letter of the 3rd selected data input pin and the 3rd crystal oscillator for stating data selector with the signal output end of the 2nd crystal oscillator Number output end is connected, and the 4th selected data input pin of data selector is connected with the signal output end of the 4th crystal oscillator；Exclusive or Second input terminal of door is connected with the output end of data selector.

In addition, the clock end of the 1st, 2,3 ... N output triggers is connected with the output end of XOR gate；1st, 2,3 ... N The triggering end of output trigger constitutes the 1st, 2,3 ... N triggering ends of multichannel dual-edge trigger circuit；1st, 2,3 ... N output The output end of trigger constitutes the 1st, 2,3 ... N output ends of multichannel dual-edge trigger circuit, and wherein N is the nature more than 3 Number.

Two, utility model works principle and the course of work are as follows：

1, bilateral along dock signal generation unit operation principle：Fig. 3 is emulated by developing software platform QUARTUS 2 Obtained oscillogram, in order to which convenient simulation (intercepts and needs defined label port name ability when the element circuit is emulated Emulated), the second input terminal of XOR gate is labeled as CLKIN in emulation, the clear terminal of d type flip flop is labeled as CLR, The output end of d type flip flop is labeled as Q, the output end of XOR gate is labeled as CLKOUT, is two clearer display circuits Waveform has obtained Fig. 4 after being amplified signal in software platform.It can be clearly seen that in CLKIN from Fig. 3 and Fig. 4 Rising edge and failing edge there is rising edge on CLKOUT when reaching, realize double edge signals and generate.Certain CLKIN's There are one time delay between rising edge arrival time and a rising edge of CLKOUT, the failing edge arrival time of CLKIN with Also there are one time delay between another secondary rising edge of CLKOUT, as can be seen from Figure 4 this delay time is about 5 to receive Second.

Concrete operating principle is as follows：The triggering end that the output end of d type flip flop passes through NOT gate and d type flip flop in the utility model Connection；The output end of d type flip flop and the first input end of XOR gate connect, when the second input terminal of XOR gate is as reception system The port of clock signal；When system starts, d type flip flop is reset, when the second input terminal of XOR gate (receives system clock letter Number port and 4 select the delivery outlet of 1 data selector) when being low level, according to XOR operation rule, two low level phases Exclusive or exports low level；When the rising edge of clock signal of system reaches, the second input terminal appearance of XOR gate is past from low level The saltus step of high level, according to XOR operation rule, the output of XOR gate also will occur saltus step from low level toward high level simultaneously, It that is to say that rising edge also occurs in the output end of XOR gate while rising edge occurs in clock signal of system, this rising edge signal is same When be also fed into the clock end of d type flip flop, the output end of d type flip flop, which is appointed, at this time is so maintained at the low level for resetting obtain before, this Low level is sent into the triggering end D of D triggers after NOT gate negates, and is stored in d type flip flop by d type flip flop after d type flip flop acquires Output end output (certainly this there are a delay time t), that is to say the output end Q of the d type flip flop in delay time t still Low level is kept, but high level then occurs after delay time t, after there is high level in the output end Q of d type flip flop, due to Second input terminal of XOR gate still maintains high level, and therefore XOR gate just exports low level, also occurs failing edge of course simultaneously, When failing edge occurs in the second input terminal of XOR gate, therefore pass through since the output end Q of d type flip flop still maintains high level XOR gate exports a rising edge (the failing edge thing followed low level that the second input terminal of XOR gate occurs after XOR operation It is high level with the high level phase exclusive or result of D trigger output ends Q, therefore namely will appear rising edge), in other words exist Clock signal of system occur under rise along while XOR gate output end occur a rising edge again, so in cycles in exclusive or The rising edge and failing edge of second input terminal of door correspond to the moment rising edge can occurs in the output end of XOR gate.

2, data selector constitutes input clock signal selecting unit operation principle

It is the 4 work originals for selecting 1 data selector that data selector, which constitutes input clock signal selecting unit operation principle, Reason selects D0 signals when selecting end input 00, the output signal of the 1st crystal oscillator is sent into the second input terminal of XOR gate；Selection Select D1 signals when end input 01, the output signal of the 2nd crystal oscillator be sent into the second input terminal of XOR gate, and so on choose not The output signal of same crystal oscillator.

The clock end of 1st, 2,3 ... N output triggers, which is connected with the output end of XOR gate, receives double edge signals, Operation principle is identical as common trigger, as shown in Figure 1, output trigger can be RS triggers, T triggers, d type flip flop, D-latch even can be accessed.These trigger resources can flexibly meet in Design of Digital System to basic sequential logic The demand of unit, designs for CPLD and brings flexibility.

The occupation mode of the utility model is as follows：Can be designed using the utility model circuit structure as CPLD one at Ripe unit uses, such as a Schematic blocks are created as in 2 softwares of QUARTUS, is called when needing.

Finally illustrate, above example is merely intended for describing the technical solutions of the present application, but not for limiting the present application, although ginseng The utility model is described in detail according to preferred embodiment, it will be understood by those of ordinary skill in the art that, it can be to this The technical solution of utility model is modified or replaced equivalently, without departing from the objective and model of technical solutions of the utility model It encloses, should all cover in the right of the utility model.

Claims (2)

1. a kind of CPLD dual-edge triggers circuit, it is characterised in that：It is mainly by d type flip flop, data selector, NOT gate and different Or door composition；The d type flip flop is rising edge trigger circuit；The XOR gate is two input XOR gates；

The output end of d type flip flop is connect with the input terminal of the NOT gate；The output end of the NOT gate and the triggering end of d type flip flop connect It connects；

The output end of d type flip flop is also connect with the first input end of XOR gate；The output end of XOR gate and the clock end of d type flip flop It is connected；Second input terminal of XOR gate is connected with the output end of data selector；The data selector selects 1 data for 4 1st selected data input pin of selector, the data selector is connected with the signal output end of the 1st crystal oscillator, the data 2nd selected data input pin of selector is connected with the signal output end of the 2nd crystal oscillator, and the 3rd of the data selector is selected Data input pin is connected with the signal output end of the 3rd crystal oscillator, the 4th selected data input pin of the data selector and the 4th The signal output end of crystal oscillator is connected；

The clock end of 1st, 2,3 ... N output triggers is connected with the output end of XOR gate；

The triggering end of 1st, 2,3 ... N output triggers constitutes the 1st, 2,3 ... N triggering ends of multichannel dual-edge trigger circuit；

The output end of 1st, 2,3 ... N output triggers constitutes the 1st, 2,3 ... N output ends of multichannel dual-edge trigger circuit.

2. a kind of CPLD dual-edge triggers circuit according to claim 1, it is characterised in that：The output trigger is Rest-set flip-flop or T triggers.