CN203895442U - Cell library and cell library-based integrated circuit structure - Google Patents
Cell library and cell library-based integrated circuit structure Download PDFInfo
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- CN203895442U CN203895442U CN201420226453.1U CN201420226453U CN203895442U CN 203895442 U CN203895442 U CN 203895442U CN 201420226453 U CN201420226453 U CN 201420226453U CN 203895442 U CN203895442 U CN 203895442U
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- 239000002184 metal Substances 0.000 claims abstract description 66
- 229910052751 metal Inorganic materials 0.000 claims abstract description 66
- 239000004020 conductor Substances 0.000 claims abstract description 53
- 239000004065 semiconductor Substances 0.000 claims abstract description 15
- 238000009792 diffusion process Methods 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims description 2
- 229910044991 metal oxide Inorganic materials 0.000 abstract 1
- 150000004706 metal oxides Chemical class 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The utility model discloses a cell library and a cell library-based integrated circuit structure. The cell library comprises cell areas which extend in a first direction and a second direction; the bottom layer of each cell area comprises an active area, a diffusion area and an MOS (metal oxide semiconductor) tube area of a gate strip area; and a conductor layer of each cell area comprises a plurality of conductors, a power wire and a ground wire. A wiring space of at least one first metal wiring is reserved on the conductor layer in each cell area by setting at least one area factor of the cell areas, and the area factor comprises one of the width of the power wire in a cell block, the width of the ground wire, the position and width of the conductors, and the position and the size of the active area. With adoption of the technical scheme provided by the utility model, the wiring resource can be increased by 10-15 percent, the resistance of a power supply ground wire is reduced, and the current intensity is increased.
Description
Technical field
The utility model relates to integrated circuit fields, especially a kind of cell library and the integrated circuit structure forming based on cell library.
Background technology
At present, integrated circuit (IC) is to the future development of high speed, miniaturization and low power consumption.In ic manufacturing process, a lot of IC manufacturing enterprises can provide the standard cell lib circuit that meets its technological standards to IC design companies, so that IC design companies is used.The cell library circuit that these YouIC manufacturing enterprises provide often has larger area, is unfavorable for reducing the area of wafer, and causes the production cost of IC to promote.
The standard cell lib circuit providing due to IC manufacturing enterprise designs often under the condition of minimum dimension, therefore, if tamper these standard cell lib circuit, may cause circuit after changing not meet the technological standards of IC manufacturing enterprise.
Therefore, how based on existing technological standards, these cell library circuit being improved, thereby reduce its area, and increase cabling resource, is the technical problem that current urgent need solves.
Utility model content
Based on above consideration, if propose a kind of can be based on existing technique, and the cell library that promotes cabling resource will be very favorable with the integrated circuit structure forming based on cell library.
One side of the present utility model, a kind of cell library has also been proposed, described cell library comprises: the unit area of extending along first direction, second direction, the bottom of described unit area comprise there is active region, the metal-oxide-semiconductor region in diffusion zone and gate strip region; The conductor layer of described unit area includes some conductors, power line, ground wire; By at least one Location factor of described unit area is set, thereby the wiring space of reserved at least one the first metal routings of the described conductor layer in described unit area, wherein, described Location factor comprise the width of power line described in described cell block, the position of the width of ground wire, conductor, the position of the width of conductor, active region, a kind of in the size of active region.
According to an embodiment of the present utility model, the width of described power line and/or ground wire is configured to that conductor layer in described unit area is reserved at least can hold the wiring space of first metal routing.
According to the length of unit area described in an embodiment of the present utility model and width, be configured to by stretching to be reserved with the wiring space of at least one the first metal routings in described unit area.
According to an embodiment of the present utility model, the distance between described conductor is configured to by reducing distance between described conductor to be reserved with the wiring space of at least one the first metal routings in described unit area.
On the other hand of the present utility model, a kind of integrated circuit structure forming based on cell library has also been proposed, it comprises: the some cell blocks that define in Semiconductor substrate, described cell block comprises respectively: the unit area of extending along first direction, second direction, the bottom of described unit area comprise there is active region, the metal-oxide-semiconductor region in diffusion zone and gate strip region; The conductor layer of described unit area includes some conductors, power line, ground wire; By at least one Location factor of described unit area is set, thereby the wiring space of reserved at least one the first metal routings of the described conductor layer in described unit area, wherein, described Location factor comprise the width of power line described in described cell block, the position of the width of ground wire, conductor, the position of the width of conductor, active region, a kind of in the size of active region; Described some cell blocks are carried out to metal routing coiling, wherein, based on described reserved wiring space, carry out the first metal routing coiling, thus the circuit function of realization.
According to an embodiment of the present utility model, the width of described power line and/or ground wire is configured to the wiring space at reserved at least one the first metal routings of the conductor layer of the inside of described cell block.
According to an embodiment of the present utility model, the length of described unit area and width are configured to by stretching to be reserved with the wiring space of at least one the first metal routings in described unit area
According to an embodiment of the present utility model, dwindle distance between described conductor and be configured to by reducing distance between described conductor to be reserved with the wiring space of at least one the first metal routings in described unit area.
The utility model is by reserved the cabling resource of at least one the first metals in standard cell lib, so the interconnection resource in rear end has increased 10-15%, and in the place of not using Metall cabling, increases the width of power ground.
Various aspects of the present utility model are by the explanation of the specific embodiment by hereinafter and more clear.
Accompanying drawing explanation
By with reference to accompanying drawing and read the following detailed description to non-limiting example, it is more obvious that other features, objects and advantages of the present utility model will become.
Fig. 1 is according to the standard cell of the utility model embodiment and the comparison diagram of standard cell of the prior art;
Fig. 2 is the flow chart according to the integrated circuit (IC) design of the utility model embodiment;
Fig. 3 is the first metal according to the utility model embodiment distribution map in domain.
In the drawings, run through different diagrams, same or similar Reference numeral represents same or analogous device (module) or step.
Embodiment
In the specific descriptions of following preferred embodiment, with reference to the appended accompanying drawing that forms the utility model part.Appended accompanying drawing shows by way of example can realize specific embodiment of the present utility model.The embodiment of example is not intended to limit according to all embodiment of the present utility model.Be appreciated that not departing under the prerequisite of scope of the present utility model, can utilize other embodiment, also can carry out the modification of structural or logicality.Therefore, following specific descriptions are also nonrestrictive, and scope of the present utility model is limited by appended claim.
The NAND gate (nand21d1) of two inputs of take is example, set forth the utility model from prior art different on standard cell circuit.
Fig. 1 is according to the standard cell of the utility model embodiment and the comparison diagram of standard cell of the prior art, wherein, the right be improvement after standard cell plane graph, the left side be standard cell figure of the prior art.
For the NAND gate before improvement, the source class of two PMOS pipes in parallel is to be all connected to power line VDD by the first metal (M1), and corresponding, in the NMOS pipe of two series connection, the source class of the NMOS pipe on the right is to be also connected to ground wire VSS by the first metal.From Fig. 1, can observe significantly, between the drain-source district of PMOS or NMOS pipe and VDD or VSS, have larger space.Although can carry out metal three (M3) cabling in space, but when manufacturing IC, the cabling of metal three is often restricted, therefore, standard cell of the prior art has increased the difficulty of follow-up cabling, and has limited the cabling resource of in unit are power line or ground wire.
In order to address the above problem, the utility model proposes a kind of cell library of the standard cell that has comprised improvement, it comprises: the unit area of extending along first direction (such as horizontal direction), second direction (such as vertical direction), the bottom of unit area comprise there is active region, the metal-oxide-semiconductor region in diffusion zone and gate strip region; The conductor layer of unit area includes some conductors, power line, ground wire; Power line width by setting unit piece region, line width, the position of conductor, width, thereby the inside of realizing some cell blocks is all reserved with respectively the wiring space of at least one metal routing in conductor layer.
Specifically, extend in the region of NAND gate respectively along continuous straight runs, vertical direction, its bottom comprises metal-oxide-semiconductor region and conductor layer, wherein metal-oxide-semiconductor district inclusion active region (source of corresponding metal-oxide-semiconductor, drain region), diffusion zone (the N well region of corresponding P pipe) and gate strip region (corresponding gate regions); Conductor layer comprises each layer of metal, power line and the ground wire in metal-oxide-semiconductor region.
In prior art, the active area 11 at drain-source place is connected with power line by the first metal 15, is connected.Because the first metal 15 is vertical with the trend of power line, therefore, cabling cannot be carried out for the first metal again in the region between drain-source and power line.
In the present embodiment, drain-source district is connected by active area 12 with power line, thereby saves metal wire 15, therefore without extra metal wire, connect.By above-mentioned structure, power line and source have formed the space that there is no metal M 1 cabling between leaking, and therefore, this region can be for increasing the width of power line or ground wire, or for other first metal routings.
Preferably, power line has the first width, ground wire has the second width, when these two width are greater than the minimum dimension in design rule, can arrange both width, for example reduce respectively or simultaneously one of both or both width, thus the wiring space of reserved at least one metal routing of the conductor layer in cell block.
Preferably, can also stretch to the overall region of cell block, increase length and/or the width of this unit area, thereby make can produce in the conductor layer of cell block inside the wiring space of reserved at least one metal wire.
Similarly, also can correspondingly dwindle the distance between some conductor (metal wire) in cell block, thus the wiring space of increase metal wire.
Known by foregoing, in the cell block of integrated circuit, can to the position of the position of active area, conductor layer and size, carry out suitable adjustment in the situation that meet the minimum dimension of design rule, thereby increase the wiring space of the metal wire in cell block.
Fig. 2 is the flow chart according to the integrated circuit (IC) design based on cell library of the utility model embodiment.
First, execution step S20: set up the cell library that includes some cell blocks.
In this step, cell library comprises a plurality of cell blocks, and extend along first, second direction the unit area of each cell block.For each unit area, it comprises metal-oxide-semiconductor region and conductor layer, wherein, and metal-oxide-semiconductor district inclusion active region, diffusion zone and gate strip region; Conductor layer comprises some conductors, power and ground.By the setting to each several part in metal-oxide-semiconductor region, conductor layer, can in unit area, reserve the wiring space that can hold metal routing.Particularly, can arrange power line width, position and the size of the position of line width, conductor and size, active region, and one or more in the position in gate strip region and size.
Be understandable that, metal routing is a kind of in holding wire, power and ground, and cell block is combinational logic gate or sequential logic gate.In addition, the adjustment to above-mentioned zone size or position, all needs to meet the design rule of current technique.
Optionally, power line has the first width, and ground wire has the second width, wherein, can, by adjusting the first width and/or the second width, so that the conductor layer in cell block is reserved, at least can hold the wiring space of a strip metal cabling.
Optionally, can stretch to the overall region of cell block, increase length and/or the width of this unit area, thereby in the conductor layer of cell block inside, the reserved wiring space that can hold at least one metal wire.
Similarly, also can correspondingly dwindle the distance between the conductor in cell block (metal wire), thus the wiring space of increase metal wire.
Then, execution step S21: layout units piece is in domain.
In this step, the input of unit piece, output correspondingly need to be connected, cell block is carried out to metal routing coiling, thereby realize the function of circuit.Due in step S20, in cell block, be reserved with the cabling space of the first metal wire, therefore, carrying out metal wire coiling, when especially power line or ground wire are wound the line, can, according to whether there being the cabling space of the first metal in cell block, adjust its live width.
When carrying out digital units self routing, by importing default net table (netlist), and then layout units is certainly in domain.
Then, execution step S22: the scope that detects the first metal routing coiling.
In this step, detect the scope in domain of the first metal routing coiling.
After having detected, will perform step S23: judge whether to be laid with the first metal routing
If do not lay the first metal routing near power line or ground wire, perform step S24, otherwise execution step S25.
In step S24, by the width that increases the power line do not lay the first metal routing, be the 3rd width, and/or the width that increases the ground wire of not laying the first metal routing is the 4th width, thereby increases the efficiency of unit are cabling.That is to say, if do not lay the first metal routing near power line, increase width to the three width of power line, same, if do not lay the first metal routing near ground wire, increase width to the four width of ground wire.
Preferably, the 3rd width is three to six times of the first width, and the 4th width is three to six times of the second width.
In step S25, owing to there is no the space of the first metal routing in cell block, therefore, need to maintain the width of power line or ground wire.
The utility model is by reserved the cabling resource of at least one the first metals in standard cell lib, so the interconnection resource in rear end has increased 10-15%, and in the place of not using the first metal routing, increases the width of power ground.
Fig. 3 is the first metal according to the utility model embodiment distribution map in domain, and in figure, VDD, VSS line all partly represent with oblique line
It is the practical situations of the standard cell lib after improvement: VDD does not walk the first metal in below, so utilize the art of this patent scheme to be increased to 0.99um, VSS top has increased first metal routing, as back end signal line SS.Finally reach following technique effect: 1) increase cabling resource 10-15%; 2) reduce the resistance of power ground, the space of saving, for increasing the width of metal, increases current strength.
To those skilled in the art, obviously the utility model is not limited to the details of above-mentioned one exemplary embodiment, and in the situation that not deviating from spirit of the present utility model or essential characteristic, can realize the utility model with other concrete form.Therefore, in any case, all should regard embodiment as exemplary, and be nonrestrictive.In addition, significantly, " comprising ", other elements and step do not got rid of in a word, and wording " one " is not got rid of plural number.A plurality of elements of stating in device claim also can be realized by an element.The first, the second word such as grade is used for representing title, and does not represent any specific order.
Claims (8)
1. a cell library, is characterized in that, described cell library comprises:
The unit area of extending along first direction, second direction, the bottom of described unit area comprise there is active region, the metal-oxide-semiconductor region in diffusion zone and gate strip region; The conductor layer of described unit area includes some conductors, power line, ground wire; By at least one Location factor of described unit area is set, thereby the wiring space of reserved at least one the first metal routings of the described conductor layer in described unit area, wherein, described Location factor comprise the width of power line described in described cell block, the position of the width of ground wire, conductor, the position of the width of conductor, active region, a kind of in the size of active region.
2. cell library according to claim 1, is characterized in that, the width of described power line and/or ground wire is configured to that conductor layer in described unit area is reserved at least can hold the wiring space of first metal routing.
3. cell library according to claim 1, is characterized in that, the length of described unit area and width are configured to be reserved with the wiring space of at least one the first metal routings in described unit area.
4. cell library according to claim 1, is characterized in that, between described conductor, distance is configured to be reserved with the wiring space of at least one the first metal routings in described unit area.
5. the integrated circuit structure forming based on cell library, is characterized in that, it comprises: the some cell blocks that define in Semiconductor substrate, and described cell block comprises respectively:
The unit area of extending along first direction, second direction, the bottom of described unit area comprise there is active region, the metal-oxide-semiconductor region in diffusion zone and gate strip region; The conductor layer of described unit area includes some conductors, power line, ground wire; By at least one Location factor of described unit area is set, thereby the wiring space of reserved at least one the first metal routings of the described conductor layer in described unit area, wherein, described Location factor comprise the width of power line described in described cell block, the position of the width of ground wire, conductor, the position of the width of conductor, active region, a kind of in the size of active region;
Described some cell blocks are carried out to metal routing coiling, wherein, based on described reserved wiring space, carry out the first metal routing coiling, thus the circuit function of realization.
6. integrated circuit structure according to claim 5, is characterized in that, the width of described power line and/or ground wire is configured to the wiring space at reserved at least one the first metal routings of the conductor layer of the inside of described cell block.
7. integrated circuit structure according to claim 5, is characterized in that, the length of described unit area and width are configured to by stretching to be reserved with the wiring space of at least one the first metal routings in described unit area.
8. integrated circuit structure according to claim 5, is characterized in that, the distance between described conductor is configured to by reducing distance between described conductor to be reserved with the wiring space of at least one the first metal routings in described unit area.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420226453.1U CN203895442U (en) | 2014-05-05 | 2014-05-05 | Cell library and cell library-based integrated circuit structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420226453.1U CN203895442U (en) | 2014-05-05 | 2014-05-05 | Cell library and cell library-based integrated circuit structure |
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| CN203895442U true CN203895442U (en) | 2014-10-22 |
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| CN201420226453.1U Expired - Lifetime CN203895442U (en) | 2014-05-05 | 2014-05-05 | Cell library and cell library-based integrated circuit structure |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105677968A (en) * | 2016-01-06 | 2016-06-15 | 深圳市同创国芯电子有限公司 | Method and device for drawing programmable logic device circuit diagram |
| CN103955582B (en) * | 2014-05-05 | 2018-08-24 | 格科微电子（上海）有限公司 | Method of designing integrated circuit based on cell library and its structure |
-
2014
- 2014-05-05 CN CN201420226453.1U patent/CN203895442U/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103955582B (en) * | 2014-05-05 | 2018-08-24 | 格科微电子（上海）有限公司 | Method of designing integrated circuit based on cell library and its structure |
| CN105677968A (en) * | 2016-01-06 | 2016-06-15 | 深圳市同创国芯电子有限公司 | Method and device for drawing programmable logic device circuit diagram |
| CN105677968B (en) * | 2016-01-06 | 2019-09-13 | 深圳市紫光同创电子有限公司 | Programmable logic device circuit drawing drawing method and device |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
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| CX01 | Expiry of patent term |
Granted publication date: 20141022 |