CN204118069U - A kind of power switch circuit chip structure - Google Patents
A kind of power switch circuit chip structure Download PDFInfo
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- CN204118069U CN204118069U CN201420586975.2U CN201420586975U CN204118069U CN 204118069 U CN204118069 U CN 204118069U CN 201420586975 U CN201420586975 U CN 201420586975U CN 204118069 U CN204118069 U CN 204118069U
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- power
- switch circuit
- power switch
- vddg
- circuit chip
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Abstract
The utility model provides a kind of power switch circuit chip structure, comprise N-type metal-oxide-semiconductor, source electrode power supply VSS, drain power VDD, substrate power line VDDG, described N-type metal-oxide-semiconductor is upper and lower overlay structure, the metal level of described substrate power line VDDG, source electrode power supply VSS is arranged on chip edge, described drain power VDD is connected with substrate power line VDDG straight line, and the utility model can reduce the surface area of power switch circuit chip on the whole.
Description
Technical field
The utility model relates to a kind of power switch circuit chip structure, belongs to integrated circuit fields.
Background technology
Existing sub-micro low-power chip structure, the wafer area that its power switch circuit used takies is larger, also be unfavorable for the connection of electric power network, therefore prior art chip structure is used to be unfavorable for that chip reduces area, and because the integrated level of chip constantly increases, function is more and more stronger, and their volume is more and more less, the power switch circuit chip structure that therefore a kind of volume is little, lightweight, efficiency is high in the urgent need to designing, performance is good.
Utility model content
Comparatively large in order to solve power switch circuit chip structure area, cost is high, the problem that power consumption is strong, and the utility model provides a kind of power switch circuit chip structure.
The utility model carrys out specific implementation by the following technical programs: a kind of power switch circuit chip structure, comprise N-type metal-oxide-semiconductor, source electrode power supply VSS, drain power VDD, substrate power line VDDG, described N-type metal-oxide-semiconductor is upper and lower overlay structure, the metal level of described substrate power line VDDG, source electrode power supply VSS is arranged on chip edge, and described drain power VDD is connected with substrate power line VDDG straight line.
Further improvement is, described N-type metal-oxide-semiconductor is in being uniformly distributed up and down.
Further improvement is, in described power switch circuit, the cabling height of substrate power line VDDG is consistent with two standard cell power line cabling height.
Compared to the prior art, the utility model has following improvement and advantage: (1) changes the plane figure of the rectangular N-type metal-oxide-semiconductor N1 of prior art into stacked on top of one another layout, has saved the surface area of chip.(2) the N-type metal-oxide-semiconductor N2 layout of prior art is changed on circuit arrange, make N-type metal-oxide-semiconductor layout in chip structure even.(3) by the substrate power line VDDG in chip structure, the metal level of source electrode power supply VSS is arranged on chip edge, is convenient to be connected with other standards unit power line straight line.(4) highly constant after chip structure correcting, lateral length reduces, and through the power switch circuit chip structure of above-mentioned design, the space of Appropriate application chip, can reduce the surface area of power switch circuit chip on the whole.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme in the embodiment of the present application, the accompanying drawing used required in describing is done further detailed annotation below to embodiment.
Fig. 1 is prior art power switch circuit chip structure schematic diagram;
Fig. 2 is the utility model power switch circuit chip structure schematic diagram;
Fig. 3 is the power line layout structure schematic diagram in prior art power switch circuit chip;
Fig. 4 is the power line layout structure schematic diagram in the utility model power switch circuit chip.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present application, clear, complete description is carried out to the technical scheme in the embodiment of the present application.
Fig. 1 is prior art power switch circuit chip structure schematic diagram, source electrode power supply VSS 605 lays respectively at two ends up and down of chip, substrate power line VDDG 603 is positioned at the centre position of chip, can find out, N-type metal-oxide-semiconductor N1, N2 of prior art adopt horizontal strip layout; As shown in Figure 2, for the utility model power switch circuit chip structure schematic diagram, can find out, the utility model is by the N-type metal-oxide-semiconductor N1 layout of prior art, change the stacked on top of one another layout of the N11 in Fig. 2 into, and the N-type metal-oxide-semiconductor N2 layout of prior art is changed to the N22 position in Fig. 2.
Fig. 3 is prior art power switch circuit chip power line layout structure schematic diagram, can find out, prior art uses single standard cell height, substrate power line VDDG 603 and drain power VDD 604 is made to adopt 90 degree of turnings to be connected like this, even if conveniently side circuit connection is changed to twice height and changes power line layout, area also can be larger, according to power switch circuit power supply connection request, in figure, the substrate power line VDDG 603 of the program status register psw 601 on the left side is connected with the drain power VDD 604 of the right standard cell std 602, need 90 degree to turn and connect substrate power line VDDG 603 and drain power VDD 604, in full chip, power switch circuit uses in a large number, adopt conventional power source switching circuit chip structure, power line can be increased and connect workload, increase power line planning complexity.
Fig. 4 is power line layout of the present utility model, a straight metal wire only need be drawn can to connect substrate power line VDDG 603 and drain power VDD 604, for a large amount of chip using power switch circuit, obviously can reduce workload, reduce power supply and connect complexity.Illustrate: use general 4000 N-type power switch circuits in the chips in some modules, calculate by conventional power source switch chip layout, in this module, the power switch circuit gross area is 4000 × 8.4 × 3.6=120960 μm
2. use power switch circuit chip structure of the present utility model, in this module, the power switch circuit gross area is 4000 × 5.7 × 3.6=76608 μm
2, compare with existing power supply switching circuit chip structure, its surface area decreases nearly 40%.
Below embodiment has been described in detail the utility model by reference to the accompanying drawings, and those skilled in the art can make many variations example to the utility model according to the above description.Thus, some details in embodiment should not formed restriction of the present utility model, the utility model by the scope that defines using appended claims as protection range of the present utility model.
Claims (3)
1. a power switch circuit chip structure, comprise N-type metal-oxide-semiconductor, source electrode power supply VSS, drain power VDD, substrate power line VDDG, it is characterized in that: described N-type metal-oxide-semiconductor is upper and lower overlay structure, the metal level of described substrate power line VDDG, source electrode power supply VSS is arranged on chip edge, and described drain power VDD is connected with substrate power line VDDG straight line.
2. power switch circuit chip structure as claimed in claim 1, is characterized in that: described N-type metal-oxide-semiconductor is the distribution of upper and lower even structure.
3. power switch circuit chip structure as claimed in claim 1, is characterized in that: in described power switch circuit, the cabling height of substrate power line VDDG is consistent with two standard cell power line cabling height.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201420586975.2U CN204118069U (en) | 2014-10-11 | 2014-10-11 | A kind of power switch circuit chip structure |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201420586975.2U CN204118069U (en) | 2014-10-11 | 2014-10-11 | A kind of power switch circuit chip structure |
Publications (1)
Publication Number | Publication Date |
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CN204118069U true CN204118069U (en) | 2015-01-21 |
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Family Applications (1)
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CN201420586975.2U Expired - Fee Related CN204118069U (en) | 2014-10-11 | 2014-10-11 | A kind of power switch circuit chip structure |
Country Status (1)
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CN (1) | CN204118069U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN114492290A (en) * | 2022-04-06 | 2022-05-13 | 飞腾信息技术有限公司 | Power switch planning method, device, equipment and storage medium of chip |
-
2014
- 2014-10-11 CN CN201420586975.2U patent/CN204118069U/en not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN114492290A (en) * | 2022-04-06 | 2022-05-13 | 飞腾信息技术有限公司 | Power switch planning method, device, equipment and storage medium of chip |
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Legal Events
Date | Code | Title | Description |
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C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150121 Termination date: 20161011 |
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CF01 | Termination of patent right due to non-payment of annual fee |