CN117040263B - Soft start circuit - Google Patents
Soft start circuit Download PDFInfo
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- CN117040263B CN117040263B CN202310975293.4A CN202310975293A CN117040263B CN 117040263 B CN117040263 B CN 117040263B CN 202310975293 A CN202310975293 A CN 202310975293A CN 117040263 B CN117040263 B CN 117040263B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/36—Means for starting or stopping converters
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The invention relates to the technical field of soft start, and discloses a soft start circuit, which comprises: the frequency division module is used for dividing the frequency of the external clock based on the output frequency division number of the soft start module to obtain a start delay clock or a soft start clock; the soft start module performs start delay, soft start delay counting, calculates the initial calculation value of the load voltage at the current moment, and compensates the initial calculation value of the load voltage at the current moment to obtain the calculation value of the load voltage at the current moment; selecting a load initial voltage value or a load voltage calculation value at the current moment as a soft start output at the current moment; the selection output module selects and outputs soft start output or normal voltage output at the current moment to the post-stage modulation module based on the soft start ending signal. The invention compensates the initial calculated value of the load voltage at the current moment, thereby overcoming the defect that the output voltage has errors due to the reasons of external environment, self process and the like; by monitoring the value of the output voltage in real time, the reliability of the soft start circuit is improved.
Description
Technical Field
The invention relates to the technical field of soft start, in particular to a soft start circuit.
Background
The DC-DC converter can cause transient current inrush and voltage overshoot during the start-up process to charge the capacitor, and if proper protection is not adopted, the power tube can overheat or even malfunction, and other devices can be lost. Therefore, a reasonable soft start scheme is one of the necessary ways to improve the reliability of the switching power supply. Soft start, which is to limit the duty cycle of PWM when the switching converter is started, control the output voltage to rise slowly, limit the starting current, and avoid the starting overshoot.
In the prior art, soft start is realized by adopting a software mode, and the output voltage is slowly increased by configuring the quantity of DAC codes in the start stage. The program is realized by a counter and a comparator, and firstly, the counter is cleared, and the counter counts with clock control signals. The counter is then compared to a target reference voltage value, and if the target value is not reached, the counter is incremented every clock cycle and remains after the target value is reached. The soft start time can be adjusted according to different clock periods, the power-on speed with controllable slope in the start process is realized, and the overshoot of the output voltage is effectively restrained in the DVS process of the output voltage. The output voltage value may be adjusted according to the target value. The pure software implementation requires the CPU to be involved all the time and does not take account of compensating for errors caused by the environment, external circuitry and manufacturing processes.
Disclosure of Invention
In view of this, the present invention provides a soft start circuit to solve the problem that the CPU is always involved in the soft start mode implemented by pure software and the error caused by the environment, the external circuit and the manufacturing process is not considered for compensation.
The invention provides a soft start circuit, comprising: the device comprises a frequency dividing module, a soft start module and a selection output module, wherein the input end of the frequency dividing module is connected with the output end of the soft start module, and the input end of the frequency dividing module is also input with an external clock, and is used for dividing the frequency of the external clock based on the output frequency dividing number of the soft start module to obtain a start delay clock or a soft start clock; the input end of the soft start module is connected with the output end of the frequency division module, and the input end of the soft start module is used for inputting a soft start starting signal, various electrical parameters and configuration parameters and sequentially counting the start delay and the soft start delay; after the soft start delay counting is finished, calculating an initial calculation value of the load voltage at the current moment, and compensating the initial calculation value of the load voltage at the current moment to obtain the calculation value of the load voltage at the current moment; selecting a load initial voltage value or a load voltage calculation value at the current moment as a soft start output at the current moment; the soft start output at the current moment is used for adjusting the duty ratio; and the selection output module is used for inputting normal voltage output at the input end and selecting and outputting soft start output or normal voltage output at the current moment to the later-stage modulation module based on the soft start ending signal.
The invention compensates the initial calculated value of the load voltage at the current moment, thereby overcoming the defect that the output voltage has errors due to the reasons of external environment, self process and the like; by monitoring the value of the output voltage in real time, the reliability of the soft start circuit is improved.
In an alternative embodiment, the soft start module includes: the device comprises a parameter calculation circuit, a frequency division number selection circuit, an initialization circuit, a delay counting circuit, an opening delay circuit, a soft start delay circuit, a voltage calculation circuit, a soft start ending circuit and a soft start error circuit, wherein the input end of the parameter calculation circuit inputs the opening delay time length, the soft start time length, a preset output value and a load initial voltage value, and the output end of the parameter calculation circuit is connected with the input end of the frequency division number selection circuit, the input end of the opening delay circuit, the input end of the soft start delay circuit and the input end of the voltage calculation circuit and is used for carrying out arithmetic operation based on the opening delay time length, the soft start time length, a preset output value and a load initial voltage value to obtain an opening delay frequency division number, an opening delay count value, a soft start step length, a soft start frequency division number and a soft start count value; the input end of the frequency division number selection circuit is connected with the output end of the start delay circuit and is used for selecting and outputting the start delay frequency division number or the soft start frequency division number based on the start delay frequency division number, the soft start frequency division number and the start delay end signal; the input end of the delay counting circuit is connected with the output end of the soft start ending circuit and the output end of the frequency dividing module, and the input end of the delay counting circuit is also input with a soft start starting signal which is used for starting to start delay counting or soft start delay counting based on the soft start starting signal, the start delay clock or the soft start clock; stopping counting based on the soft start end signal; the input end of the start delay circuit is connected with the output end of the delay counting circuit, the output end of the start delay circuit is connected with the input end of the voltage calculating circuit, and the start delay circuit is used for comparing the start delay counting value with the output of the delay counting circuit and outputting a start delay ending signal when the start delay counting value and the output of the delay counting circuit are equal; the input end of the soft start delay circuit is connected with the output end of the delay counting circuit and the output end of the start delay circuit, the output end of the soft start delay circuit is connected with the input end of the voltage calculating circuit, and the soft start delay circuit is used for comparing the soft start delay counting value with the output of the delay counting circuit and outputting a soft start delay ending signal when the soft start delay counting value and the output of the delay counting circuit are equal; the input end of the voltage calculation circuit inputs a load initial voltage value, the output end of the voltage calculation circuit is connected with the input end of the voltage calculation circuit, and the voltage calculation circuit is used for carrying out addition operation based on the soft start output, the load initial voltage value and the soft start step length at the last moment after the soft start delay is finished to obtain a load voltage initial calculated value at the current moment, and compensating the load voltage initial calculated value at the current moment to obtain a load voltage calculated value at the current moment; based on the start delay ending signal, selecting a load initial voltage value or a load voltage calculation value at the current moment as soft start output at the current moment; the soft start output at the current moment is used for adjusting the duty ratio; the input end of the soft start ending circuit is connected with the output end of the voltage calculating circuit, the input end of the soft start ending circuit is also used for inputting a preset output value, the output end of the soft start ending circuit is connected with the input end of the delay counting circuit and used for comparing the soft start output at the current moment with the preset output value, and when the soft start at the current moment is equal to the preset output value, a soft start ending signal is output; the input end of the soft start error circuit is connected with the output end of the voltage calculation circuit, the input end of the soft start error circuit is also used for inputting and outputting a voltage detection value, a preset error minimum value and a preset error maximum value, the soft start error circuit is used for comparing an operation result with the preset error minimum value and the preset error maximum value after carrying out arithmetic operation on the soft start output at the current moment and the output voltage detection value, and outputting a soft start error report when the operation result is larger than the preset error minimum value or smaller than the preset error maximum value; the input end of the initialization circuit is input with a load initial voltage value and a preset output value, the output end of the initialization circuit is connected with the input end of the voltage calculation circuit and the input end of the start delay circuit, and the initialization circuit is used for comparing the load initial voltage value with the preset output value, and when the load initial voltage value is smaller than the preset output value, the soft start module normally starts delay, soft start delay count and soft start output; when the initial voltage value of the load is larger than the preset output value, outputting a start delay ending signal to the start delay circuit, and after the soft start delay is ended, performing subtraction operation by the voltage calculation circuit based on the soft start output, the initial voltage value of the load and the soft start step length at the last moment.
The invention provides a programmable digital soft start circuit with compensation, which overcomes the defect that in the prior art, the output voltage generates errors due to the environment in the soft start process, and simultaneously increases the detection of the output voltage.
In an alternative embodiment, the parameter calculation circuit includes: the first arithmetic operation unit is used for inputting the opening delay time length at the input end, and the output end of the first arithmetic operation unit is connected with the input end of the opening delay circuit and the input end of the frequency division number selection circuit and used for obtaining an opening delay frequency division number and an opening delay count value based on the opening delay time length; and the output end of the second arithmetic operation unit is connected with the input end of the soft start delay circuit and the input end of the voltage calculation circuit and is used for obtaining a soft start step length, a soft start frequency division number and a soft start count value based on the soft start time length, the preset output value and the load initial voltage value.
In an alternative embodiment, the frequency division number selection circuit includes: and the input end of the first selection output unit is connected with the output end of the parameter calculation circuit and the output end of the start delay circuit.
In an alternative embodiment, the delay counting circuit comprises: the device comprises a delay counter, a first NOT gate and a first AND gate, wherein the input end of the first NOT gate is connected with the output end of the soft start ending circuit, and the output end of the first NOT gate is connected with the input end of the first AND gate; the input end of the first AND gate is also input with a soft start signal, and the output end of the first AND gate is connected with the input end of the delay counter; the input end of the delay counter is connected with the output end of the frequency dividing module, and the output end of the delay counter is respectively connected with the input end of the start delay circuit and the input end of the soft start delay circuit.
In an alternative embodiment, the turn-on delay circuit includes: the input end of the second NOT gate is connected with the output end of the first OR gate, and the output end of the second NOT gate is connected with the input end of the first comparator; the input end of the first comparator is connected with the output end of the parameter calculation circuit, the input end of the first comparator is also connected with the output end of the delay counting circuit, and the output end of the first comparator is connected with the input end of the first OR gate; and the input end of the first OR gate is also connected with the output end of the initializing circuit, and the output end of the first OR gate is also connected with the output end of the initializing circuit.
In an alternative embodiment, the soft start delay circuit includes: and the input end of the second comparator is connected with the output end of the delay counting circuit, the output end of the start delay circuit and the output end of the parameter calculating circuit, and the output end of the second comparator is connected with the input end of the voltage calculating circuit.
In an alternative embodiment, the initialization circuit includes: and the input end of the third comparator inputs the initial voltage value of the load and the preset output value, and the output end of the third comparator is connected with the input end of the first OR gate and the input end of the voltage calculation circuit.
In an alternative embodiment, the voltage control circuit includes: the input end of the third operation unit is input with a load initial voltage value, the input end of the third operation unit is also connected with the output end of the parameter calculation circuit and the output end of the initialization circuit, the input end of the third operation unit is also connected with the output end of the second selection output unit, and the output end of the third operation unit is connected with the voltage compensation unit; the output end of the voltage compensation unit is connected with the input end of the second selection output unit; and the input end of the second selection output unit is connected with the output end of the start delay circuit, the input end of the second selection output unit is also used for inputting a load initial voltage value, and the output end of the second selection output unit is connected with the input end of the soft start ending circuit and the input end of the soft start error circuit.
In an alternative embodiment, the soft start termination circuit includes: and the input end of the fourth comparator is connected with the output end of the voltage calculation circuit, and the input end of the fourth comparator is also input with a preset output value.
In an alternative embodiment, the soft start error circuit includes: the input end of the fourth operation unit is connected with the output end of the voltage calculation circuit, the input end of the fourth operation unit is also used for inputting and outputting a voltage detection value, and the output end of the fourth operation unit is connected with the input end of the fifth comparator; and the input end of the fifth comparator is also input with a preset error minimum value and a preset error maximum value.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a soft start circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a soft start process according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a soft start module according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a parameter calculation circuit according to an embodiment of the present invention;
fig. 5 is a schematic diagram of a frequency division number selection circuit according to an embodiment of the present invention;
FIG. 6 is a circuit topology of a soft start module according to an embodiment of the invention;
fig. 7 is a schematic diagram of yet another soft start procedure according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In this embodiment, there is provided a soft start circuit, as shown in fig. 1, including: the device comprises a frequency division module 1, a soft start module 2 and a selection output module 3.
Specifically, the input end of the frequency dividing module 1 is connected with the output end of the soft start module 2, and the input end of the frequency dividing module 1 is also input with an external clock, so that the external clock is divided based on the output frequency dividing number of the soft start module 2, and a start delay clock or a soft start clock is obtained.
Specifically, the input end of the soft start module 2 is connected with the output end of the frequency division module 1, the input end of the soft start module is used for inputting a soft start starting signal, various electrical parameters and configuration parameters, and the output end of the soft start module is connected with the input end of the selection output module and is used for sequentially counting start delay and soft start delay; after the soft start delay counting is finished, calculating an initial calculation value of the load voltage at the current moment, and compensating the initial calculation value of the load voltage at the current moment to obtain the calculation value of the load voltage at the current moment; selecting a load initial voltage value or a load voltage calculation value at the current moment as a soft start output at the current moment; the soft start output at the current time is used to adjust the duty cycle.
Specifically, as shown in fig. 2, the soft start circuit of the present embodiment includes two processes: the start delay process and the soft start process, the clock generated by the start delay frequency division number is referred to as a delay clock, and the clock generated by the soft start frequency division number is referred to as a soft start clock.
Optionally, the soft start module 2 of the present embodiment has the following functions to implement soft start:
(1) And performing arithmetic operation based on the start delay time length, the soft start time length, the preset output value and the load initial voltage value to obtain a start delay frequency division number, a start delay count value, a soft start step length, a soft start frequency division number and a soft start count value.
(2) The soft start module 2 selects and outputs the start delay clock or the soft start clock based on the start delay frequency division number, the soft start frequency division number, and the start delay end signal.
(3) The soft start module 2 performs an on delay based on the soft start signal, the on delay count value, and the on delay clock, and generates an on delay end signal after the on delay is ended.
(4) When the start delay is over, the soft start module 2 performs soft start delay based on the soft start delay clock and the soft start count value, and generates a soft start delay end signal after the soft start delay is over.
(5) After the soft start delay is finished, the soft start module 2 performs addition operation based on the soft start output, the load initial voltage value and the soft start step length at the last moment to obtain a load voltage initial calculated value at the current moment, and compensates the load voltage initial calculated value at the current moment to obtain a load voltage calculated value at the current moment; the soft start module 2 selects a load initial voltage value or a load voltage calculation value at the current moment as soft start output at the current moment based on the start delay ending signal; the soft start output at the current time is used to adjust the duty cycle.
(6) The soft start module 2 compares the soft start output at the current moment with a preset output value, and when the soft start at the current moment is equal to the preset output value, the soft start module outputs a soft start end signal.
(7) After the soft start module 2 performs arithmetic operation on the soft start output and the output voltage detection value at the current moment, comparing an operation result with a preset error minimum value and a preset error maximum value, and when the operation result is larger than the preset error minimum value or smaller than the preset error maximum value, comparing the operation result with the preset error minimum value or smaller than the preset error maximum value, and outputting a soft start error report by the soft start module 2.
(8) The soft start module 2 compares the load initial voltage value with a preset output value, and when the load initial voltage value is smaller than the preset output value, the soft start module 2 normally starts delay, soft start delay count and soft start output; when the load initial voltage value is larger than the preset output value, after the soft start delay is finished, the soft start module 2 performs subtraction operation based on the soft start output, the load initial voltage value and the soft start step length at the last moment.
Specifically, the input end of the selection output module is also input with normal voltage output, and the selection output module selects and outputs soft start output or normal voltage output at the current moment to the post-stage modulation module based on a soft start ending signal.
As shown in fig. 1, the soft start end signal is a control signal of the selection output module, and when the selection output module does not receive the soft start end signal, it outputs a normal voltage to a post-modulation module (e.g., DPWM); when the selective output module receives the soft start ending signal, the selective output module sends the soft start output at the current moment to the post-stage modulation module.
In some alternative embodiments, as shown in fig. 3, the soft start module 2 includes: the parameter calculation circuit 21, the frequency division number selection circuit 22, the initialization circuit 23, the delay counting circuit 24, the on delay circuit 25, the soft start delay circuit 26, the voltage calculation circuit 27, the soft start end circuit 28, and the soft start error circuit 29.
As shown in fig. 3, the parameter calculation circuit 21 has an input end for inputting a start delay time, a soft start time, a preset output value, and a load initial voltage value, and an output end connected to an input end of the frequency division number selection circuit 22, an input end of the start delay circuit 25, an input end of the soft start delay circuit 26, and an input end of the voltage calculation circuit 27, and is configured to perform an arithmetic operation based on the start delay time, the soft start time, the preset output value, and the load initial voltage value to obtain a start delay frequency division number, a start delay count value, a soft start step length, a soft start frequency division number, and a soft start count value.
Alternatively, as shown in fig. 4, the parameter calculation circuit 21 includes a first arithmetic operation unit 211 and a second arithmetic operation unit 212.
The first arithmetic operation unit 211 has an input end for inputting the on delay time, and an output end connected to the input end of the on delay circuit 25 and the input end of the frequency division number selection circuit 22, and is configured to obtain an on delay frequency division number and an on delay count value based on the on delay time.
The second arithmetic operation unit 212 has an input terminal for inputting a soft start duration, a preset output value, and a load initial voltage value, and an output terminal connected to the input terminal of the soft start delay circuit 26 and the input terminal of the voltage calculation circuit 27, and is configured to obtain a soft start step size, a soft start frequency division number, and a soft start count value based on the soft start duration, the preset output value, and the load initial voltage value.
As shown in fig. 3, an input terminal of the frequency division number selection circuit 22 is connected to an output terminal of the on delay circuit 25, and is configured to select and output an on delay frequency division number or a soft start frequency division number based on an on delay frequency division number, a soft start frequency division number, and an on delay end signal.
Optionally, the frequency division number selection circuit 22 includes: the input end of the first selection output unit is connected with the output end of the parameter calculation circuit 21 and the output end of the start delay circuit 25.
Specifically, as shown in fig. 5, when the start delay end signal is not received by the frequency division number selection circuit 22, the start delay frequency division number is output through the "0" terminal of the two-way selector, and when the start delay end signal is received by the frequency division number selection circuit 22, the soft start frequency division number is output through the "1" terminal of the two-way selector.
As shown in fig. 3, the input end of the delay counting circuit 24 is connected to the output end of the soft start ending circuit 28 and the output end of the frequency dividing module 1, and a soft start signal is also input to the input end of the delay counting circuit for starting to start the delay counting or the soft start delay counting based on the soft start signal, the start delay clock or the soft start clock; based on the soft start end signal, the counting is stopped.
Alternatively, as shown in fig. 6, the delay counting circuit includes: the delay counter U1, the first NOT gate U2 and the first AND gate U3, wherein the input end of the first NOT gate U2 is connected with the output end of the soft start ending circuit 28 (namely U10), and the output end of the first NOT gate U2 is connected with the input end of the first AND gate U3; the input end of the first AND gate U3 is also input with a soft start signal, and the output end of the first AND gate U3 is connected with the input end of the delay counter U1; the input end of the delay counter U1 is connected with the output end of the frequency division module 1, and the output end of the delay counter U1 is respectively connected with the input end of the start delay circuit 25 (namely U5) and the input end of the soft start delay circuit 26 (namely U7).
Specifically, the levels of the soft start end signal and the soft start signal are opposite, and when the input end of the and gate is at the same level, namely the level of the soft start signal, the delay counter U1 starts counting; since this embodiment is divided into two processes, as shown in fig. 2, the delay counter U1 counts based on the start delay clock first, and counts based on the soft start clock after the start delay is completed.
As shown in fig. 3, the on delay circuit has an input terminal connected to the output terminal of the delay counting circuit 24, an output terminal connected to the input terminal thereof, and an output terminal connected to the input terminal of the voltage calculating circuit 27, and is configured to compare the on delay count value with the output of the delay counting circuit 24, and output an on delay end signal when the on delay count value and the output are equal.
Optionally, as shown in fig. 6, the turn-on delay circuit 25 includes: the input end of the second NOT gate U4 is connected with the output end of the first OR gate U6, and the output end of the second NOT gate U4 is connected with the input end of the first comparator U5; the input end of the first comparator U5 is connected with the output end of the parameter calculation circuit 21, the input end of the first comparator U5 is also connected with the output end of the delay counting circuit (namely U1), and the output end of the first comparator U5 is connected with the input end of the first OR gate U6; the first or gate U6 has its input terminal connected to the output terminal of the initializing circuit 23 (i.e., U13) and its output terminal connected to the output terminal of the initializing circuit 23 (i.e., U13).
Specifically, after the main control module in the digital power supply enables the soft start signal, the delay counter U1 starts to count up from zero under the control of the start delay clock, the count value is compared with the start delay count value, if the count value is compared with the start delay count value, the first comparator U5 pulls up the start delay end signal, and simultaneously clears the delay counter U1.
As shown in fig. 3, the input end of the soft start delay circuit 26 is connected to the output end of the delay counting circuit 24 and the output end of the turn-on delay circuit, and the output end thereof is connected to the input end of the voltage calculating circuit 27, so as to compare the soft start delay count value with the output of the delay counting circuit 24, and when the two values are equal, output a soft start delay end signal.
Alternatively, as shown in fig. 6, the soft start delay circuit 26 includes: the input end of the second comparator U7 is connected to the output end of the delay counting circuit (i.e., U1), the output end of the turn-on delay circuit (i.e., U6), and the output end of the parameter calculation circuit 21, and the output end thereof is connected to the input end of the voltage calculation circuit 27 (i.e., U8).
Specifically, after the start delay signal is pulled high, the clock of the delay counter U1 becomes a soft start clock, the delay counter U1 starts to count up from zero under the control of the soft start clock, the count value is compared with the soft start count value, if the count value and the soft start count value are equal, a high level, namely a soft start delay end signal is output, and meanwhile the delay counter U1 is cleared. The rising edge of the next soft start clock comes, and the delay counter U1 starts counting again.
As shown in fig. 3, the voltage calculating circuit 27 has an input end for inputting a load initial voltage value, and an output end connected to the input end thereof, and is configured to perform addition operation based on the soft start output, the load initial voltage value, and the soft start step length at the last time after the soft start delay is completed, to obtain a load voltage initial calculated value at the current time, and to compensate the load voltage initial calculated value at the current time, to obtain a load voltage calculated value at the current time; based on the start delay ending signal, selecting a load initial voltage value or a load voltage calculation value at the current moment as soft start output at the current moment; the soft start output at the current time is used to adjust the duty cycle.
Alternatively, as shown in fig. 6, the voltage control circuit includes: the input end of the third operation unit U8 inputs the initial voltage value of the load, the input end of the third operation unit U8 is also connected with the output end of the parameter calculation circuit 21 and the output end of the initialization circuit 23 (i.e., U13), the input end of the third operation unit U8 is also connected with the output end of the second selection output unit, and the output end of the third operation unit U8 is connected with the voltage compensation unit 271; the output end of the voltage compensation unit 271 is connected with the input end of the second selection output unit U9; the second selection output unit U9 has an input terminal connected to the output terminal of the turn-on delay circuit 25 (i.e., U6), an input terminal for inputting the initial voltage value of the load, and an output terminal connected to the input terminal of the soft start ending circuit 28 (i.e., U10) and the input terminal of the soft start error circuit 29 (i.e., U11).
Alternatively, the voltage compensation unit 271 incorporates a compensation table established for each voltage value in correspondence with a preset voltage value, so as to select a corresponding compensation voltage for the current calculated value.
Specifically, the initial value of the third operation unit U8 is a load initial voltage value, and when the soft start delay is finished, the third operation unit U8 starts to perform addition operation on the soft start output based on the soft start step length.
As shown in fig. 3, the soft start ending circuit 28 has an input terminal connected to the output terminal of the voltage calculating circuit 27, an input terminal further inputs a preset output value, an output terminal connected to the input terminal of the delay counting circuit 24, and is configured to compare the soft start output at the current moment with the preset output value, and output a soft start ending signal when the soft start at the current moment is equal to the preset output value, and the delay counter U1 does not count any more. .
Alternatively, as shown in fig. 6, the soft start end circuit 28 includes: the input end of the fourth comparator U10 is connected to the output end of the voltage calculation circuit 27 (i.e., U9), and the input end thereof is also inputted with a preset output value.
As shown in fig. 3, the soft-start error circuit 29 has an input terminal connected to the output terminal of the voltage calculation circuit 27, and further has an input terminal for inputting and outputting a voltage detection value, a preset error minimum value, and a preset error maximum value, and is configured to perform an arithmetic operation on the soft-start output at the current time and the output voltage detection value, compare the operation result with the preset error minimum value and the preset error maximum value, and output a soft-start error report when the operation result is greater than the preset error minimum value or less than the preset error maximum value.
Alternatively, as shown in fig. 6, the soft start error circuit 29 includes: the input end of the fourth operation unit U11 is connected with the output end of the voltage calculation circuit 27 (i.e., U9), the input end of the fourth operation unit U11 is also input and output with a voltage detection value, and the output end of the fourth operation unit U11 is connected with the input end of the fifth comparator U12; the fifth comparator U12 further has an input terminal for inputting a preset error minimum value and a preset error maximum value.
Specifically, the soft start output and the output voltage detection value are compared with a preset error value through a fifth comparator U12 after arithmetic operation, if the difference value is no longer within the error allowable range, the error of an external circuit is indicated at the moment, an error signal in the soft start process is pulled high, and the main control in the digital power supply is notified to react.
As shown in fig. 3, the initializing circuit 23 has an input end for inputting a load initial voltage value and a preset output value, and an output end connected to the input end of the voltage calculating circuit 27 and the input end of the start-up delay circuit 25, and is configured to compare the load initial voltage value with the preset output value, and when the load initial voltage value is smaller than the preset output value, the soft start module 2 normally starts up delay, soft start delay count and soft start output; when the load initial voltage value is greater than the preset output value, the start delay ending signal is output to the start delay circuit 25, and after the soft start delay is ended, the voltage calculation circuit 27 performs subtraction operation based on the soft start output, the load initial voltage value and the soft start step length at the last moment.
Alternatively, as shown in fig. 6, the initialization circuit 23 includes: the input end of the third comparator U13 inputs the initial voltage value of the load and the preset output value, and the output end of the third comparator U is connected to the input end of the first or gate U6 and the input end of the voltage calculating circuit 27 (i.e., U8).
Specifically, the initialization circuit 23 initiates voltage conditions for two different loads:
(1) If the load initial voltage value is smaller than or equal to the preset output value, the third comparator U13 outputs a low level to perform normal delay and soft start processes.
(2) In order to avoid the situation that the output voltage suddenly drops, as shown by a dotted line in fig. 7, soft shutdown is performed when the initial voltage value of the load is greater than the preset output value. At this time, the third comparator U13 outputs a high level, and the third operation unit U8 performs a subtraction operation on the soft start output and the soft start step size without performing a delay process.
As an example of verification in this embodiment, each parameter is shown in table 1, and after the soft start module 2 is configured as required, a soft start signal is given. The soft start signal controls the analog-to-digital conversion module to sample the load initial voltage value, and at the same time, the two arithmetic operation units shown in fig. 4 start calculating parameters, and taking the conditions shown in table 1 as an example, each parameter of table 2 and table 3 can be obtained, wherein table 2 and table 3 are parameters under the condition that the load initial voltage is 0V and the load initial voltage is 5V respectively.
TABLE 1
| External clock | 100MHz |
| Duration of turn-on delay | 100ms |
| Duration of soft start | 500ms |
| Preset output value | 3.3V |
| Maximum frequency division coefficient | 100 |
TABLE 2
| Start delay division number | 100 |
| On delay count value | 100 |
| Soft start step size | 3.3V/500ms＝6.6mV/ms |
| Soft start frequency divider | 50 |
| Soft start count value | 1 |
TABLE 3 Table 3
| Start delay division number | 100 |
| On delay count value | 100 |
| Soft start step size | 6.6mV/ms |
| Soft start frequency divider | 50 |
| Soft start count value | 1 |
Taking the load initial voltage of 0V as an example, after sampling to 0V, the third comparator U13 outputs a low level, the circuit enters an on delay stage, the clock of the delay counter is an on delay clock, after counting to 100, the first comparator U5 outputs a high level, an on delay ending signal is pulled up, the clock is switched to a soft start clock, the second comparator U7 starts to work, when the delay counter counts to 1 under the driving of the soft start clock, the second comparator U7 outputs a high level as a clock signal of the third arithmetic operation unit, each rising edge is added with a voltage of 6.6mV, the obtained result is a soft start output after passing through a compensation table, when the soft start output rises to 3.3V, the fourth comparator U10 outputs a high level, a soft start ending signal is generated, and the whole soft start process is completed.
Taking the load initial voltage of 5V as an example, after sampling the output of 5V, the third comparator U13 outputs a high level, the first comparator U5 stops working, the start delay end signal is pulled high, the clock is switched to the soft start clock, the second comparator U7 starts working, when the delay counter counts to 1 under the drive of the soft start clock, the second comparator U7 outputs a high level as a clock signal of the third arithmetic operation unit, each rising edge subtracts a voltage of 6.6mV, the obtained result is the soft start output after passing through a compensation table, when the soft start output is reduced to 3.3V, the fourth comparator U10 outputs a high level, and a soft start end signal is generated, and the whole soft start process is completed.
Although embodiments of the present invention have been described in connection with the accompanying drawings, various modifications and variations may be made by those skilled in the art without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope of the invention as defined by the appended claims.
Claims (10)
1. A soft start circuit, comprising: the device comprises a frequency division module, a soft start module and a selection output module, wherein,
the input end of the frequency dividing module is connected with the output end of the soft start module, and the input end of the frequency dividing module is also input with an external clock, and is used for dividing the frequency of the external clock based on the output frequency dividing number of the soft start module to obtain a start delay clock or a soft start clock;
the input end of the soft start module is connected with the output end of the frequency division module, and the input end of the soft start module is used for inputting a soft start starting signal, various electrical parameters and configuration parameters and sequentially counting start delay and soft start delay; after the soft start delay counting is finished, calculating an initial calculation value of the load voltage at the current moment, and compensating the initial calculation value of the load voltage at the current moment to obtain the calculation value of the load voltage at the current moment; selecting a load initial voltage value or the load voltage calculated value at the current moment as soft start output at the current moment; the soft start output at the current moment is used for adjusting the duty ratio;
the input end of the selection output module is also input with normal voltage output, and the selection output module selects and outputs soft start output or normal voltage output at the current moment to the post-stage modulation module based on a soft start ending signal;
the soft start module comprises: a parameter calculation circuit, a frequency division number selection circuit, an initialization circuit, a delay counting circuit, a start delay circuit, a soft start delay circuit, a voltage calculation circuit, a soft start ending circuit and a soft start error circuit, wherein,
the input end of the parameter calculation circuit is connected with the input end of the frequency division number selection circuit, the input end of the starting delay circuit, the input end of the soft start delay circuit and the input end of the voltage calculation circuit, and is used for carrying out arithmetic operation based on the starting delay time, the soft start time, the preset output value and the load initial voltage value to obtain a starting delay frequency division number, a starting delay count value, a soft start step length, a soft start frequency division number and a soft start count value;
the input end of the frequency division number selection circuit is connected with the output end of the start delay circuit and is used for selecting and outputting the start delay frequency division number or the soft start frequency division number based on the start delay frequency division number, the soft start frequency division number and the start delay ending signal;
the input end of the delay counting circuit is connected with the output end of the soft start ending circuit and the output end of the frequency dividing module, and a soft start starting signal is also input into the input end of the delay counting circuit and is used for starting to start delay counting or soft start delay counting based on the soft start starting signal, the start delay clock or the soft start clock; stopping counting based on the soft start end signal;
the input end of the start delay circuit is connected with the output end of the delay counting circuit, the output end of the start delay circuit is connected with the input end of the voltage counting circuit, and the start delay circuit is used for comparing the start delay counting value with the output of the delay counting circuit and outputting a start delay ending signal when the start delay counting value and the output of the delay counting circuit are equal;
the input end of the soft start delay circuit is connected with the output end of the delay counting circuit and the output end of the start delay circuit, the output end of the soft start delay circuit is connected with the input end of the voltage calculating circuit, and the soft start delay circuit is used for comparing the soft start delay counting value with the output of the delay counting circuit and outputting a soft start delay ending signal when the soft start delay counting value and the output of the delay counting circuit are equal;
the input end of the voltage calculation circuit is input with a load initial voltage value, the output end of the voltage calculation circuit is connected with the input end of the voltage calculation circuit, and the voltage calculation circuit is used for carrying out addition operation based on the soft start output, the load initial voltage value and the soft start step length at the last moment after the soft start delay is finished to obtain a load voltage initial calculated value at the current moment, and compensating the load voltage initial calculated value at the current moment to obtain a load voltage calculated value at the current moment; based on a start delay ending signal, selecting the load initial voltage value or the load voltage calculated value at the current moment as soft start output at the current moment; the soft start output at the current moment is used for adjusting the duty ratio;
the input end of the soft start ending circuit is connected with the output end of the voltage calculating circuit, the input end of the soft start ending circuit is also used for inputting a preset output value, the output end of the soft start ending circuit is connected with the input end of the delay counting circuit and used for comparing the soft start output at the current moment with the preset output value, and when the soft start at the current moment is equal to the preset output value, a soft start ending signal is output;
the input end of the soft start error circuit is connected with the output end of the voltage calculation circuit, the input end of the soft start error circuit is also used for inputting and outputting a voltage detection value, a preset error minimum value and a preset error maximum value, the soft start error circuit is used for comparing an operation result with the preset error minimum value and the preset error maximum value after carrying out arithmetic operation on the soft start output at the current moment and the output voltage detection value, and outputting a soft start error report when the operation result is larger than the preset error minimum value or smaller than the preset error maximum value;
the input end of the initialization circuit is input with a load initial voltage value and a preset output value, the output end of the initialization circuit is connected with the input end of the voltage calculation circuit and the input end of the start delay circuit, and is used for comparing the load initial voltage value with the preset output value, and when the load initial voltage value is smaller than the preset output value, the soft start module normally starts delay, soft start delay count and soft start output; when the load initial voltage value is larger than the preset output value, outputting an opening delay ending signal to an opening delay circuit, and after the soft start delay is ended, performing subtraction operation by the voltage calculation circuit based on the soft start output at the last moment, the load initial voltage value and the soft start step length.
2. The soft start circuit of claim 1, wherein the parameter calculation circuit comprises:
the input end of the first arithmetic operation unit is input with the opening delay time length, and the output end of the first arithmetic operation unit is connected with the input end of the opening delay circuit and the input end of the frequency division number selection circuit and is used for obtaining an opening delay frequency division number and an opening delay count value based on the opening delay time length;
and the input end of the second arithmetic operation unit is input with the soft start duration, the preset output value and the load initial voltage value, and the output end of the second arithmetic operation unit is connected with the input end of the soft start delay circuit and the input end of the voltage calculation circuit and is used for obtaining the soft start step length, the soft start frequency division number and the soft start count value based on the soft start duration, the preset output value and the load initial voltage value.
3. The soft start circuit of claim 1, wherein the frequency divider selection circuit comprises:
and the input end of the first selection output unit is connected with the output end of the parameter calculation circuit and the output end of the start delay circuit.
4. The soft start circuit of claim 1, wherein the delay counting circuit comprises: a delay counter, a first NOT gate and a first AND gate, wherein,
the input end of the first NOT gate is connected with the output end of the soft start ending circuit, and the output end of the first NOT gate is connected with the input end of the first AND gate;
the input end of the first AND gate is also input with a soft start signal, and the output end of the first AND gate is connected with the input end of the delay counter;
and the input end of the delay counter is connected with the output end of the frequency dividing module, and the output end of the delay counter is respectively connected with the input end of the start delay circuit and the input end of the soft start delay circuit.
5. The soft start circuit of claim 1, wherein the turn-on delay circuit comprises: a second NOT gate, a first comparator and a first OR gate, wherein,
the input end of the second NOT gate is connected with the output end of the first OR gate, and the output end of the second NOT gate is connected with the input end of the first comparator;
the input end of the first comparator is connected with the output end of the parameter calculation circuit, the input end of the first comparator is also connected with the output end of the delay counting circuit, and the output end of the first comparator is connected with the input end of the first OR gate;
and the input end of the first OR gate is also connected with the output end of the initializing circuit, and the output end of the first OR gate is also connected with the output end of the initializing circuit.
6. The soft start circuit of claim 1, wherein the soft start delay circuit comprises:
and the input end of the second comparator is connected with the output end of the delay counting circuit, the output end of the start delay circuit and the output end of the parameter calculating circuit, and the output end of the second comparator is connected with the input end of the voltage calculating circuit.
7. The soft start circuit of claim 5, wherein the initialization circuit comprises:
and the input end of the third comparator inputs a load initial voltage value and a preset output value, and the output end of the third comparator is connected with the input end of the first OR gate and the input end of the voltage calculation circuit.
8. The soft start circuit of claim 1, wherein the voltage control circuit comprises: a third operation unit, a voltage compensation unit and a second selection output unit, wherein,
the input end of the third operation unit is input with a load initial voltage value, the input end of the third operation unit is also connected with the output end of the parameter calculation circuit and the output end of the initialization circuit, the input end of the third operation unit is also connected with the output end of the second selection output unit, and the output end of the third operation unit is connected with the voltage compensation unit;
the output end of the voltage compensation unit is connected with the input end of the second selection output unit;
and the input end of the second selection output unit is connected with the output end of the start delay circuit, the input end of the second selection output unit is also used for inputting a load initial voltage value, and the output end of the second selection output unit is connected with the input end of the soft start ending circuit and the input end of the soft start error circuit.
9. The soft start circuit of claim 1, wherein the soft start end circuit comprises:
and the input end of the fourth comparator is connected with the output end of the voltage calculation circuit, and the input end of the fourth comparator is also input with a preset output value.
10. The soft start circuit of claim 1, wherein the soft start error circuit comprises: a fourth operation unit and a fifth comparator, wherein,
the input end of the fourth operation unit is connected with the output end of the voltage calculation circuit, the input end of the fourth operation unit is used for inputting and outputting a voltage detection value, and the output end of the fourth operation unit is connected with the input end of the fifth comparator;
and the input end of the fifth comparator is also input with a preset error minimum value and a preset error maximum value.
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