KR20210029400A - Delay line, delay locked loop circuit and semiconductor apparatus using the same - Google Patents

Abstract

A delay locked loop circuit includes a first delay locked loop and a second delay locked loop having different characteristics from each other. The first delay locked loop performs a delay-locking operation on a reference clock signal to generate a delay locked clock signal. The second delay locked loop performs the delay-locking operation on the delay locked clock signal to generate an internal clock signal. According to the present invention, it is possible to generate the plurality of internal clock signals through an analog delay locked loop.

Description

Delay line, delay locked loop circuit, and semiconductor device using the same {DELAY LINE, DELAY LOCKED LOOP CIRCUIT AND SEMICONDUCTOR APPARATUS USING THE SAME}

The present invention relates to an integrated circuit technology, and more particularly, to a delay line, a delay locked loop circuit, and a semiconductor device using the same.

Electronic devices include many electronic components, and among them, a computer system may include many semiconductor devices composed of semiconductors. Semiconductor devices constituting a computer system may communicate with each other by transmitting and receiving clock signals and data. The semiconductor devices may operate in synchronization with a clock signal. The semiconductor devices may transmit and/or receive an external device (ie, another semiconductor device) and a system clock signal from each other, and transmit and receive data in synchronization with the system clock signal. The semiconductor devices may include a clock buffer and/or a receiver to receive the system clock signal and transmit the received system clock signal to an internal circuit related to a data input/output operation and an internal circuit that operates in synchronization with the clock signal. Accordingly, a phase difference may occur between a clock signal received by the internal circuits and the system clock signal due to a delay time generated inside the semiconductor devices. Accordingly, semiconductor devices are provided with a delay locked loop circuit to compensate for the above phase difference. Typically, a digital delay locked loop using a digital controlled delay line and an analog delay locked loop using a voltage controlled delay line. Is used as the delay locked loop circuit.

An embodiment of the present invention may provide a delay locked loop circuit capable of performing a delay fixing operation through a digital delay locked loop and generating a plurality of internal clock signals through an analog delay locked loop, and a semiconductor device using the same.

Embodiments of the present invention can provide a delay locked loop circuit including a correction circuit capable of compensating for mismatch inherent in an analog delay locked loop, and a semiconductor device using the same.

An embodiment of the present invention may provide a delay cell capable of improving a swing width of an output signal using a feedback method, a delay line including the same, a delay locked loop, and a semiconductor device.

An embodiment of the present invention can provide a delay locked loop circuit capable of performing a delay fixing operation by selectively or together using a digital delay locked loop and an analog delay locked loop according to a frequency of a clock signal, and a semiconductor device using the same.

A delay locked loop circuit according to an embodiment of the present invention includes: a first delay locked loop for generating a delay locked clock signal by performing a delay fixing operation on the reference clock signal based on a reference clock signal and an internal clock signal; And a second delay locked loop configured to generate the internal clock signal by performing a delay fixing operation on the delay locked clock signal based on the delay locked clock signal and the internal clock signal.

A semiconductor device according to an embodiment of the present invention includes a clock receiver that buffers an external clock signal and outputs a buffered clock signal; A divider circuit for generating a reference clock signal by dividing the buffered clock signal, and selectively outputting the buffered clock signal based on a frequency information signal; Performing a delay fixing operation based on the reference clock signal and one of a first output clock signal and a second output clock signal based on the frequency information signal to generate a first fixed delay clock signal from the reference clock signal, and the A first delay locked loop for generating a second delay locked clock signal from the buffered clock signal; A second delay locked loop for generating the first output clock signal by performing a delay fixing operation on the first delayed fixed clock signal based on the first delayed fixed clock signal and the first output clock signal; And a clock generation circuit that generates a second output clock signal based on the second delayed fixed clock signal.

A delay locked loop according to an embodiment of the present invention includes: a voltage controlled delay line for generating an internal clock signal and a feedback clock signal by delaying a reference clock signal based on a delay control voltage; A correction circuit for generating a delayed reference clock signal and a delayed feedback clock signal by delaying the internal clock signal and the feedback clock signal based on phases of the internal clock signal and the feedback clock signal; A phase detector comparing phases of the delayed reference clock signal and the delayed feedback clock signal to generate a phase detection signal; And a charge pump generating the delay control voltage based on the phase detection signal.

The embodiment of the present invention enables a precise delay fixing operation in a semiconductor device operating at a high speed to generate an internal clock signal having a desired phase. Accordingly, it is possible to improve the reliability and operation performance of the semiconductor device.

1 is a diagram illustrating a configuration of a semiconductor device according to an embodiment of the present invention.
2 is a diagram showing the configuration of a delay locked loop circuit according to an embodiment of the present invention.
3 is a diagram schematically showing the configuration of the second phase detector and the charge pump shown in FIG. 2.
4 is a diagram showing the configuration of an analog delay locked loop according to an embodiment of the present invention.
5 is a diagram showing the configuration of the timing skew detector shown in FIG. 4.
6 is a diagram showing the configuration of the delay adjuster shown in FIG. 4.
7 is a timing diagram showing an operation of a correction circuit and a delay locked loop according to an embodiment of the present invention.
8A is a diagram showing a configuration of a delay line according to an embodiment of the present invention.
8B is a timing diagram showing the operation of the delay line shown in FIG. 8A.
9A is a diagram showing a configuration of a delay line according to an embodiment of the present invention.
9B is a diagram illustrating an operation of the delay line shown in FIG. 9A.
10A, 10B, and 10C are diagrams showing a configuration of a delay line according to an embodiment of the present invention.
11 is a diagram illustrating a configuration of a semiconductor device according to an embodiment of the present invention.

1 is a diagram showing a configuration of a semiconductor device 100 according to an embodiment of the present invention. Referring to FIG. 1, the semiconductor device 100 may generate a plurality of internal clock signals by receiving a clock signal CLK. The clock signal CLK may be an external clock signal transmitted from an external device connected to the semiconductor device 100. In an embodiment, the clock signal CLK may be a periodic signal generated from a clock generator such as an oscillator. The semiconductor device 100 may generate the plurality of internal clock signals by performing a delay fixing operation on the clock signal CLK. The semiconductor device 100 may include a delay locked loop circuit including at least two delay locked loops having different characteristics. The delay locked loop circuit may perform a delay fixing operation on the clock signal CLK through at least one of the two delay locked loops. The two delay locked loops may include a digital delay locked loop and an analog delay locked loop.

The semiconductor device 100 may include a clock receiver 110 and a delay locked loop circuit 120. The clock receiver 110 may receive the clock signal CLK. The clock receiver 110 may receive the clock signal CLK and output a buffered clock signal CLKR. The clock signal CLK may be transmitted as a differential signal together with the complementary signal CLKB, or may be transmitted as a single-ended signal. When the clock signal CLK is transmitted as a differential signal, the clock receiver 110 may differentially amplify the clock signal CLK and a complementary signal CLKB to output the buffered clock signal CLKR. . When the clock signal CLK is transmitted as a single-ended signal, the clock receiver 110 differentially amplifies the clock signal CLK and the reference voltage VREF to generate the buffered clock signal CLKR. have. The reference voltage VREF may have a voltage level corresponding to the middle of the amplitude of the clock signal CLK.

The delay locked loop circuit 120 may receive a reference clock signal and perform a delay fixing operation on the reference clock signal. The buffered clock signal CLKR generated from the clock receiver 110 may be provided as the reference clock signal. The semiconductor device 100 may further include a divider circuit 130. The divider circuit 130 may receive the buffered clock signal CLKR, divide the frequency of the buffered clock signal CLKR, and provide the divided clock signal as the reference clock signal. When the semiconductor device 100 operates at a relatively low frequency, the delay lock loop circuit 120 may perform a delay fixing operation by receiving the buffered clock signal CLKR as the reference clock signal. When the semiconductor device 100 operates at a relatively high frequency, the delay lock loop 120 receives the clock signal divided by the divider circuit 130 as the reference clock signal to perform a delay fixing operation. I can. The divider circuit 130 divides the buffered clock signal CLKR to divide a first divided clock signal ICLK, a second divided clock signal QCLK, a third divided clock signal IBCLK, and a fourth divided clock signal. (QBCLK) can be created.

The first to fourth divided clock signals ICLK, QCLK, IBCLK, and QBCLK may have a lower frequency and/or a longer period than the buffered clock signal CLKR. The first divided clock signal ICLK may be a clock signal whose phase is synchronized with the buffered clock signal CLKR, and may have a phase preceding the second divided clock signal QCLK by 90 degrees. The second divided clock signal QCLK may have a phase ahead of the third divided clock signal IBCLK by 90 degrees. The third divided clock signal IBCLK may have a phase ahead of the fourth divided clock signal QBCLK by 90 degrees. The fourth divided clock signal QBCLK may have a phase ahead of the first divided clock signal ICLK by 90 degrees. The delay locked loop circuit 120 may receive the first divided clock signal ICLK as the reference clock signal and perform a delay fixing operation on the first divided clock signal ICLK. In one embodiment, the delay locked loop circuit 120 may receive the second divided clock signal QCLK as the reference clock signal and perform a delay fixing operation on the second divided clock signal QCLK. have.

The delay locked loop circuit 120 may include a first delay locked loop 121 and a second delay locked loop 122. The first delay locked loop 121 may be a digital delay locked loop, and the second delay locked loop 122 may be an analog delay locked loop. The first delay locked loop 121 may receive the reference clock signal and an internal reference clock signal. The first delay locked loop 121 may generate a delay locked clock signal CLKDLL by performing a delay fixing operation on the reference clock signal based on the reference clock signal and the internal reference clock signal. The second delay locked loop 122 may receive the delay locked clock signal CLKDLL and the internal reference clock signal. The second delay locked loop 122 receives the delay locked clock signal CLKDLL and the internal reference clock signal, and performs a delay fixing operation on the delay locked clock signal CLKDLL to obtain the internal reference clock signal Can be generated.

The first delay locked loop 121 may generate the delay locked clock signal CLKDLL by delaying the reference clock signal to compensate for a modeled delay time. The second delay locked loop 122 may adjust a phase of the delay locked clock signal CLKDLL and generate a plurality of internal clock signals having different phases from the delay locked clock signal CLKDLL. The plurality of internal clock signals may include a first internal clock signal ICLKD, a second internal clock signal QCLKD, a third internal clock signal IBCLKD, and a fourth internal clock signal QBCLKD. The first internal clock signal ICLKD may be provided as the internal reference clock signal, and may have a phase that is 90 degrees faster than the second internal clock signal QCLKD. The second internal clock signal QCLKD may have a phase that is 90 degrees faster than the third internal clock signal IBCLKD. The third internal clock signal IBCLKD may have a phase that is 90 degrees faster than the fourth internal clock signal QBCLKD. The fourth internal clock signal QBCLKD may have a phase that is 90 degrees faster than the first internal clock signal ICLKD. The first to fourth internal clock signals ICLK, QCLK, IBCLK, and QBCLK may be provided as internal circuits that operate in synchronization with a clock signal among various internal circuits included in the semiconductor device 100. Hereinafter, the internal reference clock signal and the internal clock signal may be used as names indicating the same clock signal.

In general, a digital delay locked loop can perform a fast delay fixing operation and can perform a delay fixing operation on a clock signal of a wide frequency band compared to an analog delay locked loop. However, there is a problem in that it is difficult to perform a delay fixing operation for a clock signal of a certain frequency or higher through a delay locked loop having one delay line. To solve the above problem, a dual delay locked loop having two delay lines was designed, but skew occurs in the phases of the plurality of internal clock signals generated from the delay locked loop according to the process variation between the two delay lines. easy to do. Accordingly, the semiconductor device 100 according to the embodiment of the present invention employs a delay locked loop circuit 120 including both a digital delay locked loop and an analog delay locked loop to perform a delay fixing operation for a clock signal having a high frequency. Enable, and allow a plurality of internal clock signals with precise phase difference to be generated.

2 is a diagram showing the configuration of a delay locked loop circuit 200 according to an embodiment of the present invention. The delay locked loop circuit 200 may be applied to the delay locked loop circuit 120 shown in FIG. 1. Referring to FIG. 2, the delay locked loop circuit 200 may include a first delay locked loop 210 and a second delay locked loop 220. The first delay locked loop 210 may be a digital delay locked loop, and the second delay locked loop 220 may be an analog delay locked loop. The first delay locked loop 210 receives a reference clock signal REFCLK and an internal clock signal ICLKD, and based on the reference clock signal REFCLK and the internal clock signal ICLKD, the reference clock signal ( REFCLK) may be performed to generate a delay locked clock signal CLKDLL. The second delay locked loop 220 receives the delay locked clock signal CLKDLL and performs a delay locking operation on the delay locked clock signal CLKDLL to perform the first to fourth internal clock signals ICLKD and QCLKD. , IBCLKD, QBCLKD) can be generated. One of the first to fourth internal clock signals ICLKD, QCLKD, IBCLKD, and QBCLKD may be provided as the internal reference clock signal. For example, the first internal clock signal ICLK may be used as the internal reference clock signal.

The first delay locked loop 210 may include a first delay line 211, a replica 212, a first phase detector 213 and a delay controller 214. The first delay line 211 may receive the reference clock signal REFCLK and a delay control signal DC. The first delay line 211 may generate the delayed fixed clock signal CLKDLL by delaying the reference clock signal REFCLK based on the delay control signal DC. The first delay line 211 may be a digitally controlled delay line. The delay amount of the first delay line 211 may be set based on the delay control signal DC. The first delay line 211 may generate the delayed fixed clock signal CLKDLL by delaying the reference clock signal REFCLK by a delay amount set by the delay control signal DC.

The replica 212 may receive the internal clock signal ICLKD as the internal reference clock signal. The replica 212 may generate a first feedback clock signal FBCLK1 by delaying the internal clock signal ICLKD. The replica 212 may be designed by modeling a transmission path through which the clock signal CLK is transmitted inside the semiconductor device 100 illustrated in FIG. 1. Accordingly, the replica 212 may have a delay amount corresponding to a delay time generated by a path through which the clock signal CLK is transmitted. The replica 212 may generate the first feedback clock signal FBCLK1 by delaying the internal reference clock signal by a modeled delay time.

The first phase detector 213 may receive the reference clock signal REFCLK and the first feedback clock signal FBCLK1. The first phase detector 213 may generate a first phase detection signal PD1 by comparing a phase of the reference clock signal REFCLK and the first feedback clock signal FBCLK1. The first phase detector 213 is the logic of the first phase detection signal PD1 according to whether the phase of the reference clock signal REFCLK is ahead or behind the phase of the first feedback clock signal FBCLK1. You can change the level. For example, when the phase of the reference clock signal REFCLK is ahead of the phase of the first feedback clock signal FBCLK1, the first phase detector 213 is ) Can be created. The first phase detector 213 generates the first phase detection signal PD1 having a logic low level when the phase of the reference clock signal REFCLK is later than the phase of the first feedback clock signal FBCLK1. I can.

The delay controller 214 may receive the first phase detection signal PD1 and generate the delay control signal DC. The delay control signal DC may be a digital code signal including a plurality of bits. The delay controller 214 may change the code value of the delay control signal DC based on the first phase detection signal PD1. The delay amount of the first delay line 211 may be increased or decreased according to the value of the delay control signal DC. The first delay lock loop 210 performs a delay lock operation by changing a value of the delay control signal DC until the phase of the reference clock signal REFCLK and the first feedback clock signal FBCLK1 match. You can do it. When the phase of the reference clock signal REFCLK and the first feedback clock signal FBCLK1 are identical to each other, the first delay lock loop 210 may fix and lock a value of the delay control signal DC. .

The second delay lock loop 220 may include a second delay line 221, a second phase detector 222, and a charge pump 223. The second delay line 221 may receive the delay locked clock signal CLKDLL output from the first delay locked loop 210. The second delay line 221 may generate a plurality of delayed clock signals by receiving the delay control voltage VC and delaying the delayed fixed clock signal CLKDLL based on the delay control voltage VC. . The second delay line 221 may be a voltage controller delay line. The delay amount of the second delay line 221 may be set based on the delay control voltage VC which is an analog signal. The second delay line 221 may generate the plurality of delayed clock signals by delaying the delayed fixed clock signal CLKDLL by a delay amount set by the delay control voltage VC. The second delay line 221 may output four of the plurality of delayed clock signals as the first to fourth internal clock signals ICLKD, QCLKD, IBCLKD, and QBCLKD, among the plurality of delayed clock signals. The other may be output as the second feedback clock signal FBCLK2.

The second delay line 221 may include a plurality of delay cells. In FIG. 2, it is illustrated that the second delay line includes nine delay cells (DC1, DC2, DC3, DC4, DC5, DC6, DC7, DC8, DC9), but the second delay line is not intended to be limited thereto. The number of delay cells included in the delay line 221 may be less than nine or more than nine. Referring to FIG. 1 together, one delay cell may be set to have a delay time corresponding to a quarter cycle of the clock signal CLK. When one of the first divided clock signal ICLK and the second divided clock signal QCLK divided by the divider circuit 130 is provided as the reference clock signal REFCLK, the one delay cell is the reference It may be set to have a delay time corresponding to 1/8 cycle of the clock signal REFCLK. The second delay line 221 may output a delayed clock signal output from the first delay cell DC1 as the first internal clock signal ICLKD. The first internal clock signal ICLKD may be provided as the internal reference clock signal. The second delay line 221 may output a delayed clock signal output from the third delay cell DC3 as the second internal clock signal QCLKD. The second delay line 221 may output a delayed clock signal output from the fifth delay cell DC5 as the third internal clock signal IBCLKD. The second delay line 221 may output a delayed clock signal output from the seventh delay cell DC7 as the fourth internal clock signal QBCLKD. The second delay line 221 may provide a delayed clock signal output from the last delay cell DC9 as the second feedback clock signal FBCLK2.

The second phase detector 222 may receive the internal reference clock signal and the second feedback clock signal FBCLK2. The second phase detector 222 generates a second phase detection signal PD2 based on the phases of the first internal clock signal ICLKD and the second feedback clock signal FBCLK2 provided as the internal reference clock signal. can do. The second phase detection signal PD2 may include, for example, an up signal UP and a down signal DN. The second phase detector 222 enables the up signal UP based on the phase of the first internal clock signal ICLKD, and the down signal UP based on the phase of the second feedback clock signal FBCLK2. The signal DN can be enabled. The second phase detector 222 may enable the up signal UP when the phase of the first internal clock signal ICLKD transitions from a logic low level to a logic high level. The second phase detector 222 may enable the down signal DN when the phase of the second feedback clock signal FBCLK2 transitions from a logic low level to a logic high level. The second phase detector 222 may reset the up signal UP and the down signal DN when a predetermined time elapses. The second phase detector 222 determines the up signal UP and the down signal when the predetermined time elapses from a time when a signal that is lately enabled among the up signal UP and the down signal DN is enabled. All (DN) can be disabled. The predetermined time may be shorter than a time corresponding to a 1/2 cycle of the reference clock signal REFCLK and/or the second feedback clock signal FBCLK2.

The charge pump 223 may receive the second phase detection signal PD2 and generate the delay control voltage VC based on the second phase detection signal PD2. The charge pump 223 may increase the voltage level of the delay control voltage VC based on the up signal UP, and the voltage of the delay control voltage VC based on the down signal DN You can lower the level. When the voltage level of the delay control voltage VC increases, the delay times of the delay cells DC1 to DC9 constituting the second delay line 222 may decrease. When the voltage level of the delay control voltage VC falls, the delay times of the delay cells DC1 to DC9 constituting the second delay line 222 may increase. The second delay lock loop 220 performs a delay lock operation by changing the value of the delay control voltage VC until the phase of the internal reference clock signal and the second feedback clock signal FBCLK2 coincide. I can. When the phase of the internal reference clock signal and the second feedback clock signal FBCLK2 coincide with each other, the second delay lock loop 220 may fix and lock the voltage level of the delay control voltage VC.

3 is a diagram schematically showing the configuration of the second phase detector 222 and the charge pump 223 shown in FIG. 2. The second phase detector 222 may include a first plurality of drivers 311 and a second plurality of drivers 312. The first plurality of drivers 311 may receive the first internal clock signal ICLKD and drive the first internal clock signal ICLKD to generate the up signal UP. The second plurality of drivers 312 may receive the second feedback clock signal FBCLK2 and drive the second feedback clock signal FBCLK2 to generate the down signal DN.

The charge pump 223 may include a pull-up current source 321, a pull-down current source 322, a capacitor 323, a first switch 324 and a second switch 325. The pull-up current source 321 is connected between the terminal to which the high voltage VH is supplied and the output node ON, and may generate a pull-up current IUP. The delay control voltage VC may be generated from the output node ON. The pull-up current source 321 may be implemented with at least one P-channel MOS transistor that receives a bias voltage or a current control signal. The pull-down current source 322 is connected between the output node ON and a terminal to which the low voltage VL is supplied, and may generate a pull-down current IDN. The low voltage VL may have a voltage level lower than the high voltage VH. The pull-down current source 322 may be implemented with at least one N-channel MOS transistor that receives a bias voltage or a current control signal. One end of the capacitor 323 may be connected to the output node ON, and the other end may be connected to a terminal to which the low voltage VL is supplied. The voltage levels of the output node ON and the delay control voltage VC may be changed according to the amount of charge charged in the capacitor 323.

The first switch 324 may receive the up signal UP. The first switch 324 may connect the pull-up current source 321 to the output node ON based on the up signal UP. When the first switch 324 is turned on based on the up signal UP, the pull-up current IUP is supplied to the output node ON, and the capacitor 323 may be charged. Accordingly, voltage levels of the output node ON and the delay control voltage VC may increase. The second switch 325 may receive the down signal DN. The second switch 325 may connect the pull-down current source 322 to the output node ON based on the down signal DN. When the second switch 325 is turned on based on the down signal DN, the pull-down current IDN flows from the output node ON to a terminal to which the low voltage VL is supplied, and the capacitor ( 323) can be discharged. Accordingly, the voltage levels of the output node ON and the delay control voltage VC may decrease.

In the second phase detector 222, a delay mismatch occurs between the first plurality of drivers 311 and the second plurality of drivers 312 according to local process variation. I can. Accordingly, the down signal DN is turned on according to a time when the up signal UP is enabled according to a rising edge of the first internal clock signal ICLKD and a rising edge of the second feedback clock signal FBCLK2. An error may occur between the enabled times. In addition, the pull-up current source IUP of the charge pump 321 is composed of a P-channel MOS transistor, whereas the pull-down current source 322 is composed of an N-channel MOS transistor. An error may occur between the size of IUP) and the size of the pull-down current IDN. Accordingly, even when the second delay locked loop 220 shown in FIG. 2 completes the delay fixing operation, a phase error may occur between the first internal clock signal ICLKD and the second feedback clock signal FBCLK2. I have no choice but to. The phase error can be expressed by the following equation.

Δt2 = Δt _MIS + t _RESET * (1-IUP/IDN)

Here, Δt2 may be a phase error between the first internal clock signal ICLKD and the second feedback clock signal FBCLK2 when the second delay locked loop is locked, and Δt _MIS is the second phase detector ( 222) may be a delay mismatch, and t _RESET may correspond to the predetermined time for resetting the up signal UP and the down signal DN. In general, in order to improve Δt2, a method of adjusting the magnitudes of the pull-up current and the pull-down current supplied to generate the delay control voltage from a charge pump is used. However, since it is difficult to implement high resolution and a mismatch may occur again between the adjusted pull-up current and the pull-down current, the first internal clock signal ICLKD And it is difficult to fundamentally solve a phase error between the second feedback clock signal FBCLK2.

4 is a diagram showing the configuration of an analog delay locked loop 400 according to an embodiment of the present invention. The analog delay locked loop 400 may be applied as the second delay locked loop 122 illustrated in FIG. 1, and may replace the second delay locked loop 220 illustrated in FIG. 2. The analog delay locked loop 400 may include a delay line 410, a correction circuit 420, a phase detector 430, and a charge pump 440. The delay line 410 may receive a reference clock signal REFCLK and a delay control voltage VC. When the analog delay locked loop 400 replaces the second delay locked loop 220 illustrated in FIG. 2, the reference clock signal REFCLK may correspond to the delay locked clock signal CLKDLL. The delay line 410 may generate a plurality of delayed clock signals by delaying the reference clock signal REFNCLK based on the delay control voltage VC. The delay line 410 may output one of the plurality of delayed clock signals as an internal reference clock signal, and may output the other one of the plurality of delayed clock signals as the feedback clock signal FBCLK. The delay line 410 includes a first internal clock signal (ICLKD), a second internal clock signal (QCLKD), a third internal clock signal (IBCLKD), and a fourth internal clock signal ( QBCLKD) may be generated, and the first internal clock signal ICLKD may be provided as the internal reference clock signal. The delay line 410 may include a plurality of delay cells DC1 to DC9, and the plurality of delayed clock signals may be respectively output from the plurality of delay cells. Components of the delay line 410 may be the same as those of the second delay line 221 illustrated in FIG. 2, and redundant descriptions of the same components will be omitted.

The correction circuit 420 may receive the first internal clock signal ICLKD and the feedback clock signal FBCLK. The correction circuit 420 generates a delayed reference clock signal REFD from the reference clock signal based on the phases of the first internal clock signal ICLKD and the feedback clock signal FBCLK, and generates the feedback clock signal FBCLK. A delayed feedback clock signal FEBD may be generated from ). The correction circuit 420 determines the delay amount of the first internal clock signal ICLKD and the feedback clock signal FBCLK according to the relative phases of the first internal clock signal ICLKD and the feedback clock signal FBCLK. You can change the amount of delay. The correction circuit 420 may delay a clock signal having a later phase among the first internal clock signal ICLKD and the feedback clock signal FBCLK for a longer time. For example, when the phase of the first internal clock signal ICLKD is ahead of the phase of the feedback clock signal FBCLK, the correction circuit 420 adjusts the first internal clock signal ICLKD by a first time. The delayed reference clock signal REFD is generated by delaying and the feedback clock signal FBCLK is delayed by a second time to generate the delayed feedback clock signal FEBD. The second time may be longer than the first time. When the phase of the first internal clock signal ICLKD is later than the phase of the feedback clock signal FBCLK, the correction circuit 420 delays the first internal clock signal ICLKD by the second time. The delayed feedback clock signal FEBD may be generated by generating a delayed reference clock signal REFD and delaying the feedback clock signal FBCLK by the first time.

The phase detector 430 may receive the delayed reference clock signal REFD and the delayed feedback clock signal FEBD. The phase detector 430 may generate a phase detection signal PD by detecting the phases of the delayed reference clock signal REFD and the delayed feedback clock signal FEBD. The phase detection signal PD may include an up signal UP and a down signal DN. The charge pump 440 may generate the delay control voltage VC based on the phase detection signal PD. The phase detector 430 and the charge pump 440 may include the same components and perform the same function as the second phase detector 222 and the charge pump 223 shown in FIGS. 2 and 3. Redundant descriptions of the same components will be omitted.

The correction circuit 420 may include a timing skew detector 421, a calibration signal generator 422 and a delay adjuster 423. The timing skew detector 421 may detect a phase difference between the phase of the first internal clock signal ICLKD and the feedback clock signal FBCLK. The timing skew detector 421 detects the phase of the first internal clock signal ICLKD and the phase of the feedback clock signal FBCLK to provide a first phase control signal FEBINC and a second phase control signal REFINC. Can be generated. The timing skew detector 421 detects the phases of the first internal clock signal ICLKD and the feedback clock signal FBCLK to generate a first skew detection signal and a second skew detection signal, and The first phase control signal FEBINC and the second phase control signal REFINC may be generated according to whether the logic level of the 2 skew detection signal is maintained for a time corresponding to at least twice the unit time. A time corresponding to twice the unit cycle may be a loop bandwidth of the correction circuit 420 and may mean a period in which the correction circuit 420 is updated. The loop bandwidth of the correction circuit 420 may be smaller than the loop bandwidth of the delay locked loop 400, and a period in which the correction circuit 420 is updated may be longer than a period in which the delay locked loop 400 is updated. have. In an embodiment, the loop bandwidth of the correction circuit 420 may be set to three times or more of the unit cycle. The unit cycle may be determined based on the plurality of delayed clock signals generated by the delay line 410. The unit cycle will be described later.

The calibration signal generator 422 may generate a calibration signal CAL<1:2N> by receiving the first phase control signal FEBINC and the second phase control signal REFINC. The calibration signal CAL<1:2N> may be a digital code signal including a plurality of bits. The calibration signal generator 422 may change a partial value of the calibration signal CAL<1:2N> based on the first phase control signal FEBINC. The calibration signal generator 422 may change the remaining value of the calibration signal CAL<1:2N> based on the second phase control signal REREFINC. For example, the calibration signal CAL<1:2N> may include 2N bits. Here, N may be an integer of 2 or more. The calibration signal generator 422 may change a value of the first to Nth bits (CAL<1:N>) of the calibration signal based on the first phase control signal FEBINC, and the second phase A value of the N+1 to 2N bits CAL<N+1:2N> of the calibration signal may be changed based on the control signal REFINC. The calibration signal generator 422 decodes the first and second phase adjustment signals (FEBINC, REFINC) and values of the first to 2N bits (CAL<1:2N>) of the calibration signal according to the decoded result. Components such as a decoding circuit and a shift register circuit may be included to change the value.

The delay adjuster 423 may receive the calibration signal CAL<1:2N>. The delay adjuster 423 delays the first internal clock signal ICLKD based on a part of the calibration signal CAL<1:2N> to generate the delay reference clock signal REFD, and the calibration signal The delayed feedback clock signal FEBD may be generated by delaying the feedback clock signal FBCLK based on the remainder of (CAL<1:2N). The delay adjuster 423 delays the first internal clock signal ICLKD by a delay amount set based on the first to Nth bits (CAL<1:N>) of the calibration signal to delay the delay reference clock signal ( REFD) can be created. The delay adjuster 423 delays the feedback clock signal FBCLK by a set delay amount based on the N+1 to 2N bits (CAL<N+1:2N>) of the calibration signal to delay the delay feedback clock. It can generate a signal (FEBD).

5 is a view showing the configuration of the timing skew detector 421 shown in FIG. Referring to FIG. 5, the timing skew detector 421 may include a skew detector 510, a filter 520, and a phase control signal generator 530. The skew detector 510 may generate a first skew detection signal SKW1 and a second skew detection signal SKW2 by detecting the phases of the first internal clock signal ICLKD and the feedback clock signal FBCLK. have. The first skew detection signal SKW1 may include information on whether a phase of the first internal clock signal ICLKD is earlier or later than a phase of the feedback clock signal FBCLK. The second skew detection signal SKW2 may include information on whether a phase of the feedback clock signal FBCLK is earlier or later than a phase of the first internal clock signal ICLKD.

The filter 520 may receive the first skew detection signal SKW1 and the second skew detection signal SKW2. The filter 520 may generate a first phase information signal SLOW and a second phase information signal FAST based on the first skew detection signal SKW1 and the second skew detection signal SKW2. . The first phase information signal SLOW may be enabled when the phase of the feedback clock signal FBCLK is later than the phase of the first internal clock signal ICLKD, and the second phase information signal FAST is When the phase of the feedback clock signal FBCLK is ahead of the phase of the first internal clock signal ICLKD, it may be enabled. The filter 520 may define a loop bandwidth of the correction circuit 420 based on one of the plurality of delayed clock signals. The filter 520 is based on whether the logic levels of the first skew detection signal SKW1 and the second skew detection signal SKW2 are maintained for a time corresponding to the loop bandwidth, SLOW) and the second phase information signal FAST.

The phase control signal generator 530 may receive the first phase information signal SLOW and the second phase information signal FAST. The phase control signal generator 530 generates the first phase control signal FEBINC based on the first phase information signal SLOW, and the second phase control signal FAST based on the second phase information signal FAST. It is possible to generate a control signal REFINC.

The skew detector 510 may include a first flip-flop 511 and a second flip-flop 512. The first and second flip-flops 511 and 512 may be D flip-flops. The first flip-flop 511 receives the first internal clock signal ICLKD through an input terminal D, receives the feedback clock signal FBCLK through a clock terminal, and is controlled through an output terminal Q. 1 A skew detection signal (SKW1) can be output. The second flip-flop 512 receives the feedback clock signal FBCLK through an input terminal D, receives the first internal clock signal ICLKD through a clock terminal, and receives the first internal clock signal ICLKD through an output terminal Q. 2 A skew detection signal (SKW2) can be output. The skew detector 510 is in a dual mode to reduce malfunctions that may occur due to fluctuations in setup time and hold time of the first and second flip-flops 511 and 512. A skew between the phases of the first internal clock signal ICLKD and the feedback clock signal FBCLK may be detected.

The filter 520 includes a first flip-flop 521, a second flip-flop 522, a third flip-flop 523, a fourth flip-flop 524, a first gating circuit 525, and a second gating circuit. (526) may be included. The first to fourth flip-flops 521, 522, 523, and 524 may be D flip-flops. The first flip-flop 521 receives the first skew detection signal SKW1 through an input terminal D, receives a first clock signal EVCLK through a clock terminal, and is controlled through an output terminal Q. 1 Even signal EV1 can be output. The second flip-flop 522 receives the second skew detection signal SKW2 through an input terminal D, receives the first clock signal EVCLK through a clock terminal, and receives the first clock signal EVCLK through an output terminal Q. The second even signal EV2 may be output. The third flip-flop 523 receives the first skew detection signal SKW1 through an input terminal D, a second clock signal ODCLK through a clock terminal, and a second clock signal ODCLK through an output terminal Q. 1 Odd signal OD1 can be output. The second clock signal ODCLK may have a phase later than that of the first clock signal EVCLK. The fourth flip-flop 524 receives the second skew detection signal SKW2 through an input terminal D, receives the second clock signal ODCLK through a clock terminal, and receives the second clock signal ODCLK through an output terminal Q. A second odd signal OD2 may be output.

The first gating circuit 525 receives the first even signal EV1, the first odd signal OD1, the second even signal EV2, and the second odd signal OD2, and the received The first phase information signal SLOW may be generated by performing an AND operation on signals. The first gating circuit 525 may include an AND gate. The first gating circuit receives the first even signal EV1, the first odd signal OD1, an inverted signal of the second even signal EV2, and an inverted signal of the second odd signal OD2, and , The first phase information signal SLOW may be output. The second gating circuit 526 receives the first even signal EV1, the first odd signal OD1, the second even signal EV2, and the second odd signal OD2, and the received The second phase information signal FAST may be generated by performing an AND operation on signals. The second gating circuit 526 may include an AND gate. The second gating circuit 526 includes an inverted signal of the first even signal EV1, an inverted signal of the first odd signal OD1, the second even signal EV2, and the second odd signal OD2. And outputs the second phase information signal FAST. The filter 520 may further include an additional flip-flop to reduce the loop bandwidth of the correction circuit 420 and increase an update period of the correction circuit 420. The additional flip-flop may receive a clock signal that is later in phase than the second clock signal ODCLK, and the gating circuits may be modified to further receive a signal output from the additional flip-flop.

In the first gating circuit 525, the first even signal EV1 and the first odd signal OD1 are at a logic high level, and the second even signal EV2 and the second odd signal OD2 are At a logic low level, the first phase information signal SLOW may be output at a logic high level. In the second gating circuit 526, the first even signal EV1 and the first odd signal OD1 are at a logic low level, and the second even signal EV2 and the second odd signal OD2 are At a logic high level, the second phase information signal FAST may be output at a logic high level. The first even signal EV1 and the second even signal EV2 are generated in synchronization with the first clock signal EVCLK, and the first odd signal OD1 and the second odd signal OD2 are It may be generated in synchronization with the 2 clock signal ODCLK. Accordingly, the filter 520 has the logic level of the first and second skew detection signals SKW1 and SKW2 until both the transitions of the first clock signal EVCLK and the second clock signal ODCLK occur. Only when maintained, the first phase information signal SLOW and the second phase information signal FAST may be enabled at a logic high level. In general, since the delay locked loop can generate bang-bang jitter, when the phase information signal is directly generated from the first and second skew detection signals (SKW1, SKW2), an incorrect correction operation is performed. It could be. In the embodiment of the present invention, the correct correction operation is performed by allowing the value of the calibration signal to be changed according to the phase information signal only when the logic levels of the first and second skew detection signals SKW1 and SKW2 are maintained for the predetermined time. So that it can be done.

The phase control signal generator 530 may include a first gating circuit 531, a second gating circuit 532, and a third gating circuit 533. The first gating circuit 531 may receive the first phase information signal SLOW and the second phase information signal FAST to generate a correction enable signal CALON. The first gating circuit 531 may generate the correction enable signal CALON by performing an OR operation on the first and second phase information signals SLOW and FAST. The first gating circuit 531 may include an OR gate. When at least one of the first and second phase information signals SLOW and FAST is enabled at a logic high level, the first gating circuit 531 enables the correction enable signal CALON to be at a logic high level. You can enable it. The second gating circuit 532 may receive the first phase information signal SLOW, the correction enable signal CALON, and a third clock signal ODCLKB. The third clock signal ODCLKB may have a phase that is later than that of the second clock signal ODCLK. The second gating circuit 532 performs an AND operation on the first phase information signal SLOW, the correction enable signal CALON, and the third clock signal ODCLKB, and the first phase control signal ( FEBINC) can be created. The second gating circuit 532 may include an AND gate. The second gating circuit is the first phase control signal when both the first phase information signal SLOW and the correction enable signal CALON are at a logic high level in a high level period of the third clock signal ODCLKB. You can enable (FEBINC) to a logic high level. The third gating circuit 533 may receive the second phase information signal FAST, the correction enable signal CALON, and the third clock signal ODCLKB. The third gating circuit 533 performs an AND operation on the second phase information signal FAST, the correction enable signal CALON, and the third clock signal ODCLKB, and the second phase control signal ( REFINC) can be created. The third gating circuit 533 may include an AND gate. When both the second phase information signal FAST and the correction enable signal CALON are at a logic high level in a high level period of the third clock signal ODCLKB, the third gating circuit 533 The phase adjustment signal REFINC may be enabled to a logic high level.

The timing skew detector 421 may further include a control clock generator 540. The control clock generator 540 may receive one of a plurality of delayed clock signals generated through the voltage controlled delay line 410 illustrated in FIG. 4. For example, the control clock generator 540 may receive a delay clock signal CK4 output from the fourth delay cell DC4 of the voltage control delay line 410. The control clock generator 540 may generate the first clock signal EVCLK, the second clock signal ODCLK, and the third clock signal ODCLKB from the delayed clock signal CK4. The control clock signal generator 540 may include a first divider 541, a first inverter 542, a second divider 543, a third divider 544, and a second inverter 545. have. The first divider 541 may divide the delayed clock signal CK4. The first inverter 542 may invert the output of the first divider 541. The second divider 543 may generate the first clock signal EVCLK by dividing the output of the first inverter 542. The third divider 544 may divide the output of the first divider 541 to generate the second clock signal ODCLK. The second inverter 545 may generate the third clock signal ODCLKB by inverting the second clock signal ODCLK.

6 is a diagram showing the configuration of the delay adjuster 423 shown in FIG. 4. Referring to FIG. 6, the delay adjuster 423 may include a first variable delay 610 and a second variable delay 620. The first variable delay 610 receives the first internal clock signal ICLKD and the first to Nth bits CAL<1:N> of the calibration signal to receive the delay reference clock signal REFD. Can be generated. The first variable delay unit 610 may set a delay time based on the first to Nth bits (CAL<1:N>) of the calibration signal, and the first internal clock signal ICLKD is set. The delayed reference clock signal REFD may be generated by delaying by a delay time. The second variable delayer 620 receives the feedback clock signal FBCLK and the N+1 to 2N-th bits (CAL<N+1:2N>) of the calibration signal to receive the delayed feedback clock signal FEBD. ) Can be created. The second variable delay unit 620 may set a delay time based on the N+1 to 2N bits (CAL<N+1:2N>) of the calibration signal, and the feedback clock signal FBCLK The delayed feedback clock signal FEBD may be generated by delaying by a set delay time.

7 is a timing diagram showing the operation of the correction circuit 420 and the delay locked loop 400 according to an embodiment of the present invention. The operation of the correction circuit 420 and the delay locked loop 400 will be described with reference to FIGS. 3 to 6 as follows. In S1, the skew detector 510 of the timing skew detector 421 detects the phases of the first internal clock signal ICLKD and the feedback clock signal FBCLK to detect the first skew detection signal SKW1 and the A second skew detection signal SKW2 may be generated. As shown in FIG. 7, a phase error Δt2 is generated by the phase detector 430 and the charge pump 440 so that the phase of the first internal clock signal ICLKD is the feedback clock signal FBCLK. When it is later than the phase of, the skew detector 510 may generate the first skew detection signal SKW1 having a logic low level and generate the second skew detection signal SKW2 having a logic high level. . The calibration signal CAL<1:2N> may maintain a default value before being updated, and the delay adjuster 423 provides the first internal clock signal ICLKD and the feedback clock signal FBCLK. The delayed reference clock signal REFD and the delayed feedback clock signal FEBD may be generated by delaying by the same amount of time. The phase detector 430 may enable the down signal DN when the delayed feedback clock signal FEBD transitions from a logic low level to a logic high level, and the first internal clock signal ICLKD is When transitioning from the logic low level to the logic high level, the up signal UP may be enabled. The up signal UP and the down signal DN may maintain an enabled state until reset, and a pulse width of the down signal DN may be wider than a pulse width of the up signal UP. Ideally, the charge pump 440 should generate a delay control voltage VC having a lower level based on the up signal UP and the down signal DN. However, when a mismatch occurs between the pull-up current IUP and the pull-down current IDN of the charge pump 440 and the pull-up current IUP is greater than the pull-down current IDN, the delay control voltage VC The voltage level of) is not lowered and a malfunction in which the previous voltage level is maintained may occur. Accordingly, the phases of the first internal clock signal ICLKD and the feedback clock signal FBCLK cannot be matched only by the operation of the phase detector 430 and the charge pump 440. The filter 520 of the correction circuit 420 maintains the first phase information signal SLOW in a disabled state when the logic levels of the first and second skew detection signals SKW1 and SKW2 are maintained. And enable the second phase information signal FAST to a logic high level.

In S2, the phase control signal generator 530 enables the second phase control signal REFINC according to the second phase information signal FAST, and the calibration signal generator 422 enables the second phase control signal FAST. A value of n+1 to 2n-th bits (CAL<N+1:2N>) may be increased. The delay adjuster 423 delays the feedback clock signal FBCLK for a relatively long time to generate the delayed feedback clock signal FEBD, and delays the first internal clock signal ICLKD for a relatively short time. Thus, the delayed reference clock signal REFD may be generated. Accordingly, a phase difference between the delayed reference clock signal REFD and the delayed feedback clock signal FEBD may be greater than a phase difference between the first internal clock signal ICLKD and the feedback clock signal FBCLK. . The delayed reference clock signal REFD may be delayed more by a correction phase Δt3 set by a correction operation than the delayed feedback clock signal FEBD. The phase detector 430 enables the down signal DN when the delay feedback clock signal FEBD transitions from a logic low level to a logic high level, and the delay reference clock signal REFD is at a logic low level. When transitioning from to the logic high level, the up signal UP may be enabled. The up signal UP and the down signal DN may maintain an enabled state until reset, and the up signal UP has a pulse width equal to the pulse width of the up signal UP generated in S1. On the other hand, the down signal DN may have a pulse width longer than that of the down signal DN generated in S1. Since the charge pump 440 can pull down the delay control voltage VC for a longer time by the down signal DN, even if the pull-up current IUP is greater than the pull-down current IDN, the delay The voltage level of the control voltage VC may be lowered.

In S3, when the voltage level of the delay control voltage VC falls, a phase of the first internal clock signal ICLKD generated from the delay line 410 and the feedback clock signal FBCLK may be matched. . Since the phases of the first internal clock signal ICLKD and the feedback clock signal FBCLK are identical, the correction circuit 420 ends the correction operation, and the value of the calibration signal CAL<1:2N> Can be maintained. The delay adjuster 423 may generate the delay reference clock signal REFD by delaying the first internal clock signal ICLKD by a delay time set by a correction operation compared to the feedback clock signal FBCLK. . Accordingly, the delayed reference clock signal REFD may have a phase that is later than the delayed feedback clock signal FEBD by a correction phase Δt3 set by a correction operation. The phase difference between the delayed reference clock signal REFD and the delayed feedback clock signal FEBD is a local process variation of the phase detector 430 and a pull-up current IUP and a pull-down current IDN of the charge pump 440 It is possible to compensate for the phase error Δt2 due to a mismatch therebetween, and the delay control voltage VC generated by the charge pump 440 may maintain a constant level. Accordingly, the delay locked loop 400 may generate the first internal clock signal ICLKD and the feedback clock signal FBCLK whose phases are matched by the correction circuit 420.

FIG. 8A is a diagram showing a configuration of a delay line 800 according to an embodiment of the present invention, and FIG. 8B is a timing diagram showing an operation of the delay line 800 shown in FIG. 8A. The delay line 800 may be applied as a part of the second delay line 221 and the delay line 410 shown in FIGS. 2 and 4, respectively. Referring to FIG. 8A, the delay line 800 may include a first delay cell 810 and a second delay cell 820. The first delay cell 810 may generate a first output signal OUT1 by inverting the input signal IN. The first delay cell 810 may invert the first output signal OUT1 to output a first delayed clock signal DCLK1. The second delay cell 820 may generate a second output signal OUT2 by inverting the first output signal OUT1. The second delay cell 820 may invert the second output signal OUT2 to output the second delayed clock signal DCLK2. A pull-down driving force by which the first delay cell 810 pulls down the first output signal OUT1 according to the input signal IN may be changed based on the delay control voltage VC. When the pull-down driving force of the first delay cell 810 is changed, the amount of delay of the first delay cell 810 may be changed. A pull-down driving force by which the second delay cell 820 pulls down the second output signal OUT2 according to the first output signal OUT1 may be changed based on the delay control voltage VC. When the pull-down driving force of the second delay cell 820 is changed, the amount of delay of the second delay cell 820 may be changed.

The first delay cell 810 may include a first inverter 811 and a first current source 812. The first inverter 811 may receive the input signal IN and generate the first output signal OUT1 by inverting the input signal IN. The first inverter 811 may be connected between a terminal to which a high voltage VH is supplied and a terminal to which a low voltage VL is supplied to invert the input signal IN. The high voltage VH may have a voltage level higher than the low voltage VL. The first current source 812 may be connected between the first inverter 811 and a terminal to which the low voltage VL is supplied. The first current source 812 may receive the delay control voltage VC. The first current source 812 may change a delay amount of the first delay cell 810 by changing a pull-down driving force of the first inverter 811 based on the delay control voltage VC. The first delay cell 810 may further include a second inverter 813. The second inverter 813 may invert the first output signal OUT1 to output the first delayed clock signal DCLK1.

The second delay cell 820 may include a third inverter 821 and a second current source 822. The third inverter 821 may receive the first output signal OUT1 and generate the second output signal OUT2 by inverting the first output signal OUT1. The third inverter 821 may be connected between a terminal to which the high voltage VH is supplied and a terminal to which the low voltage VL is supplied to invert the first output signal OUT1. The second current source 822 may be connected between the third inverter 821 and a terminal to which the low voltage VL is supplied. The second current source 822 may receive the delay control voltage VC. The second current source 822 may change the amount of delay of the second delay cell 820 by changing a pull-down driving force of the third inverter 821 based on the delay control voltage VC. The second delay cell 820 may further include a fourth inverter 823. The fourth inverter 823 may invert the second output signal OUT2 to output the second delayed clock signal DCLK2.

The first inverter 811 may include a first transistor M1 and a second transistor M2. The first transistor M1 may be a P-channel MOS transistor, and the second transistor M2 may be an N-channel MOS transistor. The first current source 812 may include a third transistor M3. The third transistor M3 may be an N-channel MOS transistor. A gate of the first transistor M1 receives the input signal IN, a source of the first transistor M1 is connected to a terminal to which the high voltage VH is supplied, and the first transistor M1 The drain of may be connected to the first output node ON1. The first output signal OUT1 may be output through the first output node ON1. A gate of the second transistor M2 may receive the input signal IN, and a drain of the second transistor M2 may be connected to the first output node ON1. A gate of the third transistor M3 receives the delay control voltage VC, a drain of the third transistor M3 is connected to a source of the second transistor M2, and the third transistor M3 The source of) may be connected to a terminal to which the low voltage VL is applied. The third transistor M3 may change an amount of current flowing from the source of the second transistor M2 to a terminal to which the low voltage VL is supplied based on the delay control voltage VC.

The third inverter 821 may include a fourth transistor M4 and a fifth transistor M5. The fourth transistor M4 may be a P-channel MOS transistor, and the fifth transistor M5 may be an N-channel MOS transistor. The second current source 822 may include a sixth transistor M6. The sixth transistor M6 may be an N-channel MOS transistor. A gate of the fourth transistor M4 receives the first output signal OUT1, a source of the fourth transistor M4 is connected to a terminal to which the high voltage VH is supplied, and the fourth transistor ( The drain of M4) may be connected to the second output node ON2. The second output signal OUT2 may be output through the second output node ON2. A gate of the fifth transistor M5 may receive the first output signal OUT1, and a drain of the fifth transistor M5 may be connected to the second output node ON2. A gate of the sixth transistor M6 receives the delay control voltage VC, a drain of the sixth transistor M6 is connected to a source of the fifth transistor M5, and the sixth transistor M6 The source of) may be connected to a terminal to which the low voltage VL is applied. The sixth transistor M6 may change an amount of current flowing from the source of the fifth transistor M5 to a terminal to which the low voltage VL is supplied based on the delay control voltage VC.

Since the delay amount of the delay cells 810 and 820 of the delay line 800 may be changed based on the delay control voltage VC, which is an analog signal, the input signal IN input to the delay line 800 Even if the frequency is increased, there is an advantage of reducing delay variation and reducing phase skew. However, the first output signal OUT1 and the second output signal OUT2 are as shown in FIG. , There may be a problem of not fully swinging to the voltage level of the low voltage VL. If the first output signal OUT1 and the second output signal OUT2 do not swing fully, the waveform of the final output signal may be more distorted as the number of delay cells increases, and accurate output signals may not be generated during high-speed operation May not be possible.

9A is a diagram showing a configuration of a delay line 900 according to an embodiment of the present invention. 9B is a diagram showing the operation of the delay line 900 shown in FIG. 9A. The delay line 900 may be applied as a part of the second delay line 221 and the delay line 410 shown in FIGS. 2 and 4, respectively. Referring to FIG. 9A, the delay line 900 may include a first delay cell 910 and a second delay cell 920. The first delay cell 910 may generate a first output signal OUT1 by inverting the input signal IN. The first delay cell 910 may invert the first output signal OUT1 to output a first delayed clock signal DCLK1. The second delay cell 920 may generate a second output signal OUT2 by inverting the first output signal OUT1. The second delay cell 920 may invert the second output signal OUT2 to output the second delayed clock signal DLCK2. A pull-down driving force for pulling down the first output signal OUT1 by the first delay cell 910 according to the input signal IN is based on the delay control voltage VC and the second output signal OUT2. It can be changed. When the pull-down driving force of the first delay cell 910 is changed, the amount of delay of the first delay cell 920 may be changed. A pull-down driving force by which the second delay cell 920 pulls down the second output signal OUT2 according to the first output signal OUT1 may be changed based on the delay control voltage VC. When the pull-down driving force of the second delay cell 920 is changed, the amount of delay of the second delay cell 920 may be changed. In one embodiment, the second delay cell 920 is another delay cell that may be disposed at the next stage of the second delay cell 920 (ie, a delay cell receiving the second output signal OUT2). The output signal OUT3 output from) may be further received. A pull-down driving force and a delay amount of the second delay cell 920 may be changed based on the delay control voltage VC and an output signal OUT3 output from the another delay cell.

The first delay cell 910 may include a first inverter 911, a first current source 912, and a first feedback current source 913. The first inverter 911 may generate the first output signal OUT1 by receiving the input signal IN and inverting the input signal IN. The first inverter 911 may be connected between a terminal supplied with a high voltage VH and a terminal supplied with a low voltage VL to invert the input signal IN. The first current source 912 may be connected between the first inverter 911 and a terminal to which the low voltage VL is supplied. The first current source 912 may receive the delay control voltage VC. The first current source 912 may change the amount of delay of the first delay cell 910 by changing a pull-down driving force of the first inverter 911 based on the delay control voltage VC. The first feedback current source 913 may be connected between the first inverter 911 and a terminal to which the low voltage VL is supplied. The first feedback current source 913 may receive the second output signal OUT2. The first feedback current source 913 may additionally change a pull-down driving force of the first inverter 911 based on the second output signal OUT2. The first delay cell 910 may further include a second inverter 914. The second inverter 914 may invert the first output signal OUT1 to output the first delayed clock signal DCLK1.

The second delay cell 920 may include a third inverter 921, a second current source 922, and a second feedback current source 923. The third inverter 921 may receive the first output signal OUT1 and generate the second output signal OUT2 by inverting the first output signal OUT1. The third inverter 921 may be connected between a terminal to which the high voltage VH is supplied and a terminal to which the low voltage VL is supplied to invert the first output signal OUT1. The second current source 922 may be connected between the third inverter 921 and a terminal to which the low voltage VL is supplied. The second current source 922 may receive the delay control voltage VC. The second current source 922 may change the amount of delay of the second delay cell 920 by changing a pull-down driving force of the third inverter 921 based on the delay control voltage VC. The second feedback current source 923 may be connected between the third inverter 921 and a terminal to which the low voltage VL is supplied. The second feedback current source 923 may receive an output signal OUT3 output from another delay cell. The second feedback current source 923 may additionally change the pull-down driving force of the third inverter 921 based on the output signal OUT3 output from the another delay cell. The second delay cell 920 may further include a fourth inverter 924. The fourth inverter 924 may invert the second output signal OUT2 to output the second delayed clock signal DCLK2.

The first inverter 911 may include a first transistor T1 and a second transistor T2. The first transistor T1 may be a P-channel MOS transistor, and the second transistor T2 may be an N-channel MOS transistor. The first current source 912 may include a third transistor T3. The third transistor T3 may be an N-channel MOS transistor. The first feedback current source 913 may include a fourth transistor T4. The fourth transistor T4 may be an N-channel MOS transistor. A gate of the first transistor T1 receives the input signal IN, a source of the first transistor T1 is connected to a terminal to which the high voltage VH is supplied, and the first transistor T1 The drain of may be connected to the first output node ON1. The first output signal OUT1 may be output through the first output node ON1. A gate of the second transistor T2 may receive the input signal IN, and a drain of the second transistor T2 may be connected to the first output node ON1. A gate of the third transistor T3 receives the delay control voltage VC, a drain of the third transistor T3 is connected to a source of the second transistor T2, and the third transistor T3 The source of) may be connected to a terminal to which the low voltage VL is supplied. The third transistor T3 may change an amount of current flowing from the source of the second transistor T2 to a terminal to which the low voltage VL is supplied based on the delay control voltage VC. A gate of the fourth transistor T4 receives the second output signal OUT2, a drain of the fourth transistor T4 is connected to a source of the second transistor T2, and the fourth transistor ( The source of T4) may be connected to a terminal to which the low voltage VL is supplied. The fourth transistor T4 may additionally change an amount of current flowing from the source of the second transistor T2 to a terminal to which the low voltage VL is supplied based on the second output signal OUT2.

The third inverter 921 may include a fifth transistor T5 and a sixth transistor T6. The fifth transistor T5 may be a P-channel MOS transistor, and the sixth transistor T6 may be an N-channel MOS transistor. The second current source 922 may include a seventh transistor T7. The seventh transistor T7 may be an N-channel MOS transistor. The second feedback current source 923 may include an eighth transistor T8. The eighth transistor T8 may be an N-channel MOS transistor. A gate of the fifth transistor T5 receives the first output signal OUT1, a source of the fifth transistor T5 is connected to a terminal to which the high voltage VH is supplied, and the fifth transistor ( The drain of T5) may be connected to the second output node ON2. The second output signal OUT2 may be output through the second output node ON2. A gate of the sixth transistor T6 may receive the first output signal OUT1, and a drain of the sixth transistor T6 may be connected to the second output node ON2. A gate of the seventh transistor T7 receives the delay control voltage VC, a drain of the seventh transistor T7 is connected to a source of the sixth transistor T6, and the seventh transistor T7 The source of) may be connected to a terminal to which the low voltage VL is supplied. The seventh transistor T7 may change an amount of current flowing from the source of the sixth transistor T6 to a terminal to which the low voltage VL is supplied based on the delay control voltage VC. A gate of the eighth transistor T8 receives an output signal OUT3 output from the another delay cell, and a drain of the eighth transistor T8 is connected to a source of the sixth transistor T6, The source of the eighth transistor T8 may be connected to a terminal to which the low voltage VL is supplied. The eighth transistor T8 additionally calculates the amount of current flowing from the source of the sixth transistor T6 to the terminal to which the low voltage VL is supplied based on the output signal OUT3 output from the another delay cell. You can change it.

As shown in FIG. 8B, the delay line 900 may improve a problem in that the first and second output signals OUT1 and OUT2 do not swing fully. The first and second feedback current sources 913 and 923 additionally increase the amount of current flowing from the first and third inverters 911 and 921 to terminals to which the low voltage VL is supplied, respectively, and The pull-down driving force of the second delay cells 910 and 920 may be additionally adjusted. As shown in FIG. 9B, the first and second feedback current sources 913 and 923 receive feedback of output signals output from delay cells disposed at the next stage, respectively, and the first and second delay cells 910 and 920 ), the pull-down driving force of) is additionally adjusted so that the first and second output signals OUT1 and OUT2 can pulley swing up to the level of the low voltage VL. Since the first and second feedback current sources 913 and 923 operate after the logic level of the output signal to be fed back is shifted, the first and second feedback current sources 913 and 923 are While the second output signals OUT1 and OUT2 may be pulled down to the level of the low voltage, the delay amounts of the first and second delay cells 910 and 920 may not be substantially changed.

10A to 10C are diagrams showing configurations of delay lines 1000A, 1000B, and 1000C according to an embodiment of the present invention. The delay lines 1000A, 1000B, and 1000C may be applied to the second delay line 221 and the delay line 410 shown in FIGS. 2 and 4, respectively. Referring to FIG. 10A, the delay line 1000A may include a first delay cell 10A and a second delay cell 20A. The first delay cell 10A may generate a first output signal OUT1 by inverting the input signal IN. The first delay cell 10A may invert the first output signal OUT1 to output a first delayed clock signal DCLK1. The second delay cell 20A may generate a second output signal OUT2 by inverting the first output signal OUT1. The second delay cell 20A may invert the second output signal OUT2 to output the second delayed clock signal DCLK2. The pull-down driving force for pulling down the first output signal OUT1 by the first delay cell 10A according to the input signal IN is based on the delay control voltage VC and the second output signal OUT. It can be changed. A pull-down driving force for pulling down the second output signal OUT2 by the second delay cell 20A according to the first output signal OUT1 is between the delay control voltage VC and the second delay cell 20A. It may be changed based on the output signal OUT3 output from another delay cell (that is, a delay cell receiving the second output signal OUT2) that may be disposed in the next stage.

The first delay cell 10A may include a first inverter 11A, a first current source 12A, and a first feedback current source 13A. The first inverter 11A may generate the first output signal OUT1 by receiving the input signal IN and inverting the input signal IN. The first inverter 11A may be connected between a terminal supplied with a high voltage VH and a terminal supplied with a low voltage VL to invert the input signal IN. The first current source 12A may be connected between the first inverter 11A and a terminal to which the low voltage VL is supplied. The first current source 12A may receive the delay control voltage VC. The first current source 12A may change the amount of delay of the first delay cell 10A by changing a pull-down driving force of the first inverter 11A based on the delay control voltage VC. The first feedback current source 13A may be connected between the first inverter 11A and a terminal to which the low voltage VL is supplied. The first feedback current source 13A may receive the second output signal OUT2. The first feedback current source 13A may additionally change the pull-down driving force of the first inverter 11A based on the second output signal OUT2. In an embodiment, the first feedback current source 13A may further receive the first switching signal SW1. The first feedback current source 13A may be selectively connected to the first inverter 11A according to the first switching signal SW1. The first delay cell 10A may further include a second inverter 14A. The second inverter 14A may invert the first output signal OUT1 to output the first delayed clock signal DCLK1.

In an embodiment, the first delay cell 10A may further include a first auxiliary current source 15A. The first auxiliary current source 15A may be connected between the first inverter 11A and a terminal to which the low voltage VL is supplied. The first auxiliary current source 15A may receive the delay control voltage VC. The first auxiliary current source 15A may additionally change the pull-down driving force of the first inverter 11A based on the delay control voltage VC. In an embodiment, the first auxiliary current source 15A may further receive a second switching signal SW2. The first auxiliary current source 15A may be selectively connected to the first inverter 11A according to the second switching signal SW2.

The second delay cell 20A may include a third inverter 21A, a second current source 22A, and a second feedback current source 23A. The third inverter 21A may receive the first output signal OUT1 and generate the second output signal OUT2 by inverting the first output signal OUT1. The third inverter 21A may be connected between a terminal to which the high voltage VH is supplied and a terminal to which the low voltage VL is supplied to invert the first output signal OUT1. The second current source 22A may be connected between the third inverter 21A and a terminal to which the low voltage VL is supplied. The second current source 22A may receive the delay control voltage VC. The second current source 22A may change the amount of delay of the second delay cell 20A by changing a pull-down driving force of the third inverter 21A based on the delay control voltage VC. The second feedback current source 23A may be connected between the third inverter 21A and a terminal to which the low voltage VL is supplied. The second feedback current source 23A may receive an output signal OUT3 output from another delay cell. The second feedback current source 23A may additionally change the pull-down driving force of the third inverter 21A based on the output signal OUT3 output from the another delay cell. In an embodiment, the second feedback current source 23A may further receive the first switching signal SW1. The second feedback current source 23A may be selectively connected to the third inverter 21A according to the first switching signal SW1. The second delay cell 20A may further include a fourth inverter 24A. The fourth inverter 24A may invert the second output signal OUT2 to output the second delayed clock signal DCLK2.

In an embodiment, the second delay cell 20A may further include a second auxiliary current source 25A. The second auxiliary current source 25A may be connected between the third inverter 21A and a terminal to which the low voltage VL is supplied. The second auxiliary current source 25A may receive the delay control voltage VC. The second auxiliary current source 25A may additionally change the pull-down driving force of the third inverter 21A based on the delay control voltage VC. In an embodiment, the second auxiliary current source 25A may further receive the second switching signal SW2. The second auxiliary current source 25A may be selectively connected to the third inverter 21A according to the second switching signal SW2.

The first inverter 11A may include a first transistor T11 and a second transistor T12. The first transistor T11 may be a P-channel MOS transistor, and the second transistor T12 may be an N-channel MOS transistor. The first current source 12A may include a third transistor T13. The third transistor T13 may be an N-channel MOS transistor. The first feedback current source 13A may include a fourth transistor T14 and a fifth transistor T15. The fourth and fifth transistors T14 and T15 may be N-channel MOS transistors. The first auxiliary current source 15A may include a sixth transistor T16 and a seventh transistor T17. The sixth and seventh transistors T16 and T17 may be N-channel MOS transistors. A gate of the first transistor T11 receives the input signal IN, a source of the first transistor T11 is connected to a terminal to which the high voltage VH is supplied, and the first transistor T11 The drain of may be connected to the first output node ON1. The first output signal OUT1 may be output through the first output node ON1. A gate of the second transistor T12 may receive the input signal IN, and a drain of the second transistor T12 may be connected to the first output node ON1. A gate of the third transistor T13 receives the delay control voltage VC, a drain of the third transistor T13 is connected to a source of the second transistor T12, and the third transistor T13 The source of) may be connected to a terminal to which the low voltage VL is supplied. The third transistor T13 may change an amount of current flowing from the source of the second transistor T12 to a terminal to which the low voltage VL is supplied based on the delay control voltage VC. A gate of the fourth transistor T14 may receive the second output signal OUT2, and a source of the fourth transistor T14 may be connected to a terminal to which the low voltage VL is supplied. A gate of the fifth transistor T15 receives the first switching signal SW1, a drain of the fifth transistor T15 is connected to a source of the second transistor T12, and the fifth transistor ( The source of T15) may be connected to the drain of the fourth transistor T14. The fourth transistor T14 may additionally change an amount of current flowing from the source of the second transistor T12 to a terminal to which the low voltage VL is supplied based on the second output signal OUT2, The fifth transistor T15 may selectively connect the fourth transistor T14 to the source of the second transistor T12 based on the first switching signal SW1. A gate of the sixth transistor T16 may receive the delay control voltage VC, and a source of the sixth transistor T16 may be connected to a terminal to which the low voltage VL is supplied. A gate of the seventh transistor T17 receives the second switching signal SW2, a drain of the seventh transistor T17 is connected to a source of the second transistor T12, and the seventh transistor ( The source of T17) may be connected to the drain of the sixth transistor T16. The sixth transistor T16 may additionally change the amount of current flowing from the source of the second transistor T12 to the terminal to which the low voltage VL is supplied based on the delay control voltage VC, and the The seventh transistor T17 may selectively connect the sixth transistor T16 to the source of the second transistor T12 based on the second switching signal SW2.

The third inverter 21A may include a first transistor T21 and a second transistor T22. The first transistor T21 may be a P-channel MOS transistor, and the second transistor T22 may be an N-channel MOS transistor. The second current source 22A may include a third transistor T23. The third transistor T23 may be an N-channel MOS transistor. The second feedback current source 23A may include a fourth transistor T24 and a fifth transistor T25. The fourth and fifth transistors T24 and T25 may be N-channel MOS transistors. The second auxiliary current source 25A may include a sixth transistor T26 and a seventh transistor T27. The sixth and seventh transistors T26 and T27 may be N-channel MOS transistors. A gate of the first transistor T21 receives the first output signal OUT1, a source of the first transistor T21 is connected to a terminal to which the high voltage VH is supplied, and the first transistor ( The drain of T21 may be connected to the second output node ON2. The second output signal OUT2 may be output through the second output node ON2. A gate of the second transistor T22 may receive the first output signal OUT1, and a drain of the second transistor T22 may be connected to the second output node ON2. A gate of the third transistor T23 receives the delay control voltage VC, a drain of the third transistor T23 is connected to a source of the second transistor T22, and the third transistor T23 The source of) may be connected to a terminal to which the low voltage VL is supplied. The third transistor T23 may change an amount of current flowing from the source of the second transistor T22 to a terminal to which the low voltage VL is supplied based on the delay control voltage VC. A gate of the fourth transistor T24 may receive an output signal OUT3 output from another delay cell, and a source of the fourth transistor T24 may be connected to a terminal to which the low voltage VL is supplied. A gate of the fifth transistor T25 receives the first switching signal SW1, a drain of the fifth transistor T25 is connected to a source of the second transistor T22, and the fifth transistor ( The source of T25 may be connected to the drain of the fourth transistor T24. The fourth transistor T24 additionally calculates the amount of current flowing from the source of the second transistor T22 to the terminal to which the low voltage VL is supplied based on the output signal OUT3 output from the another delay cell. The fifth transistor T25 may selectively connect the fourth transistor T24 to the source of the second transistor T22 based on the first switching signal SW1. A gate of the sixth transistor T26 may receive the delay control voltage VC, and a source of the sixth transistor T26 may be connected to a terminal to which the low voltage VL is supplied. A gate of the seventh transistor T27 receives the second switching signal SW2, a drain of the seventh transistor T27 is connected to a source of the second transistor T22, and the seventh transistor ( The source of T27) may be connected to the drain of the sixth transistor T26. The sixth transistor T26 may additionally change the amount of current flowing from the source of the second transistor T22 to the terminal to which the low voltage VL is supplied based on the delay control voltage VC, and the The seventh transistor T27 may selectively connect the sixth transistor T26 to the source of the second transistor T22 based on the second switching signal SW2.

Referring to FIG. 10B, the delay line 1000B may include a first delay cell 10B and a second delay cell 20B. The first delay cell 10B may generate a first output signal OUT1 by inverting the input signal IN. The first delay cell 10B may invert the first output signal OUT1 to output a first delayed clock signal DCLK1. The second delay cell 20B may generate a second output signal OUT2 by inverting the first output signal OUT1. The second delay cell 20B may invert the second output signal OUT2 to output the second delayed clock signal DCLK2. The pull-up driving force for pulling up the first output signal OUT1 by the first delay cell 10B according to the input signal IN is based on the delay control voltage VC and the second output signal OUT2. It can be changed. The pull-down driving force for pulling up the second output signal OUT2 by the second delay cell 20B according to the first output signal OUT1 is between the delay control voltage VC and the second delay cell 20B. It may be changed based on the output signal OUT3 output from another delay cell (that is, a delay cell receiving the second output signal OUT2) that may be disposed in the next stage.

The first delay cell 10B may include a first inverter 11B, a first current source 12B, and a first feedback current source 13B. The first inverter 11B may generate the first output signal OUT1 by receiving the input signal IN and inverting the input signal IN. The first inverter 11B may be connected between a terminal supplied with a high voltage VH and a terminal supplied with a low voltage VL to invert the input signal IN. The first current source 12B may be connected between a terminal to which the high voltage VH is supplied and the first inverter 11B. The first current source 12B may receive the delay control voltage VC. The first current source 12B may change the amount of delay of the first delay cell 10B by changing a pull-up driving force of the first inverter 11B based on the delay control voltage VC. The first feedback current source 13B may be connected between a terminal to which the high voltage VH is supplied and the first inverter 11B. The first feedback current source 13B may receive the second output signal OUT2. The first feedback current source 13B may additionally change the pull-up driving force of the first inverter 11B based on the second output signal OUT2. In an embodiment, the first feedback current source 13B may further receive the first switching signal SW1. The first feedback current source 13B may be selectively connected to the first inverter 11B according to the first switching signal SW1. The first delay cell 10B may further include a second inverter 14B. The second inverter 14B may invert the first output signal OUT1 to output the first delayed clock signal DCLK1.

In an embodiment, the first delay cell 10B may further include a first auxiliary current source 15B. The first auxiliary current source 15B may be connected between the terminal to which the high voltage VH is supplied and the first inverter 11B. The first auxiliary current source 15B may receive the delay control voltage VC. The first auxiliary current source 15B may additionally change the pull-up driving force of the first inverter 11B based on the delay control voltage VC. In an embodiment, the first auxiliary current source 15B may further receive a second switching signal SW2. The first auxiliary current source 15B may be selectively connected to the first inverter 11B according to the second switching signal SW2.

The second delay cell 20B may include a third inverter 21B, a second current source 22B, and a second feedback current source 23B. The third inverter 21B may receive the first output signal OUT1 and generate the second output signal OUT2 by inverting the first output signal OUT1. The third inverter 21B may be connected between a terminal to which the high voltage VH is supplied and a terminal to which the low voltage VL is supplied to invert the first output signal OUT1. The second current source 22B may be connected between the terminal to which the high voltage VH is supplied and the third inverter 21B. The second current source 22B may receive the delay control voltage VC. The second current source 22B may change the amount of delay of the second delay cell 20B by changing a pull-up driving force of the third inverter 21B based on the delay control voltage VC. The second feedback current source 23B may be connected between the terminal to which the high voltage VH is supplied and the third inverter 21B. The second feedback current source 23B may receive an output signal OUT3 output from another delay cell. The second feedback current source 23B may additionally change the pull-up driving force of the third inverter 21B based on the output signal OUT3 output from the another delay cell. In an embodiment, the second feedback current source 23B may further receive the first switching signal SW1. The second feedback current source 23B may be selectively connected to the third inverter 21B according to the first switching signal SW1. The second delay cell 20B may further include a fourth inverter 24B. The fourth inverter 24B may invert the second output signal OUT2 to output the second delayed clock signal DCLK2.

In one embodiment, the second delay cell 20B may further include a second auxiliary current source 25B. The second auxiliary current source 25B may be connected between a terminal to which the high voltage VH is supplied and the third inverter 21B. The second auxiliary current source 25B may receive the delay control voltage VC. The second auxiliary current source 25B may additionally change the pull-up driving force of the third inverter 21B based on the delay control voltage VC. In an embodiment, the second auxiliary current source 25B may further receive the second switching signal SW2. The second auxiliary current source 25B may be selectively connected to the third inverter 21B according to the second switching signal SW2.

The first inverter 11B may include a first transistor T31 and a second transistor T32. The first transistor T31 may be a P-channel MOS transistor, and the second transistor T32 may be an N-channel MOS transistor. The first current source 12B may include a third transistor T33. The third transistor T33 may be a P-channel MOS transistor. The first feedback current source T13B may include a fourth transistor T34 and a fifth transistor T35. The fourth and fifth transistors T34 and T35 may be P-channel MOS transistors. The first auxiliary current source 15B may include a sixth transistor T36 and a seventh transistor T37. The sixth and seventh transistors T36 and T37 may be P-channel MOS transistors. A gate of the first transistor T31 receives the input signal IN, a source of the first transistor T31 is connected to a terminal to which the high voltage VH is supplied, and the first transistor T31 The drain of may be connected to the first output node ON1. The first output signal OUT1 may be output through the first output node ON1. A gate of the second transistor T32 may receive the input signal IN, and a drain of the second transistor T32 may be connected to the first output node ON1. A gate of the third transistor T33 receives the delay control voltage VC, a source of the third transistor T33 is connected to a terminal to which the high voltage VH is supplied, and the third transistor T33 The drain of) may be connected to the source of the first transistor T31. The third transistor T33 may change an amount of current flowing from the terminal to which the high voltage VH is supplied to the source of the first transistor T31 based on the delay control voltage VC. A gate of the fourth transistor T34 may receive the second output signal OUT2, and a source of the fourth transistor T34 may be connected to a terminal to which the high voltage VH is supplied. A gate of the fifth transistor T35 receives the first switching signal SW1, a source of the fifth transistor T35 is connected to a drain of the fourth transistor T34, and the fifth transistor ( The drain of T35 may be connected to the source of the first transistor T31. The fourth transistor T34 may additionally change the amount of current flowing from the terminal to which the high voltage VH is supplied to the source of the first transistor T31 based on the second output signal OUT2, The fifth transistor T35 may selectively connect the fourth transistor T34 to the source of the first transistor T31 based on the first switching signal SW1. A gate of the sixth transistor T36 may receive the delay control voltage VC, and a source of the sixth transistor T36 may be connected to a terminal to which the high voltage VH is supplied. A gate of the seventh transistor T37 receives the second switching signal SW2, a source of the seventh transistor T37 is connected to a drain of the sixth transistor T36, and the seventh transistor ( The drain of T37 may be connected to the source of the first transistor T31. The sixth transistor T36 may additionally change the amount of current flowing from the terminal to which the high voltage VH is supplied to the source of the first transistor T31 based on the delay control voltage VC, and the The seventh transistor T37 may selectively connect the sixth transistor T36 to the source of the first transistor T31 based on the second switching signal SW2.

The third inverter 21B may include a first transistor T41 and a second transistor T42. The first transistor T41 may be a P-channel MOS transistor, and the second transistor T42 may be an N-channel MOS transistor. The first current source 22B may include a third transistor T43. The third transistor T43 may be a P-channel MOS transistor. The first feedback current source 23B may include a fourth transistor T44 and a fifth transistor T45. The fourth and fifth transistors T44 and T45 may be P-channel MOS transistors. The first auxiliary current source 25B may include a sixth transistor T46 and a seventh transistor T47. The sixth and seventh transistors T46 and T47 may be P-channel MOS transistors. A gate of the first transistor T41 receives the first output signal OUT1, a source of the first transistor T41 is connected to a terminal to which the high voltage VH is supplied, and the first transistor ( The drain of T41 may be connected to the second output node ON2. The first output signal OUT1 may be output through the second output node ON2. A gate of the second transistor T42 may receive the first output signal OUT1, and a drain of the second transistor T42 may be connected to the second output node ON2. A gate of the third transistor T43 receives the delay control voltage VC, a source of the third transistor T43 is connected to a terminal to which the high voltage VH is supplied, and the third transistor T43 The drain of) may be connected to the source of the first transistor T41. The third transistor T43 may change an amount of current flowing from the terminal to which the high voltage VH is supplied to the source of the first transistor T41 based on the delay control voltage VC. A gate of the fourth transistor T44 may receive an output signal OUT3 output from the another delay cell, and a source of the fourth transistor T44 may be connected to a terminal to which the high voltage VH is supplied. . A gate of the fifth transistor T45 receives the first switching signal SW1, a source of the fifth transistor T45 is connected to a drain of the fourth transistor T44, and the fifth transistor ( The drain of T45 may be connected to the source of the first transistor T41. The fourth transistor T44 may additionally change the amount of current flowing from the terminal to which the high voltage VH is supplied to the source of the first transistor T41 based on the second output signal OUT2, The fifth transistor T45 may selectively connect the fourth transistor T44 to the source of the first transistor T41 based on the first switching signal SW1. A gate of the sixth transistor T46 may receive the delay control voltage VC, and a source of the sixth transistor T46 may be connected to a terminal to which the high voltage VH is supplied. A gate of the seventh transistor T47 receives the second switching signal SW2, a source of the seventh transistor T47 is connected to a drain of the sixth transistor T46, and the seventh transistor ( The drain of T47 may be connected to the source of the first transistor T41. The sixth transistor T46 may additionally change the amount of current flowing from the terminal to which the high voltage VH is supplied to the source of the first transistor T41 based on the delay control voltage VC, and the The seventh transistor T47 may selectively connect the sixth transistor T46 to the source of the first transistor T41 based on the second switching signal SW2.

Referring to FIG. 10C, the delay line 1000C may include a first delay cell 10C and a second delay cell 20C. The first delay cell 10C may generate a first output signal OUT1 by inverting the input signal IN. The first delay cell 10C may invert the first output signal OUT1 to output a first delayed clock signal DCLK1. The second delay cell 20C may generate a second output signal OUT2 by inverting the first output signal OUT1. The second delay cell 20C may invert the second output signal OUT2 to output the second delayed clock signal DCLK2. A pull-up driving force by which the first delay cell 10C pulls up the first output signal OUT1 according to the input signal IN is based on a pull-up delay control voltage VCP and the second output signal OUT2. It can be changed. A pull-down driving force by which the first delay cell 10C pulls down the first output signal OUT1 according to the input signal IN is based on a pull-down delay control voltage VCN and the second output signal OUT2. It can be changed. The pull-up driving force for pulling up the second output signal OUT2 by the second delay cell 20C according to the first output signal OUT1 is the pull-up delay control voltage VCP and the second delay cell 20C. It may be changed based on the output signal OUT3 output from another delay cell (that is, a delay cell receiving the second output signal OUT2) that may be disposed at the next stage of. A pull-down driving force for pulling down the second output signal OUT2 by the second delay cell 20C according to the first output signal OUT1 is output from the pull-down delay control voltage VCN and the other delay cell. It may be changed based on the output signal OUT3. The first delay cell 10C may include a first inverter 11C, a first current source 12C, a second current source 13C, a first feedback current source 14C, and a second feedback current source 15C. . The first delay cell 10C may further include a second inverter 16C, a first auxiliary current source 17C, and a second auxiliary current source 18C. The second delay cell 20C may include a third inverter 21C, a third current source 22C, a fourth current source 23C, a third feedback current source 24C, and a fourth feedback current source 25C. . The second delay cell 20C may further include a fourth inverter 26C, a third auxiliary current source 27C, and a fourth auxiliary current source 28C. The delay line 1000C may have a form in which components of the delay lines 1000A and 1000B shown in FIGS. 10A and 10B are integrated.

The first inverter 11C may receive the input signal IN and generate a first output signal OUT1 by inverting the input signal IN. The first current source 12C may be connected between the terminal to which the high voltage VH is supplied and the first inverter 11C. The first current source 12C may receive the pull-up delay control voltage VCP. The first current source 12C may change a delay amount of the first delay cell 10C by adjusting a pull-up driving force of the first inverter 11C based on the pull-up delay control voltage VCP. The second current source 13C may be connected between the first inverter 11C and a terminal to which the low voltage VL is supplied. The second current source 13C may receive the pull-down delay control voltage VCN. The second current source 13C may change a delay amount of the first delay cell 10C by adjusting a pull-down driving force of the first inverter 11C based on the pull-down delay control voltage VCN. The first feedback current source 14C may be connected between a terminal to which the high voltage VH is supplied and the first inverter 11C. The first feedback current source 14C may receive the second output signal OUT2. The first feedback current source 14C may additionally change the pull-up driving force of the first inverter 11C based on the second output signal OUT2. In an embodiment, the first feedback current source 14C may further receive a complementary signal SW1B of the first switching signal SW1. The first feedback current source 14C may be selectively connected to the first inverter 11C according to the complementary signal SW1B. The second feedback current source 15C may receive the second output signal OUT2. The second feedback current source 15C may be connected between the first inverter 11C and a terminal to which the low voltage VL is supplied. The second feedback current source 15C may additionally change the pull-down driving force of the first inverter 11C based on the second output signal OUT2. In an embodiment, the second feedback current source 15C may further receive the first switching signal SW1. The second feedback current source 15C may be selectively connected to the first inverter 11C according to the first switching signal SW1. The second inverter 16C may invert the first output signal OUT1 to output the first delayed clock signal DCLK1. The first auxiliary current source 17C may be connected between the terminal to which the high voltage VH is supplied and the first inverter 11C. The first auxiliary current source 17C may receive the pull-up delay control voltage VCP. The first auxiliary current source 17C may additionally change the pull-up driving force of the first inverter 11C based on the pull-up delay control voltage VCP. In an embodiment, the first auxiliary current source 17C may further receive a complementary signal SW2B of the second switching signal SW2. The first auxiliary current source 17C may be selectively connected to the first inverter 11C according to the complementary signal SW2B. The second auxiliary current source 18C may be connected between the first inverter 11C and a terminal to which the low voltage VL is supplied. The second auxiliary current source 18C may receive the pull-down delay control voltage VCN. The second auxiliary current source 18C may additionally change the pull-down driving force of the first inverter 11C based on the pull-down delay control voltage VCN. In an embodiment, the second auxiliary current source 18C may further receive the second switching signal SW2. The second auxiliary current source 18C may be selectively connected to the first inverter 11C according to the second switching signal SW2.

The third inverter 21C may receive the first output signal OUT1 and generate a second output signal OUT2 by inverting the first output signal OUT1. The third current source 22C may be connected between the terminal to which the high voltage VH is supplied and the second inverter 21C. The third current source 22C may receive the pull-up delay control voltage VCP. The third current source 22C may change a delay amount of the second delay cell 20C by adjusting a pull-up driving force of the third inverter 21C based on the pull-up delay control voltage VCP. The fourth current source 23C may be connected between the third inverter 21C and a terminal to which the low voltage VL is supplied. The fourth current source 23C may receive the pull-down delay control voltage VCN. The fourth current source 23C may change a delay amount of the second delay cell 20C by adjusting a pull-down driving force of the third inverter 21C based on the pull-down delay control voltage VCN. The third feedback current source 24C may be connected between the terminal to which the high voltage VH is supplied and the third inverter 21C. The third feedback current source 24C may receive an output signal OUT3 output from another delay cell. The third feedback current source 24C may additionally change the pull-up driving force of the third inverter 21C based on the output signal OUT3 output from the another delay cell. In an embodiment, the third feedback current source 24C may further receive a complementary signal SW1B of the first switching signal SW1. The third feedback current source 24C may be selectively connected to the third inverter 21C according to the complementary signal SW1B. The fourth feedback current source 25C may receive an output signal OUT3 output from another delay cell. The second feedback current source 25C may be connected between the third inverter 21C and a terminal to which the low voltage VL is supplied. The fourth feedback current source 25C may additionally change the pull-down driving force of the third inverter 21C based on the output signal OUT3 output from the another delay cell. In an embodiment, the fourth feedback current source 25C may further receive the first switching signal SW1. The fourth feedback current source 25C may be selectively connected to the third inverter 21C according to the first switching signal SW1. The fourth inverter 26C may invert the second output signal OUT2 to output the second delayed clock signal DCLK2. The third auxiliary current source 27C may be connected between the terminal to which the high voltage VH is supplied and the third inverter 21C. The third auxiliary current source 27C may receive the pull-up delay control voltage VCP. The third auxiliary current source 27C may additionally change the pull-up driving force of the third inverter 21C based on the pull-up delay control voltage VCP. In an embodiment, the third auxiliary current source 27C may further receive a complementary signal SW2B of the second switching signal SW2. The third auxiliary current source 27C may be selectively connected to the third inverter 21C according to the complementary signal SW2B. The fourth auxiliary current source 28C may be connected between the third inverter 21C and a terminal to which the low voltage VL is supplied. The fourth auxiliary current source 28C may receive the pull-down delay control voltage VCN. The fourth auxiliary current source 28C may additionally change the pull-down driving force of the third inverter 21C based on the pull-down delay control voltage VCN. In an embodiment, the fourth auxiliary current source 28C may further receive the second switching signal SW2. The fourth auxiliary current source 28C may be selectively connected to the third inverter 21C according to the second switching signal SW2.

11 is a diagram illustrating a configuration of a semiconductor device 1100 according to an embodiment of the present invention. Referring to FIG. 11, the semiconductor device 1100 may generate a plurality of internal clock signals by receiving a clock signal CLK and performing a delay fixing operation on the clock signal CLK. The semiconductor device 1100 may include a delay locked loop circuit to generate the plurality of internal clock signals from the clock signal CLK. The semiconductor device 1100 may include a clock receiver 1110 (RX), a divider circuit 1120, a first delay locked loop 1130, a second delay locked loop 1140, and a clock generation circuit 1150. . The clock receiver 1110 may receive the clock signal CLK transmitted from the outside of the semiconductor device 1100. The clock receiver 1110 may buffer the clock signal CLK and output the buffered clock signal CLKR. The divider circuit 1120 may receive the buffered clock signal CLKR and the frequency information signal EN. The frequency information signal EN may have information on whether the semiconductor device 1100 operates at a relatively high frequency or a relatively low frequency. For example, when the semiconductor device 1100 operates at a high frequency, the frequency information signal EN may be enabled. When the semiconductor device 1100 operates at a low frequency lower than the high frequency, the frequency information signal EN may be disabled. The divider circuit 1120 may receive the buffered clock signal CLKR and divide the buffered clock signal CLKR to generate a divided clock signal ICLK. The divider circuit 1120 may provide the divided clock signal ICLK as a reference clock signal. The divider circuit 1120 may selectively output the buffered clock signal CLKR based on the frequency information signal EN. For example, when the frequency information signal EN is disabled, the divider circuit 1120 transmits the buffered clock signal CLKR together with the divided clock signal ICLK to the first delay locked loop 1130. ) Can be printed.

The first delay locked loop 1130 may be a digital delay locked loop including at least one digitally controlled delay line. The first delay locked loop 1130 may receive the reference clock signal, the frequency information signal EN, a first output clock signal ICLKD1 and a second output clock signal ICLKD2. The first delay locked loop 1130 is based on the reference clock signal and one of the first output clock signal ICLKD1 and the second output clock signal ICLKD2 based on the frequency information signal EN. A delay fixing operation may be performed on the reference clock signal. The first delay locked loop 1130 may receive the divided clock signal ICLK generated from the divider circuit 1120 as the reference clock signal. The first delay locked loop 1130 may delay the reference clock signal to generate a first delayed locked clock signal CLKDLL1, and delay the buffered clock signal CLKR to generate a second delayed locked clock signal ( CLKDLL2) can be created. When the frequency information signal EN is enabled, the first delay locked loop 1130 performs a delay fixing operation based on the first output clock signal ICLKD1 and the divided clock signal ICLK, A first delayed fixed clock signal CLKDLL1 may be generated by delaying the divided clock signal ICLK. When the frequency information signal EN is disabled, the first delay locked loop 1130 performs a delay fixing operation based on the second output clock signal ICLKD2 and the divided clock signal ICLK, A second delayed fixed clock signal CLKDLL2 may be generated by delaying the buffered clock signal CLKR.

The second delay locked loop 1140 may be an analog delay locked loop including a voltage controlled delay line. The second delay locked loop 1140 may receive the first delay locked clock signal CLKDLL1 to generate a first output clock signal ICLKD1. The second delay locked loop 1140 performs a delay locking operation on the first delay locked clock signal CLKDLL1 based on the first delay locked clock signal CLKDLL1 and the first output clock signal ICLKD1. Thus, the first output clock signal ICLKD1 may be generated. The second delay locked loop 1140 may generate a first plurality of output clock signals ICLKD1, QCLKD1, IBCLKD1, and QBCLKD1 by delaying the first delay locked clock signal CLKDLL1. One of the first plurality of output clock signals ICLKD1, QCLKD1, IBCLKD1, and QBCLKD1 may be provided as the first output clock signal ICLKD1.

The clock generation circuit 1150 may receive the second delayed fixed clock signal CLKDLL2. The clock generation circuit 1150 may generate the second output clock signal ICLKD2 based on the second delayed fixed clock signal CLKDLL2. The clock generation circuit 1150 may generate a plurality of second output clock signals ICLKD2, QCLKD2, IBCLKD2, and QBCLKD2 from the second delayed fixed clock signal CLKDLL2. One of the second plurality of output clock signals ICLKD2, QCLKD2, IBCLKD2, and QBCLKD2 may be provided as the second output clock signal ICLKD2. The clock generation circuit 1150 may further receive the frequency information signal EN. The clock generation circuit 1150 includes the first plurality of output clock signals ICLKD1, QCLKD1, IBCLKD1, QBCLKD1 and the second plurality of output clock signals ICLKD2, QCLKD2, IBCLKD2, based on the frequency information signal EN. One of QBCLKD2) may be output as a plurality of internal clock signals ICLKD, QCLKD, IBCLKD, and QBCLKD. When the frequency information signal EN is enabled, the clock generation circuit 1150 transmits the first plurality of output clock signals ICLKD1, QCLKD1, IBCLKD1, and QBCLKD1 to the plurality of internal clock signals ICLKD, QCLKD, IBCLKD, QBCLKD) can be output. When the frequency information signal EN is disabled, the clock generation circuit 1150 transmits the second plurality of output clock signals ICLKD2, QCLKD2, IBCLKD2, QBCLKD2 to the plurality of internal clock signals ICLKD, QCLKD, IBCLKD, QBCLKD) can be output.

When the semiconductor device 1100 operates at a high frequency, the frequency information signal EN is enabled, and a delay fixing operation is performed through the first delay locked loop 1130 and the second delay locked loop 1140. Can be done. The divider circuit 1120 may divide the buffered clock signal CLKR to output the divided clock signal ICLK as the reference clock signal. The first delay locked loop 1130 may generate the first delay locked clock signal CLKDLL1 by performing a delay fixing operation based on the divided clock signal ICLK and the first output clock signal ICLKD1. have. When the delay fixing operation of the first delay locked loop 1130 is completed, the second delay locked loop 1140 is applied to the first delay locked clock signal CLKDLL1 received from the first delay locked loop 1130. It is possible to perform a delay fixing operation. The second delay locked loop 1140 may generate the first plurality of output clock signals ICLKD1, QCLKD1, IBCLKD1, and QBCLKD1 by performing a delay fixing operation on the first delay locked clock signal CLKDLL1. . The clock generation circuit 1150 uses the plurality of first output clock signals ICLKD1, QCLKD1, IBCLKD1, QBCLKD1 output from the second delay locked loop 1140 to the plurality of internal clock signals ICLKD, QCLKD, IBCLKD, QBCLKD) can be used.

When the semiconductor device 1100 operates at a low frequency, the frequency information signal EN is disabled, and a delay fixing operation may be performed through the first delay locked loop 1130. The divider circuit 1120 may output the divided clock signal ICLK as the reference clock signal, and may output the buffered clock signal CLKR together with the divided clock signal. The first delay locked loop 1130 performs a delay fixing operation based on the divided clock signal ICLK and the second output clock signal ICLKD2, and delays the buffered clock signal CLKR. 2 A delayed fixed clock signal (CLKDLL2) can be generated. When the delay fixing operation of the first delay locked loop 1130 is completed, the clock generation circuit 1150 may receive the second delay locked clock signal CLKDLL2 from the first delay locked loop 1130. . The clock generation circuit 1150 may generate the second plurality of output clock signals ICLKD2, QCLKD2, IBCLKD2, and QBCLKD2 based on the second delayed fixed clock signal CLKDLL2. The clock generation circuit 1150 may output the second plurality of output clock signals ICLKD2, QCLKD2, IBCLKD2, and QBCLKD2 as the plurality of internal clock signals ICLKD, QCLKD, IBCLKD, and QBCLKD.

The divider circuit 1120 may include a clock divider 1121 and a gating circuit 1122. The clock divider 1121 may receive the buffered clock signal CLKR and divide the buffered clock signal CLKR. For example, the clock divider 1121 may generate four divided clock signals by dividing the buffered clock signal CLKR by two, and one of the four divided clock signals as the reference clock signal. Can be printed. For example, the clock divider 1121 converts one divided clock signal ICLK having a phase corresponding to the phase of the buffered clock signal CLKR among the four divided clock signals as the reference clock signal. Can be printed. The gating circuit 1122 may selectively output the buffered clock signal CLKR based on the frequency information signal EN. The gating circuit 1122 may receive the buffered clock signal CLKR and a complementary signal ENB of the frequency information signal EN. The gating circuit 1122 may gate the buffered clock signal CLKR as a complementary signal ENB of the frequency information signal EN. The gating circuit 1122 may include an AND gate. The gating circuit 1122 receives the buffered clock signal CLKR when the frequency information signal EN is disabled (that is, when the complementary signal ENB of the frequency information signal EN is enabled). It may be output to the first delay locked loop 1130.

The first delay locked loop 1130 may include a high frequency delay line 1131, a low frequency delay line 1132, a replica 1133, a first phase detector 1134, and a delay controller 1135. Both the high frequency delay line 1131 and the low frequency delay line 1132 may be digitally controlled delay lines. The high frequency delay line 1131 may receive the divided clock signal ICLK, a delay control signal DC, and the frequency information signal EN. When the frequency information signal EN is enabled, the high frequency delay line 1131 delays the divided clock signal ICLK based on the delay control signal DC, and thus the first delayed fixed clock signal CLKDLL1 ) Can be created. The high frequency delay line 1131 may be deactivated when the frequency information signal EN is disabled. The low frequency delay line 1132 may receive the buffered clock signal CLKR and the delay control signal DC. The low frequency delay line 1132 may generate the second delayed fixed clock signal CLKDLL2 by delaying the buffered clock signal CLKR based on the delay control signal DC.

The replica 1133 may receive one of the first output clock signal ICLKD1 and the second output clock signal ICLKD2. When the frequency information signal EN is enabled, the replica 1133 receives the first output clock signal ICLKD1 and delays the first output clock signal ICLKD1 by a modeled delay time, The feedback clock signal FBCLK1 may be output. When the frequency information signal EN is disabled, the replica 1133 receives the second output clock signal ICLKD2, and delays the second output clock signal ICLKD2 by a modeled delay time. 1 A feedback clock signal FBCLK1 may be output. In one embodiment, the replica 1133 receives one of the plurality of internal clock signals ICLKD, QCLKD, IBCLKD, and QBCLKD output from the clock generation circuit 1150 regardless of the frequency information signal EN. Can be modified to For example, the replica 1133 is the internal clock signal having a phase corresponding to the first and second output clock signals ICLKD1 and ICLKD2 among the plurality of internal clock signals ICLKD, QCLKD, IBCLKD, and QBCLKD. It can be modified to receive (ICLKD).

The first phase detector 1134 may generate the first phase detection signal PD1 by comparing the phases of the divided clock signal ICLK provided as the reference clock signal and the first feedback clock signal FBCLK1. have. The delay controller 1135 may generate the delay control signal DC1 based on the first phase detection signal PD1. The delay controller 1135 may increase or decrease the value of the delay control signal DC according to the logic level of the first phase detection signal PD1. The delay control signal DC may be commonly provided to the high frequency delay line 1131 and the low frequency delay line 1132. The delay amounts of the high frequency delay line 1131 and the low frequency delay line 1132 may be set based on the delay control signal DC.

The first delay locked loop 1130 may further include a clock selector 1136. The clock selector 1146 may receive the first output clock signal ICLKD1, the second output clock signal ICLKD2, and the frequency information signal EN. The clock selector 1136 may receive one of the first output clock signal ICLKD1 and the second output clock signal ICLKD2 based on the frequency information signal EN. The clock selector 1136 may be connected to the replica 1133, and a clock signal output from the clock selector 1136 may be input to the replica 1133. The clock selector 1136 may output the first output clock signal ICLKD1 to the replica 1133 when the frequency information signal EN is enabled. The clock selector 1136 may output the second output clock signal ICLKD2 to the replica 1133 when the frequency information signal EN is disabled.

The second delay locked loop 1140 may include a voltage controlled delay line 1141, a correction circuit 1142, a second phase detector 1143, and a charge pump 1144. The voltage control delay line 1141 may receive the first delayed fixed clock signal CLKDLL1 and the delay control voltage VC. The voltage control delay line 1141 delays the first delayed fixed clock signal CLKDLL1 based on the delay control voltage VC to provide a first output clock signal ICLKD1 and a second feedback clock signal FBCLK2. Can be generated. In addition, the voltage control delay line 1141 delays the first delayed fixed clock signal CLKDLL1 to generate the remaining first plurality of output clock signals QCLK1, IBCLK1, QBLCK1 other than the first output clock signal. I can. The correction circuit 1142 may receive the first output clock signal ICLKD1 and the second feedback clock signal FBCLK2. The correction circuit 1142 detects the phases of the first output clock signal ICLKD1 and the second feedback clock signal FBCLK2, and delays the first output clock signal ICLKD1 to determine the delay reference clock signal REFD. ) And delaying the second feedback clock signal FBCLK2 to generate a delayed feedback clock signal FEBD. The correction circuit 1142 is a phase error between the first output clock signal ICLKD1 and the second feedback clock signal FBCLK2, which may occur due to components constituting the second delay locked loop 1140 Is compensated so that the second delay locked loop 1140 can perform an accurate delay fixing operation. The correction circuit 420 illustrated in FIG. 4 may be applied to the correction circuit 1142. The second phase detector 1143 may receive the delayed reference clock signal REFD and the delayed feedback clock signal FEBD. The second phase detector 1143 may generate a second phase detection signal PD2 by detecting phases of the delayed reference clock signal REFD and the delayed feedback clock signal FEBD. The second phase detection signal PD2 may include an up signal UP and a down signal DN. The charge pump 1144 may receive the second phase detection signal PD2 and generate the delay control voltage VC based on the second phase detection signal PD2. The charge pump 1144 raises the voltage level of the delay control voltage VC based on the up signal UP, and adjusts the voltage level of the delay control voltage VC based on the down signal DN. You can descend.

The clock generation circuit 1150 may include a multi-phase clock generator 1151 and a clock selector 1152. The multi-phase clock generator 1151 may receive the second delayed fixed clock signal CLKDLL2. The multi-phase clock generator 115 may generate the second plurality of output clock signals ICLKD2, QCLKD2, IBCLKD2, and QBCLKD2 from the second delayed fixed clock signal CLKDLL2. The multi-phase clock generator 1151 divides the phase of the second delayed fixed clock signal CLKDLL2, divides the frequency of the second delayed fixed clock signal CLKDLL2, Output clock signals ICLKD2, QCLKD2, IBCLKD2, and QBCLKD2 can be generated. Although not shown, the multi-phase clock generator 1151 may include components such as a phase splitter and a divider. The clock selector 1152 includes the frequency information signal EN, the first plurality of output clock signals ICLKD1, QCLKD1, IBCLKD1, QBCLKD1, and the second plurality of output clock signals ICLKD2, QCLKD2, IBCLKD2, QBCLKD2. Can be received. The clock selector 1152 includes the first plurality of output clock signals ICLKD1, QCLKD1, IBCLKD1, QBCLKD1 and the second plurality of output clock signals ICLKD2, QCLKD2, IBCLKD2, based on the frequency information signal EN. One of QBCLKD2) may be output as the plurality of internal clock signals ICLKD, QCLKD, IBCLKD, and QBCLKD. When the frequency information signal EN is enabled, the clock selector 1152 transmits the first plurality of output clock signals ICLKD1, QCLKD1, IBCLKD1, and QBCLKD1 to the plurality of internal clock signals ICLKD, QCLKD, and IBCLKD. , QBCLKD). When the frequency information signal EN is disabled, the clock selector 1152 transmits the second plurality of output clock signals ICLKD2, QCLKD2, IBCLKD2, QBCLKD2 to the plurality of internal clock signals ICLKD, QCLKD, and IBCLKD. , QBCLKD).

The semiconductor device 1100 includes a command receiver 1210 (RX), a command decoder 1220, a command delay line 1230, a clock generation replica 1240, a delay cell replica 1250, a command selector 1260, and a synchronization circuit. (1270) may be included. The command receiver 1210 may receive the command signal CMD transmitted from the outside of the semiconductor device 1100. The command signal CMD may be a control signal that enables the semiconductor device 1100 to perform various operations. The command signal CMD may include a plurality of different types of signals. The command decoder 1220 may generate an internal command signal ICMD by decoding the command signal CMD received through the command receiver 1210. The command decoder 1220 may generate various internal command signals ICMD based on the command signal CMD. Although not limited, for example, the internal command signal ICMD may include an active command signal, a precharge command signal, a read command signal, a write command signal, an on-die termination command signal, a refresh command signal, and the like. The command decoder 1220 latches the command signal CMD received through the command receiver 1210 based on the buffered clock signal CLKR, decodes the latched command signal, and decodes the internal command signal ICMD. ) Can be created.

The command delay line 1230 may receive the internal command signal ICMD and the delay control signal DC. The command delay line 1230 may generate a delay command signal DCMD by delaying the internal command signal ICMD based on the delay control signal DC. The delay amount of the command delay line 1230 may be set based on the delay control signal DC. The command delay line 1230 may have substantially the same configuration as the high frequency delay line 1131 and/or the low frequency delay line 1132. Since the command delay line 1230, the high frequency delay line 1131, and the low frequency delay line 1132 commonly receive the delay control signal DC, the amount of delay of the command delay line 1230 is It may be set equal to the delay amount of the high frequency delay line 1131 and/or the low frequency delay line 1132. The internal command signal ICMD is the command delay line as long as the divided clock signal ICLK or the buffered clock signal CLKR is delayed through the high frequency delay line 1131 or the low frequency delay line 1132. It can be delayed through (1230).

The clock generation replica 1240 may delay the delay command signal DCMD to additionally output a delayed command signal. The clock generation replica 1240 is a circuit modeling the clock generation circuit 1150 and is required to generate the second plurality of output clock signals ICLKD2, QCLKD2, IBCLKD2, QBCLKD2 from the clock generation circuit 1150. The delay command signal DCMD may be additionally delayed by a period of time. The second delayed fixed clock signal CLKDLL2 delayed through the low-frequency delay line 1132 may be generated as the second plurality of output clock signals ICLKD2, QCLKD2, IBCLKD2, QBCLKD2 through the clock generation circuit 1150. have. Therefore, the clock generation replica 1240 takes the delay command signal DCMD to generate the second plurality of output clock signals ICLKD2, QCLKD2, IBCLKD2, QBCLKD2 from the second delayed fixed clock signal CLKDLL2. The timing of the command signal output from the clock generation replica 1240 and the phase of the second plurality of output clock signals ICLKD1, QCLKD1, IBCLKD1, and QBCLKD1 may be matched by delaying by a predetermined time.

The delay cell replica 1250 may be a model of at least one of a plurality of delay cells constituting the voltage controlled delay line 1141. The number of delay cells included in the delay cell replica 1250 may correspond to the number of delay cells used to generate the first output clock signal ICLKD1 from the first delayed fixed clock signal CLKDLL1. For example, when the first delayed fixed clock signal CLKDLL1 is delayed through one delay cell in the voltage-controlled delay line 1141 to be generated as the first output clock signal ICLKD1, the delay cell The replica 1250 may be configured to include one delay cell. The delay cell replica 1250 receives the delay command signal DCMD and the delay control voltage DC, and delays the delay command signal DCMD based on the delay control voltage VC to additionally delay the command. It can generate a signal. The first delayed fixed clock signal CLKDLL1 delayed through the high frequency delay line 1131 may be additionally delayed through the voltage controlled delay line 1141 of the second delay locked loop 1140. The delay cell replicator 1250 takes the delay command signal DCMD to generate the first output clock signals ICLKD1, QCLKD1, IBCLKD1, and QBCLKD1 from the first delayed fixed clock signal CLKDLL1. The timing of the command signal output from the delayed cell replica 1250 and the phase of the first plurality of output clock signals ICLKD1, QCLKD1, IBCLKD1, and QBCLKD1 may be matched by delaying by a delay.

The command selector 1260 may receive an output signal of the clock generation replica 1240, an output signal of the delay cell replica 1250, and the frequency information signal EN. The command selector 1260 outputs one of the output signal of the clock generation replica 1240 and the output signal of the delay cell replica 1250 as an asynchronous command signal ASCMD based on the frequency information signal EN. I can. When the frequency information signal EN is enabled, the command selector 1260 may output an output signal of the delay cell replica 1250 as the asynchronous command signal ASCMD. When the frequency information signal EN is disabled, the command selector 1260 may output an output signal of the clock generation replica 1240 as the asynchronous command signal ASCMD.

The synchronization circuit 1270 may receive one of the plurality of internal clock signals ICLKD, QCLKD, IBCLKD, and QBCLKD and the asynchronous signal ASCMD. For example, the synchronization circuit 1270 may receive the internal clock signal ICLKD. The synchronization circuit 1270 may change the domain of the asynchronous command signal ASCMD. The synchronization circuit 1270 may output the synchronization command signal SCMD by synchronizing the asynchronous command signal ASCMD with the internal clock signal ICLKD. The synchronous circuit 1270 converts the asynchronous command signal ASCMD into a synchronous command signal SCMD synchronized with the internal clock signal ICLKD, and the synchronous command signal SCMD is applied to the semiconductor device 1100. Make it available for use in internal circuits. In an embodiment, the synchronization circuit 1270 may be modified to generate the synchronization command signal SCMD in synchronization with the internal clock signal QCLKD.

Those skilled in the art to which the present invention pertains, since the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof, the embodiments described above are illustrative in all respects and should be understood as non-limiting. Only do it. The scope of the present invention is indicated by the claims to be described later rather than the detailed description, and all changes or modified forms derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included in the scope of the present invention. do.

Claims (34)

A first delay locked loop for generating a delay locked clock signal by performing a delay fixing operation on the reference clock signal based on a reference clock signal and an internal clock signal; And
A delay locked loop circuit comprising a second delay locked loop configured to generate the internal clock signal by performing a delay fixing operation on the delay locked clock signal based on the delay locked clock signal and the internal clock signal. The method of claim 1,
The first delay locked loop may include: a first delay line configured to delay the reference clock signal based on a delay control signal to generate the delay locked clock signal;
A replica for generating a first feedback clock signal by delaying the internal clock signal by a modeled delay time;
A first phase detector for generating a first phase detection signal by comparing the phases of the reference clock signal and the first feedback clock signal; And
A delay locked loop circuit comprising a delay controller generating the delay control signal based on the first phase detection signal. The method of claim 1,
The second delay locked loop may include: a second delay line for generating the internal clock signal and a second feedback clock signal by delaying the delay locked clock signal based on a delay control voltage;
A second phase detector for generating a second phase detection signal by comparing the phases of the internal clock signal and the second feedback clock signal; And
A delay locked loop circuit comprising a charge pump generating the delay control voltage based on the second phase detection signal. The method of claim 1,
The second delay locked loop may include: a second delay line for generating the internal clock signal and a second feedback clock signal by delaying the delay locked clock signal based on a delay control voltage;
A correction circuit for generating a delayed reference clock signal from the internal clock signal and a delayed feedback clock signal from the second feedback clock signal based on the phase of the internal clock signal and the second feedback clock signal;
A second phase detector configured to detect phases of the internal clock signal and the delayed feedback clock signal to generate a second phase detection signal; And
A delay locked loop circuit comprising a charge pump generating the delay control voltage based on the second phase detection signal. The method of claim 4,
When the phase of the second feedback clock signal is later than the phase of the internal clock signal, the correction circuit delays the internal clock signal by a first time and outputs the delayed reference clock signal, and the second feedback clock signal To generate the delayed feedback clock signal by delaying by a second time longer than the first time,
When the phase of the second feedback clock signal is ahead of the phase of the internal clock signal, the internal clock signal is delayed by the second time and output as the delayed reference clock signal, and the second feedback clock signal is output to the first A delay locked loop circuit for generating the delayed feedback clock signal by delaying it by a period of time. The method of claim 4,
The correction circuit includes: a timing skew detector configured to detect phases of the internal clock signal and the second feedback clock signal to generate a first phase control signal and a second phase control signal;
A calibration signal generator that generates a calibration signal based on the first and second phase control signals; And
Delay for generating the delayed reference clock signal by delaying the internal clock signal based on a part of the calibration signal, and generating the delayed feedback clock signal by delaying the second feedback clock signal based on the remainder of the calibration signal Delay locked loop circuit with regulator. The method of claim 6,
The timing skew detector detects the phases of the internal clock signal and the second feedback clock signal to generate a first skew detection signal and a second skew detection signal, and the logic level of the first and second skew detection signals is at least A delay locked loop circuit for generating the first phase control signal and the second phase control signal according to whether or not it is maintained for a time corresponding to twice a unit cycle. The method of claim 7,
The timing skew detector may include: a skew detector configured to detect phases of the internal clock signal and the second feedback clock signal to generate a first skew detection signal and a second skew detection signal;
A second clock signal that is generated as a first even signal from the first skew detection signal in synchronization with a first clock signal and a second even signal from the second skew detection signal, and has a later phase than the first clock signal Synchronously, the first skew detection signal is generated as a first odd signal and the second skew detection signal is generated as a second odd signal, and the first even signal, the second even signal, the first odd signal, and A filter generating a first phase information signal and a second phase information signal based on the second odd signal; And
A delay locked loop circuit comprising a phase control signal generator that generates the first phase control signal based on the first phase information signal and generates the second phase control signal based on the second phase information signal. The method of claim 6,
The delay adjuster includes: a first variable delay unit configured to set a delay amount based on a part of the calibration signal and delay the internal clock signal to generate the delay reference clock signal; And
A delay locked loop circuit comprising a second variable delay configured to generate the delayed feedback clock signal by setting a delay amount based on the remainder of the calibration signal and delaying the second feedback clock signal. The method of claim 4,
The delay line includes at least a first delay cell and a second delay cell,
The first delay cell inverts an input signal to generate a first output signal, the second delay cell inverts the first output signal to generate a second output signal,
A driving force for pulling down the first output signal by the first delay cell is adjusted based on the delay control voltage and the second output signal. The method of claim 4,
The delay line includes at least a first delay cell and a second delay cell,
The first delay cell inverts an input signal to generate a first output signal, the second delay cell inverts the first output signal to generate a second output signal,
A driving force for pulling up the first output signal by the first delay cell is adjusted based on the delay control voltage and the second output signal. The method of claim 4,
The delay line includes at least a first delay cell and a second delay cell, and the delay control voltage includes a pull-up control voltage and a pull-down control voltage,
The first delay cell inverts an input signal to generate a first output signal, the second delay cell inverts the first output signal to generate a second output signal,
A driving force for pulling up the first output signal by the first delay cell is adjusted based on a pull-up control voltage and the second output signal, and a driving force for pulling down the first output signal by the first delay cell is a pull-down control voltage And a delay locked loop circuit that is adjusted based on the second output signal. A clock receiver that buffers an external clock signal and outputs the buffered clock signal;
A divider circuit for generating a reference clock signal by dividing the buffered clock signal, and selectively outputting the buffered clock signal based on a frequency information signal;
Performing a delay fixing operation based on the reference clock signal and one of a first output clock signal and a second output clock signal based on the frequency information signal to generate a first fixed delay clock signal from the reference clock signal, and the A first delay locked loop for generating a second delay locked clock signal from the buffered clock signal;
A second delay locked loop for generating the first output clock signal by performing a delay fixing operation on the first delayed fixed clock signal based on the first delayed fixed clock signal and the first output clock signal; And
And a clock generation circuit that generates a second output clock signal based on the second delayed fixed clock signal. The method of claim 13,
The divider circuit comprises: a clock divider for generating a divided clock signal by dividing the buffered clock signal, and outputting the divided clock signal as the reference clock signal; And
And a gating circuit selectively outputting the buffered clock signal according to the frequency information signal. The method of claim 13,
The first delay locked loop may include: a high frequency digital control delay line for generating a first delay locked clock signal by delaying the reference clock signal based on the frequency information signal and a delay control signal;
A low frequency digital control delay line for generating the second delayed fixed clock signal by delaying the buffered clock signal based on the delay control signal;
A replica for generating a first feedback clock signal by delaying one of the first output clock signal and the second output clock signal by a modeled delay time;
A first phase detector for generating a first phase detection signal by comparing a phase of the reference clock signal and the first feedback clock signal; And
And a delay controller configured to generate the delay control signal based on the first phase detection signal. The method of claim 13,
The second delay locked loop includes: a voltage controlled delay line configured to delay the first delayed fixed clock signal based on a delay control voltage to generate the first output clock signal and a second feedback clock signal;
A second phase detector configured to detect phases of the first output clock signal and the second feedback clock signal to generate a second phase detection signal; And
And a charge pump generating the delay control voltage based on the second phase detection signal. The method of claim 13,
The second delay locked loop includes: a voltage controlled delay line configured to delay the first delayed fixed clock signal based on a delay control voltage to generate the first output clock signal and a second feedback clock signal;
A correction circuit for generating a delayed reference clock signal from the first output clock signal and a delayed feedback clock signal from the second feedback clock signal based on the phases of the first output clock signal and the second feedback clock signal;
A second phase detector for generating a second phase detection signal by comparing a phase of the delayed reference clock signal and the delayed feedback clock signal; And
And a charge pump generating the delay control voltage based on the second phase detection signal. The method of claim 17,
The correction circuit, when the phase of the second feedback clock signal is later than the phase of the first output clock signal, delays the first output clock signal by a first time and outputs the delayed reference clock signal, and the second 2 generating the delayed feedback clock signal by delaying the feedback clock signal by a second time longer than the first time,
When the phase of the second feedback clock signal is ahead of the phase of the first output clock signal, the first output clock signal is delayed by the second time and output as the delayed reference clock signal, and the second feedback clock signal The semiconductor device generating the delayed feedback clock signal by delaying the signal by the first time. The method of claim 17,
The correction circuit includes: a timing skew detector configured to detect phases of the first output clock signal and the second feedback clock signal to generate a first phase adjustment signal and a second phase adjustment signal;
A calibration signal generator that generates a calibration signal based on the first and second phase control signals; And
The delayed reference clock signal is generated by delaying the first output clock signal based on a part of the calibration signal, and the delayed feedback clock signal is generated by delaying the second feedback clock signal based on the remainder of the calibration signal. A semiconductor device comprising a delay adjuster. The method of claim 19,
The timing skew detector detects the phases of the first output clock signal and the second feedback clock signal to generate a first skew detection signal and a second skew detection signal, and the logic level of the first and second skew detection signals A semiconductor device that generates the first phase control signal and the second phase control signal according to whether or not it is maintained for a time corresponding to at least twice the unit cycle. The method of claim 19,
The timing skew detector may include: a skew detector configured to detect phases of the first output clock signal and the second feedback clock signal to generate a first skew detection signal and a second skew detection signal;
A second clock signal that is generated as a first even signal from the first skew detection signal in synchronization with a first clock signal and a second even signal from the second skew detection signal, and has a later phase than the first clock signal Synchronously, the first skew detection signal is generated as a first odd signal and the second skew detection signal is generated as a second odd signal, and the first even signal, the second even signal, the first odd signal, and A filter generating a first phase information signal and a second phase information signal based on the second odd signal; And
A semiconductor device comprising a phase control signal generator that generates the first phase control signal based on the first phase information signal and generates the second phase control signal based on the second phase information signal. The method of claim 19,
The delay adjuster includes: a first variable delay unit configured to generate the delay reference clock signal by setting a delay amount based on a part of the calibration signal and delaying the first output clock signal; And
A semiconductor device comprising: a second variable delayer configured to generate the delayed feedback clock signal by setting a delay amount based on the remainder of the calibration signal and delaying the second feedback clock signal. The method of claim 13,
The clock generation circuit further comprises a clock selector configured to output one of the first output clock signal and the second output clock signal as an internal clock signal based on the frequency information signal. The method of claim 13,
The first delay locked loop further includes a clock selector configured to receive one of the first output clock signal and the second output clock signal based on the frequency information signal. A voltage controlled delay line for generating an internal clock signal and a feedback clock signal by delaying the reference clock signal based on the delay control voltage;
A correction circuit for generating a delayed reference clock signal and a delayed feedback clock signal by delaying the internal clock signal and the feedback clock signal based on phases of the internal clock signal and the feedback clock signal;
A phase detector comparing phases of the delayed reference clock signal and the delayed feedback clock signal to generate a phase detection signal; And
A delay locked loop circuit comprising a charge pump generating the delay control voltage based on the phase detection signal. The method of claim 25,
The voltage control delay line delays the reference clock signal based on the delay control voltage to generate a plurality of delayed clock signals, outputs one of the plurality of delayed clock signals as the internal clock signal, and the plurality of A delay locked loop circuit for outputting the other one of the delayed clock signals as the feedback clock signal. The method of claim 25,
The voltage controlled delay line includes at least a first delay cell and a second delay cell,
The first delay cell inverts an input signal to generate a first output signal, the second delay cell inverts the first output signal to generate a second output signal,
A driving force for pulling down the first output signal by the first delay cell is adjusted based on the delay control voltage and the second output signal. The method of claim 25,
The delay line includes at least a first delay cell and a second delay cell,
The first delay cell inverts an input signal to generate a first output signal, the second delay cell inverts the first output signal to generate a second output signal,
A driving force for pulling up the first output signal by the first delay cell is adjusted based on the delay control voltage and the second output signal. The method of claim 25,
The delay line includes at least a first delay cell and a second delay cell, and the delay control voltage includes a pull-up control voltage and a pull-down control voltage,
The first delay cell inverts an input signal to generate a first output signal, the second delay cell inverts the first output signal to generate a second output signal,
A driving force for pulling up the first output signal by the first delay cell is adjusted based on a pull-up control voltage and the second output signal, and a driving force for pulling down the first output signal by the first delay cell is a pull-down control voltage And a delay locked loop circuit that is adjusted based on the second output signal. The method of claim 25,
The correction circuit, when the phase of the feedback clock signal is later than the phase of the internal clock signal, delays the internal clock signal by a first time and outputs the delayed reference clock signal, and outputs the feedback clock signal to the first Delayed by a second time longer than the time to generate the delayed feedback clock signal,
When the phase of the feedback clock signal is ahead of the phase of the internal clock signal, the internal clock signal is delayed by the second time and output as the delayed reference clock signal, and the feedback clock signal is delayed by the first time. A delay locked loop circuit for generating the delayed feedback clock signal. The method of claim 25,
The correction circuit includes: a timing skew detector configured to generate a first phase control signal and a second phase control signal by detecting phases of the internal clock signal and the feedback clock signal;
A calibration signal generator that generates a calibration signal based on the first and second phase control signals; And
A delay adjuster for generating the delayed reference clock signal by delaying the internal clock signal based on a part of the calibration signal, and delaying the feedback clock signal based on the remainder of the calibration signal to generate the delayed feedback clock signal Including a delay locked loop. The method of claim 31,
The timing skew detector generates a first skew detection signal and a second skew detection signal by detecting phases of the internal clock signal and the feedback clock signal, and the logic level of the first and second skew detection signals is at least a unit A delay locked loop circuit for generating the first phase adjustment signal and the second phase adjustment signal depending on whether or not it is maintained for a time corresponding to twice a cycle. The method of claim 31,
The timing skew detector may include: a skew detector configured to detect phases of the internal clock signal and the feedback clock signal to generate a first skew detection signal and a second skew detection signal;
A second clock signal that is generated as a first even signal from the first skew detection signal in synchronization with a first clock signal and a second even signal from the second skew detection signal, and has a later phase than the first clock signal Synchronously, the first skew detection signal is generated as a first odd signal and the second skew detection signal is generated as a second odd signal, and the first even signal, the second even signal, the first odd signal, and A filter generating a first phase information signal and a second phase information signal based on the second odd signal; And
A delay locked loop circuit comprising a phase control signal generator that generates the first phase control signal based on the first phase information signal and generates the second phase control signal based on the second phase information signal. The method of claim 31,
The delay adjuster includes: a first variable delay unit configured to set a delay amount based on a part of the calibration signal and delay the internal clock signal to generate the delay reference clock signal; And
A delay locked loop circuit comprising a second variable delay configured to generate the delayed feedback clock signal by setting a delay amount based on the remainder of the calibration signal and delaying the feedback clock signal.

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