KR100685604B1 - Delay locked loop for generating a internal clock signal with decreased jitter components - Google Patents

Abstract

The present invention relates to a DLL that generates an internal clock signal with reduced jitter component, wherein the DLL according to the present invention is output such that the output signal of the up-down counter is output in synchronization with the falling edge of the previous internal clock signal. By controlling, a stable internal clock signal with reduced jitter components can be generated. Further, according to the present invention, since the jitter component of the internal clock signal is reduced, the glitch noise component included in a signal output from a circuit such as a data output buffer of the semiconductor memory device operating in synchronization with the internal clock signal can be reduced. have.

Clock Delay Circuit, Unit Delay Circuit, Output Control Circuit, Internal Clock Signal, Polling Edge

Description

Delay locked loop for generating a internal clock signal with reduced jitter components}

1 is a block diagram schematically illustrating a conventional DLL and an output buffer of a semiconductor memory device.

FIG. 2 is a timing diagram of signals related to the operation of the DLL and the output buffer shown in FIG. 1.

3 is a block diagram schematically illustrating a DLL and an output buffer of a semiconductor memory device according to an embodiment of the present invention.

4 is a diagram illustrating the output control circuit shown in FIG. 3 in more detail.

FIG. 5 is a detailed circuit diagram of the delay unit illustrated in FIG. 3.

6 is a timing diagram of signals related to the operation of the DLL illustrated in FIG. 3.

<Explanation of symbols for main parts of drawing>

100: DLL 110: Clock Receiver

120: phase detector 130: up-down counter

140: output control circuit 150: clock delay circuit

160: replica delay unit ISC1 to ISCN: input circuit

OSC1 to OSCN: Output Circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly, to a delay locked loop (DLL) for generating an internal clock signal.

In general, a semiconductor memory device operating in synchronization with a clock signal such as a synchronous semiconductor memory device includes an internal clock generator for receiving an external clock signal and generating an internal clock signal. Therefore, the data input / output operation of the synchronous semiconductor memory device is performed in synchronization with the internal clock signal. A typical circuit for generating such an internal clock signal is a DLL. 1 is a block diagram schematically illustrating a conventional DLL and an output buffer of a semiconductor memory device. Referring to FIG. 1, the DLL 10 includes a clock receiver 11, a phase detector 12, an up-down counter 13, a delay circuit 14, and a replica delay unit. And (15). In addition, the delay circuit unit 14 includes a plurality of unit delay units 15 connected in series. The output buffer 20 receives the internal data signal DI in synchronization with the internal clock signal INCLK received from the delay circuit 14, and outputs an output data signal DO. However, the internal clock signals INCLK 'and INCLK' 'output from the DLL 10 include jitter components, as shown in FIG. 2. In more detail, the up-down counter 13 counts up or down in synchronization with the control signal SEL_EN according to the logic state of the up-down control signal UPDN received from the phase detector 12. do. The up-down counter 13 outputs a selection signal SEL as a counting result. The selection signal SEL includes bits P1 to PK (K is an integer). Thus, when the up-down counter 13 up counts, the bit value of the selection signal SEL increases, and when the up-down counter 13 down counts, the selection signal SEL The bit value is reduced. Preferably, the up-down counter 13 counts up or down at the rising edge of the control signal SEL_EN and changes the values of the bits of the selection signal SEL. At this time, the signal path between the output terminal of the up-down counter 13 and the input terminals of the unit delay units 16 may have different magnitudes of resistance, capacitance, and power noise. There may be delay components. For example, there may be a case where the delay component present in the signal paths through which the bits P1 to P (K-1) pass is smaller than the signal path through which the bit PK passes. In this case, as shown in FIG. 2, the time point at which the bits P1 to P (K-1) are input to the corresponding unit delay units 16 is a unit delay unit to which the bit PK corresponds. It is faster than the point of time entered in (16). As described above, when the bits P1 to PK are respectively input to the corresponding unit delay units 16, the unit delay units 16 may operate unstable. As a result, the delay signals DECKL and DC1 to DC1 input to the unit delay units 16 during the time C1 or C2 when the up-down counter 13 changes the bit value of the selection signal SEL. When DC (K-1)) transitions from 'high' to 'low' or from 'low' to 'high', the output signals of the unit delay units 16 include jitter components. Referring to FIG. 2, the delay signal DC (K−1 ′ ′) input to the unit delay unit 16 disposed at the final output terminal is shifted in the change periods C1 and C2, and as a result, the unit. It can be seen that jitters G1 and G2 are generated in the internal clock signal INCLK 'output from the delay unit 16. However, when the delay signal DC (K-1) that does not transition in the change periods C1 and C2 is input to the unit delay unit 16, the internal clock signal INCLK includes a jitter component. I never do that. This jitter generation problem of the internal clock signal occurs more seriously when the frequency of the external clock signal EXCLK input to the DLL 10 increases. In addition, when the internal clock signal INCLK includes a jitter component, it glitches the output data signal DO output from the output buffer 20 operating in synchronization with the internal clock signal INCLK. There is a problem that the sex noise components G3 and G4 are included.

Accordingly, a technical problem of the present invention is to control the output signal of the up-down counter to be output in synchronization with the falling edge of the previous internal clock signal, thereby generating an internal clock signal with reduced jitter components. Is to provide a DLL.

A DLL according to the present invention for achieving the above technical problem includes a clock receiver, a phase detector, an up-down counter, an output control circuit, and a clock delay circuit. The clock receiver receives an external clock signal and outputs a delayed clock signal. The phase detector detects the phase difference between the delayed clock signal and the reference clock signal, and outputs a detection signal in accordance with the detection result. The up-down counter, in response to the detection signal and the counting control signal, up or down counts and outputs a first selection control signal based on the accumulated counting value. The output control circuit receives the first selection control signal and outputs the second selection control signal in synchronization with the J-1 (J is an integer) internal clock signal. The clock delay circuit delays the delayed clock signal for a delay time adjusted in response to the second selection control signal and outputs a Jth internal clock signal. Preferably, the J-1th internal clock signal is earlier in time than the Jth internal clock signal.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information.

3 is a block diagram schematically illustrating a DLL and an output buffer of a semiconductor memory device according to an embodiment of the present invention. Referring to FIG. 3, the DLL 100 includes a clock receiver 110, a phase detector 120, an up-down counter 130, an output control circuit 140, a clock delay circuit 150, and a replica delay unit. 160. The clock receiver 110 receives an external clock signal ECLK and outputs a delayed clock signal DCLK. Preferably, the delayed clock signal DCLK is a signal in which the external clock signal ECLK is delayed for a predetermined time by the clock receiver 110. The phase detector 120 detects a phase difference between the delayed clock signal DCLK and the reference clock signal REFCLK and outputs a detection signal UDZ according to the detection result. The up-down counter 130 counts up or down in response to the detection signal UDZ and the counting control signal SEN, and outputs a first selection control signal ISEL based on the accumulated counting value. do. Preferably, the first selection control signal ISEL includes first to Nth bits (N is an integer) bits S1 to SN. Further, when the up-down counter 130 up counts, the bit value of the first selection control signal ISEL is increased, and when the up-down counter 130 down counts, the first selection. The bit value of the control signal ISEL is reduced. In more detail, as shown in FIG. 6, the counting control signal SEN is a signal that is periodically toggled. In addition, the up-down counter 130 performs the first selection control by counting up in synchronization with a rising edge of the counting control signal SEN while the detection signal UDZ is in an enabled state. Increment the bit value of the signal ISEL. In addition, the up-down counter 130 down counts in synchronization with the rising edge of the counting control signal SEN while the detection signal UDZ is in a disabled state, thereby performing the first selection control signal ISEL. Decreases the bit value of

The output control circuit 140 synchronizes the first selection control signal in synchronization with a J-1 (J is an integer) internal clock signal (that is, a post internal clock signal) (ICLK (J-1)). (ISEL) is received, and the second selection control signal FSEL is output. More specifically, the output control circuit 140 is synchronized with the falling edge of the J-1 internal clock signal ICLK (J-1), so that the second selection control signal FSEL is synchronized. Outputs Preferably, the second selection control signal FSEL also includes first to Nth bits B1 to BN similarly to the first selection control signal ISEL. Substantially, the second selection control signal FSEL is a time when the first selection control signal ISEL is set by the output control circuit 140 (for example, the J-1 internal clock signal ICLK ( Signal delayed for 1/2 clock cycle) of J-1)). As a result, when the bit value of the first selection control signal ISEL increases, the bit value of the second selection control signal FSEL also increases, and the bit value of the first selection control signal ISEL decreases. At this time, the bit value of the second selection control signal FSEL is also reduced.

The clock delay circuit 150 includes first to Nth unit delay circuits UD1 to UDN (N is an integer) connected in series. The clock delay circuit 150 delays the delay clock signal DCLK during a delay time adjusted in response to the second selection control signal FSEL and outputs a J-th internal clock signal ICLKJ. Preferably, the J-th internal clock signal ICLK (J-1) is earlier in time than the J-th internal clock signal ICLKJ.

The first to Nth unit delay circuits UD1 to UDN receive the first to Nth bits B1 to BN of the second selection control signal FSEL by one bit, respectively, and receive the delay. Further receives a clock signal DCLK. For example, the first unit delay circuit UD1 receives the first bit B1 and the delay clock signal DCLK. In addition, the first unit delay circuit UD1 is enabled in response to the enable control signal ETL. Preferably, the enable control signal ETL is maintained at the voltage VDD level. Each of the first to Nth unit delay circuits UD1 to UDN includes a NAND gate 151 and a delay unit 152. The NAND gate 151 outputs a logic signal (one of L1 to LN) in response to a corresponding one of the delayed clock signal DCLK and the first to Nth bits B1 to BN. More specifically, when the corresponding one of the first to Nth bits B1 to BN is enabled (that is, logic '1'), the synchronization is performed in synchronization with the delay clock signal DCLK. Toggles the logic signal (one of L1 to LN). In addition, when the corresponding one of the first to Nth bits B1 to BN is disabled (that is, logic '0'), the logic is independent of the logic state of the delay clock signal DCLK. Keep signal (one of L1-LN) in an enabled state (ie, a logic 'high' state).

The delay units 152 of the first to Nth unit delay circuits UD1 to UDN are connected in series. The delay unit 152 of the first unit delay circuit UD1 includes the enable control signal ETL received through an enable terminal en and the logic signal L1 received through an input terminal in. In response to the delay signal CK1 is output to the output terminal out. More specifically, when the logic signal L1 is toggled, the delay unit 152 of the first unit delay circuit UD1 toggles the delay signal CK1. In addition, when the logic signal L1 is maintained in an enabled state, the delay unit 152 of the first unit delay circuit UD1 may enable the delay signal CK1 (ie, logic 'high'). State). In addition, the delay units 152 of the second to Nth unit delay circuits UD2 to UDN respectively include the first to Nth unit delay circuits UD1 to UD (N-1). Delay signals CK1 to CK (N-1) are received from the delay unit 152. For example, the delay unit 152 of the second unit delay circuit UD2 receives the delay signal CK1. In addition, the N-th unit delay circuit UDN responds to the delay signal CK (N-1) and the logic signal LN, and thus, the J-th internal clock signal ICLK (J-1). ) Or the J-th internal clock signal ICLKJ is output.

The delay unit 152 of the second to Nth unit delay circuits UD2 to UDN operates similarly to the first unit delay circuit UD1. For example, the delay unit 152 of the second unit delay circuit UD2 may receive the delay signal CK1 received through an enable terminal en and the logic signal received through an input terminal in. In response to L1, the delay signal CK2 is output to the output terminal out. More specifically, when one of the logic signal L1 and the delay signal CK1 is toggled, the delay unit 152 of the second unit delay circuit UD2 causes the delay signal CK2. Toggle In addition, when both the delay signal CK1 and the logic signal L1 are kept in an enabled state, the delay unit 152 of the second unit delay circuit UD2 receives the delay signal CK2. Keep it in the enabled state (that is, logic 'high' state). Here, referring to FIG. 5, the configuration and specific operation of the delay unit 152 will be described in detail. The delay unit 152 includes an input driver circuit 181 and an output driver circuit 182. The input driver circuit 181 includes PMOS transistors PM1 and PM2 and NMOS transistors NM1 and NM2. The voltage VDD is input to the sources of the PMOS transistors PM1 and PM2, and the drains thereof are connected to the node D1. A drain of the NMOS transistor NM1 is connected to the node D1, a source thereof is connected to a drain of the NMOS transistor NM2, and a ground voltage VSS is input to a source of the NMOS transistor NM2. . Gates of the PMOS transistor PM1 and the NMOS transistor NM1 are connected to an enable terminal en, and gates of the PMOS transistor PM2 and the NMOS transistor NM2 are connected to an input terminal in. do. In response to one of the enable control signal ETL or the delay signals CK1 to CK (N-1) input to the enable terminal en, the PMOS transistor PM1 and the NMOS transistor ( NM1) is turned on or off. Preferably, when the PMOS transistor PM1 is turned on, the NMOS transistor NM1 is turned off. In addition, the PMOS transistor PM2 and the NMOS transistor NM2 are turned on or off in response to the logic signals L1 to LN input to the input terminal in. Preferably, when the PMOS transistor PM2 is turned on, the NMOS transistor NM2 is turned off. As a result, when one or both of the PMOS transistors PM1 and PM2 are turned on and one or both of the NMOS transistors NM1 and NM2 are turned off, the inside of the logic high at the node D1 is turned off. The signal IL is generated. On the contrary, when one or both of the NMOS transistors NM1 and NM2 are turned on and one or both of the PMOS transistors PM1 and PM2 are turned off, the inside of the logic row at the node D1 is turned off. The signal IL is generated.

Any one of a signal (ECTL or CK1 to CK (N-1)) input to the enable terminal en and a signal (one of L1 to LN) input to the input terminal in are toggled. When the other remains enabled, the internal signal IL is toggled. In addition, both the signal (ECTL or CK1 to CK (N-1)) input to the enable terminal en and the signal (one of L1 to LN) input to the input terminal in are enabled. When kept at, the internal signal IL is held low.

The output driver circuit 182 includes PMOS transistors PM3 and PM4 and NMOS transistors NM3 and NM4. The voltage VDD is input to the sources of the PMOS transistors PM3 and PM4, and the drains thereof are connected to the node D2. A drain of the NMOS transistor NM3 is connected to the node D2, a source thereof is connected to a drain of the NMOS transistor NM4, and a ground voltage VSS is input to a source of the NMOS transistor NM4. . The internal signal IL is input to gates of the PMOS transistor PM3 and the NMOS transistor NM3, and the voltage VDD is applied to gates of the PMOS transistor PM4 and the NMOS transistor NM4. Is entered. In response to the internal signal IL, the PMOS transistor PM3 and the NMOS transistor NM3 are turned on or off. Preferably, when the PMOS transistor PM3 is turned on, the NMOS transistor NM3 is turned off. In addition, in response to the voltage VDD, the PMOS transistor PM4 is turned off and the NMOS transistor NM4 is turned on.

As a result, when the PMOS transistor PM3 is turned on and the NMOS transistors NM3 are turned off, a logic high output signal out is generated at the node D2. In contrast, when the PMOS transistor PM3 is turned off and the NMOS transistor NM3 is turned on, a logic low output signal out is generated at the node D2.

As a result, the delay time of the clock delay circuit 150 increases when the number of unit delay circuits outputting the delayed signal among the first to Nth unit delay circuits UD1 to UDN increases. On the contrary, when the number of unit delay circuits outputting the delayed signal among the first to Nth unit delay circuits UD1 to UDN decreases, the delay time of the clock delay circuit 150 decreases. Here, when the bit value of the second selection control signal FSEL increases, the number of unit delay circuits outputting the delayed delay signal increases, and the bit value of the second selection control signal FSEL decreases. When the number of unit delay circuits outputting a delayed delay signal is reduced. The replica delay unit 160 delays the J-1 th internal clock signal ICLK (J-1) for a predetermined time and outputs the reference clock signal REFCLK.

4 is a diagram illustrating the output control circuit shown in FIG. 3 in more detail. Referring to FIG. 4, the output control circuit 140 includes first to Nth input circuits ISC1 to ISCN and the first to Nth output circuits OSC1 to OSCN. The first to Nth input circuits ISC1 to ISCN may be configured to synchronize the first selection control signal ISEL with the rising edge of the J-1 internal clock signal ICLK (J-1). The first to Nth bits S1 to SN are respectively received, and the first to Nth latch signals LAT1 to LATN are output. In more detail, each of the first to Nth input circuits ISC1 to ISCN includes a transmission circuit 141 and a latch circuit 142. The transmission circuit 141 may include the first through Nth bits S1 through N1 of the first selection control signal ISEL when the J-1 internal clock signal ICLK (J-1) is enabled. Receive and output the corresponding bit in SN). For example, the transmission circuit 141 of the first input circuit ISC1 receives the bit S1 when the J-1 internal clock signal ICLK (J-1) is enabled. Output In addition, the transmission circuit 141 may be implemented as an inverter 143 and a transmission gate 144. The latch circuit 142 latches the corresponding bit (one of S1 to SN) received from the transmission circuit 141 and transmits the latched signal to the first to Nth latch signals LAT1 to LATN. Output as one of For example, the latch circuit 142 of the first input circuit ISC1 latches the bit S1 and outputs the first latch signal LAT1. The latch circuit 142 may be implemented with inverters 145 and 146.

The first to Nth output circuits OSC1 to OSCN are synchronized with the falling edge of the J-1th internal clock signal ICLK (J-1), so that the first to Nth latch signals LAT1 to Nth. LATNs are respectively received, and the first through Nth bits B1 through BN of the second selection control signal FSEL are output. Each of the first to Nth output circuits OSC1 to OSCN includes a transmission circuit 171 and a latch circuit 172. The transmission circuit 171 receives a corresponding one of the first to Nth latch signals LAT1 to LATN when the J-1th internal clock signal ICLK (J-1) is enabled. Output For example, the transmission circuit 171 of the first output circuit OSC1 may receive the first latch signal LAT1 when the J-1 internal clock signal ICLK (J-1) is disabled. Receive and output. In addition, the transmission circuit 171 may be implemented as an inverter 173 and a transmission gate 174. The latch circuit 172 latches a corresponding latch signal (one of LAT1 to LATN) received from the transmission circuit 171 and transmits the latched signal to the first to second signals of the second selection control signal FSEL. Output as one of the Nth bits B1 to BN.

Next, referring to Figure 6, the operation of the DLL 100 in more detail as follows. For convenience of description, in FIG. 6, the first and second selection control signals ISEL and FSEL are 5 bits, respectively, and the clock delay circuit 150 includes first to fifth unit delay circuits UD1 to ˜. The case including UD5) will be described as an example.

First, the phase detector 120 detects a phase difference between the delayed clock signal DCLK and the reference clock signal REFCLK and outputs a detection signal UDZ. 6 illustrates the detection signal UDZ output by the phase detector 120 when the phase of the internal clock signal ICLKJ is to be pulled forward in time. When the phase of the internal clock signal ICLKJ is to be pulled forward in time, the phase detector 120 outputs the detection signal UDZ at a logic low level.

Since the detection signal UDZ is in a low state, the up-down counter 130 counts down every time FT1 to FT4 when the counting control signal SEN is enabled. For example, an initial counting value of the up-down counter 130 (ie, a logic value of bits S5, S4, S3, S3, and S1 of the initial first selection control signal ISEL) is' 10000. ', The up-down counter 130 counts down to the time point FT1 and changes the logic value of the bits S5, S4, S3, S3, and S1 to' 01000 '. In this case, the output control circuit 140 receives the bits S5, S4, S3, S3, and S1 having a logic value of '01000', and the falling edge of the internal clock signal ICLK1 (that is, the start point of time). In synchronization with ST1)), the bits B5, B4, B3, B2, and B1 of the second selection control signal FSEL having a logic value of '01000' are output. As a result, in response to the bit B4, the second unit delay circuit UD2 toggles the delay signal CK2. As a result, the delay clock signal DCLK must pass through the second to fifth unit delay circuits UD2 to UD5, and the delay time by the second to fifth unit delay circuits UD2 to UD5. Thereafter, the fifth unit delay circuit UD5 outputs the internal clock signal ICLK2 whose phase is earlier than the internal clock signal ICLK1.

In addition, the up-down counter 130 counts down at the time point FT1 and changes the logic value of the bits S5, S4, S3, S3, and S1 to '00100'. At this time, the output control circuit 140 receives the bits (S5, S4, S3, S3, S1), the logic of '00100' in synchronization with the falling edge (ST2) of the internal clock signal (ICLK2) The bits B5, B4, B3, B2, and B1 of the second selection control signal FSEL having a value are output. As a result, in response to the bit B3, the third unit delay circuit UD3 toggles the delay signal CK3. As a result, the delay clock signal DCLK must pass through the third to fifth unit delay circuits UD3 to UD5, and the delay time by the third to fifth unit delay circuits UD3 to UD5. Thereafter, the fifth unit delay circuit UD5 outputs the internal clock signal ICLK3 whose phase is earlier than the internal clock signal ICLK2.

As such, the DLL 100 adjusts the delay time of the clock delay circuit 150 in synchronization with the falling edge of the previous internal clock signal to generate a current internal clock signal. It is possible to prevent the unit delay circuits included in the operation from being unstable. Thus, the DLL 100 can generate a stable internal clock signal with reduced jitter components.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the DLL according to the present invention controls the output signal of the up-down counter to be output in synchronization with the falling edge of the previous internal clock signal, thereby providing a stable internal clock signal with reduced jitter component. May occur.

Further, according to the present invention, since the jitter component of the internal clock signal is reduced, the glitch noise component included in a signal output from a circuit such as a data output buffer of the semiconductor memory device operating in synchronization with the internal clock signal can be reduced. have.

Claims (10)

A clock receiver for receiving an external clock signal and outputting a delayed clock signal; A phase detector for detecting a phase difference between the delayed clock signal and a reference clock signal and outputting a detection signal according to the detection result; An up-down counter responsive to the detection signal and a counting control signal, the up-down counter outputting a first selection control signal having a bit value of 1 to N bits that is changed based on the accumulated counting value; An output control circuit for receiving the first selection control signal and outputting a second selection control signal having a bit value of 1 to N bits in synchronization with the J-1 (J is an integer) internal clock signal; And A clock delay circuit for delaying the delay clock signal for a delay time adjusted in response to the second selection control signal and outputting a J-th internal clock signal; A delay locked loop (DLL) in which the J-1th internal clock signal advances in time earlier than the Jth internal clock signal. The method of claim 1, And a replica delay unit configured to delay the J-1th internal clock signal for a predetermined time and output the reference clock signal. The method of claim 1, And the output control circuit outputs the second selection control signal in synchronization with a falling edge of the J-1 internal clock signal. The method of claim 1, The first selection control signal and the second selection control signal include first to Nth bits (where N is an integer), Bit values of the first and second selection control signals are increased when the up-down counter is up counting, and bit values of the first and second selection control signals when the up-down counter is down counting. DLLs are reduced. The method of claim 4, wherein the output control circuit, First to Nth bits respectively receiving the first to Nth bits of the first selection control signal and outputting first to Nth latch signals in synchronization with the rising edge of the J-1 internal clock signal; Input circuits; And First to Nth, respectively, receiving the first to Nth latch signals and outputting the first to Nth bits of the second selection control signal in synchronization with the falling edge of the J-1 internal clock signal. DLL containing N output circuits. The method of claim 5, wherein each of the first to Nth input circuits, A transmission circuit configured to receive and output a corresponding bit among the first to Nth bits of the first selection control signal when the J-1 internal clock signal is enabled; And And a latch circuit for latching the corresponding bit received from the transmission circuit and outputting the latched signal as one of the first to Nth latch signals. The method of claim 5, wherein each of the first to Nth output circuits, A transmission circuit configured to receive and output one of the first to Nth latch signals when the J-1 internal clock signal is disabled; And A latch circuit for latching one of the first to Nth latch signals received from the transmission circuit and outputting the latched signal as one of the first to Nth bits of the second select control signal. DLL. The method of claim 4, wherein When the bit value of the second selection control signal is increased, the delay time of the clock delay circuit is increased, and when the bit value of the second selection control signal is decreased, the delay time of the clock delay circuit is decreased. DLL. The method of claim 4, wherein The counting control signal is a signal that is periodically toggled (toggle), The up-down counter increases the bit value of the first selection control signal by up counting in synchronization with a rising edge of the counting control signal while the detection signal is in an enabled state, And while the signal is in a disabled state, down counting in synchronization with the rising edge of the counting control signal, thereby reducing the bit value of the first select control signal. The method of claim 4, wherein The clock delay circuit includes first to Nth unit delay circuits connected in series, and the first to Nth unit delay circuits each include one bit of the first to Nth bits of the second selection control signal. Each of the first to Nth unit delay circuits outputs a delayed signal that is toggled according to a received logic value of the corresponding bit, or remains enabled. Output the delay signal, When the number of unit delay circuits for outputting the toggled delay signal among the first to Nth unit delay circuits increases, the delay time increases, and the toggled delay among the first to Nth unit delay circuits is increased. The delay time decreases when the number of unit delay circuits outputting a signal decreases.

Images