CN111416619B - Time delay measuring circuit, time delay measuring method, electronic equipment and chip - Google Patents

Time delay measuring circuit, time delay measuring method, electronic equipment and chip Download PDF

Info

Publication number
CN111416619B
CN111416619B CN202010224274.4A CN202010224274A CN111416619B CN 111416619 B CN111416619 B CN 111416619B CN 202010224274 A CN202010224274 A CN 202010224274A CN 111416619 B CN111416619 B CN 111416619B
Authority
CN
China
Prior art keywords
signal
bit
delay
circuit
bit signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202010224274.4A
Other languages
Chinese (zh)
Other versions
CN111416619A (en
Inventor
杨洁
赵野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Institute of Microelectronics of CAS
Original Assignee
Institute of Microelectronics of CAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Institute of Microelectronics of CAS filed Critical Institute of Microelectronics of CAS
Priority to CN202010224274.4A priority Critical patent/CN111416619B/en
Publication of CN111416619A publication Critical patent/CN111416619A/en
Application granted granted Critical
Publication of CN111416619B publication Critical patent/CN111416619B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop

Abstract

The invention discloses a delay measuring circuit, a delay measuring method, electronic equipment and a chip, and relates to the technical field of electronic circuits, in order to realize the delay between a turnover edge of a dynamic measuring counter and a trigger edge of a main clock, so that the sampling compensation is more accurate, and the consistency between channels is ensured. The delay measurement circuit includes a logic circuit for generating a delay interval signal based on a first multi-bit signal, a second multi-bit signal, and a master clock signal; the latch circuit is used for latching the multi-phase clock signals based on the rising edge of the delay interval signal to obtain the latch values of the multi-phase clock signals; and an encoding circuit for generating a delay code between a first multi-bit signal flip edge and a rising edge of the main clock signal or a delay code between a second multi-bit signal flip edge and a falling edge of the main clock signal based on the latch value. The time delay measuring method and the time delay measuring chip are applied to time delay measurement. The delay measurement circuit is applied to electronic equipment.

Description

Delay measurement circuit, delay measurement method, electronic equipment and chip
Technical Field
The present invention relates to the field of electronic circuit technologies, and in particular, to a delay measurement circuit, a delay measurement method, an electronic device, and a chip.
Background
A Time-to-digital converter (TDC) is widely used to measure a Time difference between two input signals and output the Time difference in a digital manner. However, due to existence of non-ideal factors such as clock jitter, process, voltage, temperature (PVT), metastability, large fan-out, etc., an uncertain delay is generated between the counter of the key functional component of the time-to-digital converter and the trigger clock, which further affects the timing result of the time-to-digital converter, and reduces the linearity and precision of the time-to-digital converter.
In order to solve the above problem, a common measurement method is to perform multiple time delays on a single input signal to obtain a set of excitation signals arriving at different times, and compare the set of excitation signals to estimate the true arrival time of the input signal without delay. Since each time-to-digital converter can only process one signal, the above measurement method is not favorable for channel expansion, which not only doubles the number of channels, but also causes a sharp increase in cost. Moreover, since the high-precision time-to-digital converter is extremely sensitive to clock jitter, PVT variations, and the like, a simple calibration method is difficult to meet actual working requirements.
In the prior art, a programmable Delay (Delay) method can be adopted, a group of buffer (buffer) chains are used for interpolating the time length of more than 1 period, then an analog loop structure is used for locking the phase difference between a clock triggering edge and a counter overturning edge, and the buffer is adjusted to enable a multi-phase clock to carry out Delay with the same degree. However, this method requires a complex feedback loop, the circuit structure is complex, the occupied area is large, each channel needs to be adjusted independently, the reliability is poor, and the expansion of multiple channels is not facilitated. Furthermore, the phase difference between the lock clock trigger edge and the counter flip edge requires a long time, resulting in extremely low efficiency. And the phase difference is locked and then is not changed. However, the delay of the counter along with the clock may change due to PVT, clock jitter, etc., and the delay between the clock trigger edge and the counter flip edge cannot be updated in time.
Therefore, no matter the simple or complex measuring method is adopted, the influence of the time delay between the data turning edge and the clock triggering edge on the high-speed high-precision system is not fundamentally solved, and no measuring method aiming at the high-speed high-precision system, which is simple, efficient, low in cost and not influenced by non-ideal factors such as PVT, exists at present.
Disclosure of Invention
The invention aims to provide a delay measuring circuit, which can dynamically measure the uncertain delay between the data turning edge of a first multi-bit signal or a second multi-bit signal and the triggering edge of a main clock signal, so that the sampling compensation is more accurate, and the consistency among multiple channels is ensured.
In order to achieve the above object, the present invention provides a delay measurement circuit comprising a logic circuit, a latch circuit and an encoding circuit connected in this order, wherein,
the logic circuit is configured to generate a delay interval signal based on the first multi-bit signal, the second multi-bit signal, and the master clock signal; the latch circuit is configured to latch the multi-phase clock signals based on the rising edge of the delay interval signal, and obtain the latch values of the multi-phase clock signals, wherein the frequency of the master clock signal is the same as the frequency of the multi-phase clock signals; the encoding circuit is configured to generate a delay code between a first multi-bit signal flip edge and a rising edge of the master clock signal or a delay code between a second multi-bit signal flip edge and a falling edge of the master clock signal based on the latched value.
Preferably, the first multi-bit signal and the second multi-bit signal are respectively at the same frequency as the master clock signal; the first multi-bit signal and the second multi-bit signal are multi-bit Gray code counter signals with the same bit width; when the encoding circuit is configured to generate the delay code between the flip edge of the first multi-bit signal and the rising edge of the master clock signal based on the latch value, the phase of the first multi-bit signal leads the phase of the second multi-bit signal by a phase time of
Figure BDA0002427127360000031
Wherein f is the frequency of the master clock signal; when the encoding circuit is configured to generate the delay code between the inverted edge of the second multi-bit signal and the falling edge of the master clock signal based on the latched value, the phase of the first multi-bit signal lags behind the phase of the second multi-bit signal by a phase time of
Figure BDA0002427127360000032
Where f is the frequency of the master clock signal.
Preferably, the logic circuit comprises a delay signal generating circuit, an enable signal generating circuit, and a first gate circuit connected to an output of the delay signal generating circuit and an output of the enable signal generating circuit, respectively, wherein the delay signal generating circuit is configured to generate the delay signal based on the first multi-bit signal and the second multi-bit signal; the enable signal generation circuit is configured to generate an enable signal based on the master clock signal; the first gate circuit is configured to generate a delay interval signal by performing an and operation on the delay signal and the enable signal.
Preferably, the delay signal generating circuit comprises a third gate circuit and at least two second gate circuits, and the output ends of the at least two second gate circuits are connected with the input end of the third gate circuit; at least two second gate circuits configured to generate a third multi-bit signal by performing an exclusive-or operation on the first multi-bit signal and the second multi-bit signal; the third gate circuit is configured to generate the time-delayed signal by performing an or operation on each bit signal of the third multi-bit signal.
Preferably, the enable signal generating circuitComprises a first timing circuit and a fourth gate circuit connected in sequence, wherein when the phase of the first multi-bit signal is advanced by the phase of the second multi-bit signal by a time of
Figure BDA0002427127360000033
The first timing circuit is configured to trigger to output a fourth multi-bit signal according to a rising edge of the master clock signal, wherein f is the frequency of the master clock signal; when the phase of the first multi-bit signal lags behind the phase of the second multi-bit signal by a time of
Figure BDA0002427127360000041
The first timing circuit is configured to trigger to output a fourth multi-bit signal according to a falling edge of the master clock signal, wherein f is the frequency of the master clock signal; the fourth gate circuit is configured to generate an enable signal by performing an and operation on each bit signal of the fourth multi-bit signal.
Preferably, the enable signal generating circuit further includes a fifth gate circuit configured to delay the interval signal by delaying the enable signal
Figure BDA0002427127360000042
The high level of the periodic pulse width is continuously extracted by an enable signal, wherein f is the frequency of the master clock signal.
Preferably, the first timing circuit is an m-bit counter, where m is a natural number greater than or equal to 2.
Preferably, the delay measuring circuit further comprises a calibration circuit, and the calibration circuit is used for controlling the encoding circuit to output the delay code.
Preferably, the multi-phase clock signal is 2 k Bit clock signals in which any adjacent single bit signals have a phase difference of
Figure BDA0002427127360000043
Where k is a natural number greater than or equal to 1 and f is the frequency of the master clock signal.
Compared with the prior art, the delay measuring circuit provided by the invention comprises a logic circuit, a latch circuit and an encoding circuit which are sequentially connected. And converting the time delay between the turnover edge of the first multi-bit signal and the rising edge of the main clock signal or between the turnover edge of the second multi-bit signal and the falling edge of the main clock signal into the rising edge information of the time delay interval signal through a logic circuit. When the rising edge of the delay interval signal output by the logic circuit arrives, the latch circuit latches the instantaneous level of the multi-phase clock signal, and the delay code between the first multi-bit signal turning edge and the rising edge of the main clock signal or between the second multi-bit signal turning edge and the falling edge of the main clock signal is obtained according to a plurality of instantaneous level information of the latched multi-phase clock signal. The latch circuit latches the multi-phase clock signals according to the rising edge of the delay interval signal to obtain the delay codes corresponding to the delay interval signal. The delay code of the present invention is dynamically changed according to the input first and second multi-bit signals. Although there is an indeterminate delay between the data flip edge of the first multi-bit signal or the second multi-bit signal and the trigger edge of the master clock signal in the prior art due to the influence of clock jitter, PVT, and other non-ideal factors. But through the technical scheme of the delay measuring circuit, uncertain delay between the data turning edge of the first multi-bit signal or the second multi-bit signal and the triggering edge of the main clock signal can be dynamically obtained, and compared with the condition that the phase difference is locked by a phase-locked loop and then is fixed, the delay can be dynamically fed back, so that the subsequent sampling compensation is more accurate, the consistency among multiple channels can be ensured, and the influence of any non-ideal factor is avoided. Compared with other slow latching processes, the multi-phase clock signal can be latched as long as the rising edge of the delay interval signal arrives at the latch, and the delay code is obtained by using the coding circuit according to the latching value, so that the method is fast and efficient, and the measurement of the delay code is accurate. Compared with a complex analog circuit with multiple parasitic effects, the digital circuit design is adopted, and the structure is simple.
The invention also provides a time delay measuring method, which comprises the following steps: generating a delay interval signal based on the first multi-bit signal, the second multi-bit signal and the master clock signal; latching the multi-phase clock signals based on the rising edge of the delay interval signal to obtain a latched value of the multi-phase clock signals, wherein the frequency of the main clock signal is the same as that of the multi-phase clock signals; a delay code between a first multi-bit signal flip edge and a rising edge of the master clock signal is generated based on the latched value, or a delay code between a second multi-bit signal flip edge and a falling edge of the master clock signal is generated.
Preferably, the first and second multi-bit signals have the same frequency as the master clock signal, respectively, and are multi-bit gray code counter signals having the same bit width, and when the delay code between the inversion edge of the first multi-bit signal and the rising edge of the master clock signal is generated based on the latch value, the phase of the first multi-bit signal is advanced by the phase time of the second multi-bit signal by
Figure BDA0002427127360000061
Wherein f is the frequency of the master clock signal; when generating a delay code between a flip edge of the second multi-bit signal and a falling edge of the master clock signal based on the latched value, the phase of the first multi-bit signal lags behind the phase of the second multi-bit signal by a phase time of
Figure BDA0002427127360000062
Where f is the frequency of the master clock signal.
Preferably, generating the delay interval signal based on the first multi-bit signal, the second multi-bit signal and the master clock signal comprises: generating a delayed signal based on the first multi-bit signal and the second multi-bit signal; generating an enable signal based on a master clock signal; and operation is performed on the delay signal and the enable signal to generate a delay interval signal.
Preferably, generating the delayed signal based on the first multi-bit signal and the second multi-bit signal comprises: performing an exclusive-or operation on the first multi-bit signal and the second multi-bit signal to generate a third multi-bit signal; performing an or operation on each bit signal of the third multi-bit signal generates a delayed signal.
Preferably, generating the enable signal based on the master clock signal comprises: when the phase of the first multi-bit signal leadsThe phase time of the two multi-bit signal is
Figure BDA0002427127360000063
Triggering the first timing circuit to output a fourth multi-bit signal according to the rising edge of the main clock signal, wherein f is the frequency of the main clock signal; when the phase of the first multi-bit signal lags behind the phase of the second multi-bit signal by a time of
Figure BDA0002427127360000064
Triggering the first timing circuit to output a fourth multi-bit signal according to the falling edge of the master clock signal, wherein f is the frequency of the master clock signal; and operation is performed on each bit signal of the fourth multi-bit signal to generate an enable signal.
Preferably, after performing and operation on each bit signal of the fourth signal to generate the enable signal, delaying the enable signal such that the interval signal is delayed
Figure BDA0002427127360000071
The high level of the periodic pulse width is continuously extracted by an enable signal, wherein f is the frequency of the master clock signal.
Preferably, the first timing circuit is an m-bit counter, where m is a natural number greater than or equal to 2.
Preferably, generating the delay code preamble between the flip edge of the first multi-bit signal and the rising edge of the master clock signal or between the flip edge of the second multi-bit signal and the falling edge of the master clock signal based on the latched value further comprises calibrating the delay code.
Preferably, the multi-phase clock signal is 2 k Bit clock signals in which any adjacent single bit signals have a phase difference of
Figure BDA0002427127360000072
Where k is a natural number greater than or equal to 1 and f is the frequency of the master clock signal.
Compared with the prior art, the beneficial effects of the delay measurement method provided by the invention are the same as those of the delay measurement circuit provided by the technical scheme, and are not repeated herein.
The invention also provides electronic equipment which comprises the delay measuring circuit provided by the technical scheme.
Compared with the prior art, the electronic device provided by the invention has the same beneficial effects as the delay measuring circuit provided by the technical scheme, and the details are not repeated herein.
The invention also provides a chip, wherein the chip is stored with instructions, and when the instructions are operated, the time delay measuring method provided by the technical scheme is executed.
Compared with the prior art, the beneficial effects of the chip provided by the invention are the same as those of the time delay measuring method provided by the technical scheme, and the details are not repeated herein.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and do not limit the invention. In the drawings:
fig. 1 shows a circuit diagram of a prior art scenario for generating and applying a delay signal;
FIG. 2 shows a timing diagram of the signals shown in FIG. 1 provided by the prior art;
FIG. 3 is a block diagram of a delay measurement circuit according to an embodiment of the present invention;
FIG. 4 is a circuit diagram of a first multi-bit signal according to an embodiment of the present invention;
FIG. 5 is a circuit diagram for generating a second multi-bit signal according to an embodiment of the present invention;
FIG. 6 is a circuit diagram of a logic circuit provided by an embodiment of the present invention;
FIG. 7 is a circuit diagram of a single latch in the latch circuit according to the embodiment of the present invention;
FIG. 8 is a timing diagram of signals established according to a delay measurement circuit according to an embodiment of the present invention;
fig. 9 is a flowchart of a delay measurement method according to an embodiment of the present invention.
The circuit comprises a logic circuit 1, a delay signal generating circuit 10, a second gate circuit 110, a third gate circuit 120, a third gate circuit 20, an enable signal generating circuit 210, a first timing circuit 220, a fourth gate circuit 230, a fifth gate circuit 2201, a buffer 30, a first gate circuit 2, a latch circuit 200, a latch 2001, a sensitive amplifier 2002.SR latch 3, a coding circuit 4, a calibration circuit 510, a first counter 520, a second counter 1001, a first D trigger 1002 and a second D trigger.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 1 shows a circuit diagram of a generation and application scenario of a delay signal provided by the prior art. As shown in FIG. 1, clock CLK1 toggles first D flip-flop 1001 to generate first signal CNT1[ N:0], where first signal CNT1[ N:0] is a multi-bit signal. The rising edge of the asynchronous clock CLK2 triggers the second D flip-flop 1002 to sample the first signal CNT1[ N:0]. Ideally, second D flip-flop 1002 should sample to a stable first signal CNT1[ N:0]. However, due to the insertion of the buffer 2201 chain, the second signal CNT2[ N:0] actually sampled by the second D flip-flop 1002 will deviate from the original first signal CNT1[ N:0]. Since the second signal CNT2[ N:0] is obtained after the original first signal CNT1[ N:0] is delayed by the buffer 2201 chain, the second signal CNT2[ N:0] is also a multi-bit signal, wherein N is a natural number greater than or equal to 1.
Furthermore, due to the existence of non-ideal factors such as clock jitter, process, voltage, temperature (PVT), metastable state, large fan-out, etc. in the high-speed high-precision circuit system, the delay between the second signal CNT2[ N:0] obtained through the buffer 2201 chain and the original first signal CNT1[ N:0] is not fixed, where N is a natural number greater than or equal to 1.
Fig. 2 shows a timing diagram of the signals shown in fig. 1 provided by the prior art. As shown in FIG. 2, the first region A is a metastable region, the second region B is a stable region, and an indeterminate delay t exists between the first signal CNT1[ N:0] and the second signal CNT2[ N:0] due to the chain of the buffer 2201, wherein N is a natural number greater than or equal to 1.
As will be appreciated by the background, asynchronous clock CLK2 can be delayed to an equal degree by inserting and adjusting the number of buffers 2201 before asynchronous clock CLK 2. However, this method requires a complex feedback loop, the circuit structure is complex, the occupied area is large, each channel needs to be adjusted independently, the reliability is poor, and the expansion of multiple channels is not facilitated. And it takes a long time to lock the phase difference between the second signal CNT2[ N:0] flip edge and the first signal CNT1[ N:0] flip edge, resulting in extremely low efficiency. And the phase difference is locked and then is not changed. So that the dynamic delay between the transition edges of the second signal CNT2[ N:0] and the first signal CNT1[ N:0] cannot be updated in time. The above method does not fundamentally solve the influence of the delay between the second signal CNT2[ N:0] and the first signal CNT1[ N:0] on the high-speed high-precision system, where N is a natural number greater than or equal to 1.
In view of the foregoing problems, an embodiment of the present invention provides a delay measurement circuit, and fig. 3 shows a block diagram of the delay measurement circuit provided in the embodiment of the present invention.
As shown in fig. 3, the delay measuring circuit includes a logic circuit 1, a latch circuit 2, and an encoding circuit 3, which are connected in sequence. Wherein the first multi-bit signal PCNT [ n-1]Second multi-bit signal NCNT [ n-1]And a master clock signal f PLL The delay interval signal P _ Dly is output through the logic operation of the logic circuit 1, where n is a natural number greater than or equal to 2. It should be understood that the delay interval signal P _ Dly may be a first multi-bit signal PCNT [ n-1]And a master clock signal f PLL The delay between the first multi-bit signal NCNT [ n-1]And a master clock signal f PLL The delay between them. For example, the delay interval signal P _ Dly may be the first multi-bit signal PCNT [ n-1]Flip edge and mainClock signal f PLL The delay between rising edges may also be a delay for the second multi-bit signal NCNT [ n-1]The flip edge and the master clock signal f PLL The delay between the falling edges may also be a delay of other phases, and is not limited in this respect.
As shown in FIG. 3, the latch circuit 2 is triggered to latch the multiphase clock signal F [2 ] by the rising edge of the delay interval signal P _ Dly k -1:0]Latching is performed, wherein k is a natural number greater than or equal to 1, that is, at the time of the rising edge of the delay interval signal P _ DYy, the latch circuit 2 latches the multiphase clock signal F [2 ] k -1:0]Is latched to obtain a multi-phase clock signal F2 k -1:0]The latched value of (1). It will be appreciated that the latch circuit 2 latches the multi-phase clock signal F2 k -1:0]At the instant of the rising edge of the delay interval signal P _ Dly, a plurality of instantaneous levels, for example: multiphase clock signal F2 k -1:0]Is 2 k Bit, then obtain 2 k And (c) instantaneous level values, wherein k is a natural number greater than or equal to 1.
As shown in FIG. 3, the latch circuit 2 obtains a multi-phase clock signal F [2 ] k -1:0]Since each of the plurality of instantaneous levels corresponds to a binary code of 0 or 1, the plurality of instantaneous levels correspond to a string of binary codes of 0 or 1. The latch circuit 2 thus latches the multiphase clock signal F2 k -1:0]A plurality of momentary binary codes. The delay codes corresponding to the plurality of instantaneous binary codes latched by the latch circuit 2 are found by the encoding circuit 3. For example, the plurality of transient binary codes is 0011111111000000, and the corresponding delay code is 13.
Based on the technical scheme of the delay measurement circuit, the delay between the first multi-bit signal turning edge and the rising edge of the main clock signal or the delay between the second multi-bit signal turning edge and the falling edge of the main clock signal is converted into the rising edge information of the delay interval signal through the logic circuit. When the rising edge of the delay interval signal comes, the latch circuit latches the instantaneous level of the multi-phase clock signal, and obtains the delay code between the first multi-bit signal turning edge and the rising edge of the main clock signal or between the second multi-bit signal turning edge and the falling edge of the main clock signal according to the binary codes of a plurality of instantaneous levels of the latched multi-phase clock signal. The latch circuit latches the multi-phase clock signals according to the rising edge of the delay interval signal to obtain the delay codes corresponding to the delay interval signal. The delay code of the present invention is dynamically varied according to the input first multi-bit signal and the second multi-bit signal. Although there is an indeterminate delay t between the data flip edge of the first multi-bit signal or the second multi-bit signal and the trigger edge of the master clock signal due to the effects of clock jitter, PVT, and other non-ideal factors. But through the technical scheme of the delay measuring circuit, uncertain delay between the data turning edge of the first multi-bit signal or the second multi-bit signal and the triggering edge of the main clock signal can be dynamically obtained, compared with the condition that the phase difference is locked by a phase-locked loop and then is fixed, the delay can be dynamically fed back, the sampling compensation is more accurate, the consistency among multiple channels can be ensured, and the influence of non-ideal factors is not easily caused. Compared with other slow latching processes, the multi-phase clock signal can be latched as long as the rising edge of the delay interval signal arrives at the latching circuit, the delay code is obtained by the coding circuit according to the latching value, the method is fast and efficient, and delay measurement is accurate. Compared with a complex analog circuit with multiple parasitic effects, the digital circuit design is adopted, and the structure is simple.
As a possible implementation manner, fig. 4 shows a circuit diagram for generating a first multi-bit signal provided by an embodiment of the present invention, and fig. 5 shows a circuit diagram for generating a second multi-bit signal provided by an embodiment of the present invention.
As shown in fig. 4-5, the master clock signal f PLL The single-channel counter signals are respectively output after passing through the first counter 510 and the second counter 520, and because the single-channel counter signals have limited driving capability and a large number of channels, the single-channel counter signals need to be respectively driven by a plurality of buffers 2201 in an increasing manner, and simultaneously, the single-channel counter signals are respectively expanded into a plurality of output signals through a buffer tree composed of the buffers 2201 so as to be sampled by a plurality of channels.
Specifically, as shown in fig. 4, the master clock signal f PLL Passes through the first counter 510 and then outputsThe one-way counter signal, for example, the first counter 510 may be an n-bit gray code counter, where n is a natural number greater than 1, such as an 11-bit gray code counter. The one-way counter signal passes through a buffer tree composed of buffers 2201 and then outputs at least two first signals PCNT [ n-1]. It should be understood that outputting the first multi-bit signal PCNT [ n-1]Is related to the number of buffers 2201 and the buffer tree, such as the number of output 8 first multi-bit signals PCNT [ n-1]Of course, other numbers of first multi-bit signals PCNT [ n-1]。
Illustratively, as shown in fig. 4, if the first counter 510 is an n-bit gray code counter, the first multi-bit signal PCNT [ n-1]Is an n-bit gray code counter signal where n is a natural number greater than 1, and may be, for example, an 11-bit gray code counter signal. Since the first multi-bit signal PCNT [ n-1]Is by a master clock signal f PLL Triggers the gray code counter to get, so that the first multi-bit signal PCNT [ n-1]And a master clock signal f PLL The frequencies are the same. It should be understood that when measuring the first multi-bit signal PCNT [ n-1]The flip edge and the master clock signal f PLL Delay code between rising edges, first multi-bit signal PCNT [ n-1]Phase-advanced second multi-bit signal NCNT [ n-1]The time of the phase is
Figure BDA0002427127360000131
Where f is the frequency of the master clock signal.
Specifically, as shown in fig. 5, the circuit configurations of fig. 5 and fig. 4 are identical, and only the differences between fig. 5 and fig. 4 are described herein, if the second counter 520 is an n-bit gray code counter, the second multi-bit signal NCNT [ n-1]For an n-bit gray code counter signal, where n is a natural number greater than 1, for example, an 11-bit gray code counter signal may be used. First multi-bit signal PCNT [ n-1]And the second multi-bit signal NCNT [ n-1A signal from a device. Since the second multi-bit signal NCNT [ n-1]By means of a master clock signal f PLL Triggered gray code counter, so that second multi-bit signal NCNT [ n-1]And a master clock signal f PLL The frequencies are the same, it being understood that when measuring the second multi-bit signal NCNT [ n-1]The flip edge and the master clock signal f PLL In the time of the delay code between rising edges, the first multi-bit signal PCNT [ n-1]Phase-delayed second multi-bit signal NCNT [ n-1]The time of the phase is
Figure BDA0002427127360000132
Where f is the frequency of the master clock signal.
Fig. 6 shows a circuit diagram of a logic circuit provided in an embodiment of the present invention as a possible implementation method. Fig. 8 shows a timing diagram of signals established according to a delay measurement circuit provided by an embodiment of the invention. As shown in fig. 6, the logic circuit 1 includes a delayed signal generating circuit 10, an enable signal generating circuit 20, and a first gate circuit 30 connected to an output terminal of the delayed signal generating circuit 10 and an output terminal of the enable signal generating circuit 20, respectively.
As shown in fig. 6, the delay signal generating circuit 10 is configured to generate a delay signal according to a first multi-bit signal PCNT [ n-1]And a second multi-bit signal NCNT [ n-1]The delay signal P _ Dly _ Tmp is extracted, it being understood that the delay signal P _ Dly _ Tmp may be a first multi-bit signal PCNT [ n-1]Flip edge and master clock signal f PLL The delay between rising edges may also be the delay between the second multi-bit signal NCNT [ n-1]Flip edge and master clock signal f PLL The delay between falling edges. The enable signal generating circuit 20 is used for generating a master clock signal f PLL The enable signal En is output. The delay signal P _ Dly _ Tmp and the enable signal En are anded by the first gate circuit 30 to output the delay interval signal P _ Dly. It should be understood that the delay interval signal P _ Dly occurs every several master clock cycles.
Specifically, as shown in fig. 6, the delayed signal generating circuit 10 includes a third gate circuit 120 and at least two second gate circuits 110, and output terminals of the at least two second gate circuits 110 are connected to input terminals of the third gate circuit 120. The first multi-bit signal PCNT [ n-1 ] and the second multi-bit signal NCNT [ n-1 ] are input to at least two second gate circuits, respectively, and since the first multi-bit signal PCNT [ n-1 ] and the second multi-bit signal NCNT [ n-1 ] are n-bit gray code counter signals, n second gate circuits 110 are required, where n is a natural number greater than 1. Each bit gray code counter signal of the first multi-bit signal PCNT [ n-1 ] and the second multi-bit signal NCNT [ n-1 ] is exclusive-ored by a second gate circuit 110 to generate a bit signal corresponding to the third signal PNT [ n-1 ]. The third multi-bit signal PNT [ n-1 ] obtained by exclusive-oring each bit gray code counter signal of the first multi-bit signal PCNT [ n-1 ] and the second multi-bit signal NCNT [ n-1 ] by the second gate circuit 110 is also an n-bit gray code counter signal, and each bit signal of the third multi-bit signal PNT [ n-1 ] is or-operated by the third gate circuit 120 to obtain the delay signal P _ Dly _ Tmp _. The first multi-bit signal PCNT [ n-1 ] and the second multi-bit signal NCNT [ n-1 ] are preliminarily extracted by logical operations of n second gate circuits 110 and a third gate circuit 120, respectively, to obtain the delay signal P _ Dly _ Tmp _.
Illustratively, as shown in fig. 8, the first multi-bit signal PCNT [ n-1]Phase-advanced second multi-bit signal NCNT [ n-1]Has a phase time of
Figure BDA0002427127360000151
For example, the first multi-bit signal PCNT [ n-1]The flip edge and the master clock signal f PLL The time delay between rising edges is
Figure BDA0002427127360000152
Wherein
Figure BDA0002427127360000153
T is the master clock signal f PLL Period of (d), f is the master clock signal f PLL Of (c) is detected. According to the master clock signal f PLL First multi-bit signal PCNT [ n-1]And a second multi-bit signal NCNT [ n-1]Preliminary extraction and processing by the delay signal generating circuit 10
Figure BDA0002427127360000154
The delay of (2) is corresponding to the delay signal P _ Dly _ Tmp _.
As shown in fig. 6, the enable signal generating circuit 20 includes a first timing circuit 210, a fourth gate circuit 220, and a fifth gate circuit 230 connected in sequence. Wherein, when the first multi-bit signal PCNT [ n-1]Phase-advanced second multi-bit signal NCNT [ n-1]Has a phase time of
Figure BDA0002427127360000155
According to a master clock signal f PLL The rising edge triggers the first timing circuit 210 to output the fourth multi-bit signal Cnt [ m-1]When the first multi-bit signal PCNT [ n-1]Is delayed by the phase lag of the second multi-bit signal NCNT [ n-1]Has a phase time of
Figure BDA0002427127360000156
According to a master clock signal f PLL The falling edge triggers the first timing circuit to output the fourth multi-bit signal Cnt [ m-1]Where f is the frequency of the master clock signal and m is a natural number greater than or equal to 2.
Illustratively, the first multi-bit signal PCNT [ n-1]Phase-advanced second multi-bit signal NCNT [ n-1]Has a phase time of
Figure BDA0002427127360000157
Thus according to the master clock signal f PLL The rising edge triggers the first timing circuit 210 to output the fourth multi-bit signal Cnt [ m-1]。
Specifically, the first timing circuit 210 is an m-bit counter, where m is a natural number greater than or equal to 2. For example, it may be a 3-bit counter. Master clock signal f PLL The rising edge triggers the first timing circuit 210 to output the fourth multi-bit signal Cnt [ m-1]Since the first timing circuit 210 is an m-bit counter, the fourth multi-bit signal Cnt [ m-1]For m-bit counter signals, e.g. 3-bit counter signals, cnt [ 0] respectively]、Cnt[1]And Cnt [2 ]]. Fourth multi-bit signal Cnt [ m-1]And each bit signal thereof is anded by the fourth gate circuit 220 and an initial enable signal Cnt _ En is output, initially enabledThe enable signal Cnt _ En is delayed by the fifth gate circuit 230 and then outputs the enable signal En.
Further, as shown in fig. 6 and 8, the fifth gate 230 may include a plurality of buffers 2201, and it should be understood that the delay time is related to the number of buffers 2201. For example, if the arrival time of the rising edge of the enable signal En is not during the low level of the delay signal P _ Dly _ Tmp, the number of the buffers 2201 is increased in the fifth gate circuit 230, that is, during the low level of the delay signal P _ Dly _ Tmp by increasing the arrival time of the rising edge of the delay enable signal En. Because the delay interval signal P _ Dly can be enabled only when the rising edge of the enable signal En arrives during the low level of the delay signal P _ Dly _ Tmp
Figure BDA0002427127360000161
The high level of the periodic pulse width is extracted by the enable signal En continuously, where f is the frequency of the master clock signal, so that the rising edge of the delay interval signal P _ Dly can be obtained.
Illustratively, as shown in fig. 8, the first multi-bit signal PCNT [ n-1 ] and the second multi-bit signal NCNT [ n-1. Therefore, the rising edge of the delay interval signal P _ Dly output by the logic circuit 1 appears once through 8 main clock cycles, i.e., the delay interval signal P _ Dly is updated once through 8 main clock cycles.
Based on the technical scheme, compared with the situation that the phase difference is fixed after being locked by the phase-locked loop, and compared with other slow latching processes, the time delay code is updated once every 8 periods, so that the method and the device are quick and efficient, and the time delay code is accurately measured.
As a possible implementation manner, as shown in fig. 7 and fig. 8, after the logic circuit 1 extracts the rising edge of the interval signal P _ Dly appearing once in 8 clock cycles, the rising edge of the interval signal P _ Dly is used to trigger the latch circuit 2 to latch the multiphase clock signal F [2 ] k -1:0]Performs latch, in which the multi-phase clock signal F [2 ] k -1:0]Frequency of and master clock signal f PLL Are the same.
Illustratively, as shown in FIG. 8, the multi-phase clock signal F [2 ] k -1:0]Is 2 k Bit clock signal, multiphase clock signal F2 k -1:0]May be 2, 4, 8, 16 \8230, in which the phase difference of any adjacent single-bit signals is
Figure BDA0002427127360000171
Where k is a natural number greater than or equal to 1 and f is the frequency of the master clock signal. For example, a multi-phase clock signal F [2 ] k -1:0]May be a 16-bit clock signal, may be generated by a phase-locked loop circuit, wherein any adjacent single-bit signal is out of phase by
Figure BDA0002427127360000172
Where f is the frequency of the master clock signal.
As shown in FIGS. 7 and 8, due to the multi-phase clock signal F [2 ] k -1:0]For multi-bit clock signals, the latch circuit of FIG. 7 has only two differential inputs for a single latch, and thus, it is necessary to compare the multi-phase clock signals F [2 ] k -1:0]Latching is performed, and 2 is required in each latch circuit 2 k-1 A latch as shown in fig. 7, wherein k is a natural number equal to or greater than 1. For example, a multi-phase clock signal F2 k -1:0]Is a 16-bit clock signal, whereas the latch circuit of fig. 7 has only two differential inputs for a single latch, and therefore requires 8 latches as shown in fig. 7.
Specifically, as shown in FIGS. 7 and 8, the latch 200 includes a sense amplifier 2001 and an SR latch 2002, F [ i ], []And F [ i +2 ] k-1 ]For differential input signals, the rising edge of the delay interval signal P _ Dly triggers the SR latch 2002 to latch the differential input signal F [ i]And F [ i +2 ] k-1 ]Latch and output the latch value Dly _ Lat [ i ]]Equal to the level value of the differential input signal sampled instantaneously when the rising edge of the delay interval signal P _ DY arrives, DYY _ Lat _ N [ i [ [ i ])]Is Dly _ Lat [ i ]]Wherein i is 0 or more and 2 or less k-1 K is a natural number of 1 or more.
As shown in FIG. 8, the latch circuit 2 is triggered to latch multiple phases at the rising edge of the delay interval signal P _ DYyBit clock signal F2 k -1:0]Latching to obtain multi-phase clock signal F2 k -1:0]A plurality of instantaneous levels, i.e. a plurality of binary codes, corresponding to the rising edge of the delay interval signal P _ Dly. Illustratively, as shown in FIG. 8, a multi-phase clock signal F [2 ] k -1:0]From F [ 0]]To F [15 ]]The binary code corresponding to the instantaneous level latched by the latch circuit 2 is 0011111111000000. From the latched binary code, the corresponding delay code is found to be 13 in table 1, and the first multi-bit signal PCNT [ n-1]Flip edge and master clock signal f PLL The delay between the rising edges is between 13/16T and 14/16T, and is substantially the same as the actual 13/16T delay, because the gate circuit has a smaller delay, and the delay interval signal P _ Dly is not strictly switched at the rising edge of the counter, so the measured delay is slightly larger than the actual delay, so long as the delay is within the error range.
TABLE 1 corresponding relationship table of delay code and latch value
Figure BDA0002427127360000181
Figure BDA0002427127360000191
As a possible implementation manner, as shown in fig. 3, the delay measuring circuit further includes a calibration circuit 4, and when the output of the delay Code Dly _ Code does not coincide with the actual delay, the calibration circuit 4 needs to be used to calibrate the delay Code Dly _ Code.
Illustratively, when the output of the delay Code Dly _ Code is inconsistent with the actual delay, the adjustable control line Adjust of the calibration circuit is used to Adjust the output of the delay Code Dly _ Code in table 1. Illustratively, the calibration circuit may be an I2C module. Specifically, when the output of the delay Code Dly _ Code is inconsistent with the actual delay, the calibration circuit 4 performs an add-1 loop operation on Adjust, and adjusts the delay Code Dly _ Code from large to small, with an adjustment step size of 1. For example, if the delay Code Dly _ Code in table 1 is 13, and does not coincide with the actual delay, adjust adds 1, and the calibration circuit 4 adjusts 13 in table 1 to 12, further compares with the actual delay until finding the delay Code within the error range, and then keeps the value of the adjustable control line Adjust unchanged.
Based on the above technical solution of the calibration circuit in the delay measurement circuit, it can be known that by setting the external calibration circuit 4, the system error can be eliminated, and a more accurate delay code can be obtained.
It should be understood that the present embodiment provides a first multi-bit signal PCNT [ n-1]And the flip edge of (f) and the master clock signal f PLL Delay between rising edges, and extracting rising edges of the delay interval signal P _ Dly appearing once in 8 main clock cycles, upon arrival of the rising edges of the delay interval signal P _ Dly, the multiphase clock signal F [2 ] k -1:0]Latching is performed, and the delay Code Dly _ Code is obtained from the encoding circuit 3 based on the latched value of the binary encoding.
However, the technical solution provided by the embodiment of the present invention may also measure the second multi-bit signal NCNT [ n-1]And the flip edge of (f) and the master clock signal f PLL Delay between falling edges, when the second multi-bit signal NCNT [ n-1]And the flip edge of (f) and the master clock signal f PLL When the time delay between the falling edges occurs, the falling edge of the delay interval signal P _ Dly appearing once in 8 periods is extracted, the falling edge of the delay interval signal P _ Dly is reflected as the rising edge through the phase inverter, and when the falling edge of the delay interval signal P _ Dly comes, the rising edge output by the phase inverter is opposite to the multiphase clock signal F [2 ] k -1:0]Latching is performed, and the delay Code Dly _ Code is obtained from the encoding circuit 3 based on the latched value of the binary Code.
The embodiment of the invention also provides a time delay measuring method. As shown in fig. 9, the delay measurement method includes the following steps:
step 101, generating a delay interval signal based on the first multi-bit signal, the second multi-bit signal and the master clock signal.
And 102, latching the multi-phase clock signal based on the rising edge of the delay interval signal to obtain a latched value of the multi-phase clock signal, wherein the frequency of the main clock signal is the same as that of the multi-phase clock signal.
And 103, generating a delay code between the first multi-bit signal turning edge and the rising edge of the main clock signal or generating a delay code between the second multi-bit signal turning edge and the falling edge of the main clock signal based on the latched value.
Preferably, the first and second multi-bit signals have the same frequency as the master clock signal, respectively, and are multi-bit gray code counter signals having the same bit width, and when the delay code between the inversion edge of the first multi-bit signal and the rising edge of the master clock signal is generated based on the latch value, the phase of the first multi-bit signal is advanced by the phase time of the second multi-bit signal by
Figure BDA0002427127360000211
Wherein f is the frequency of the master clock signal; when generating a delay code between a flip edge of the second multi-bit signal and a falling edge of the master clock signal based on the latched value, the phase of the first multi-bit signal lags behind the phase of the second multi-bit signal by a phase time of
Figure BDA0002427127360000212
Where f is the frequency of the master clock signal.
Preferably, generating the delay interval signal based on the first multi-bit signal, the second multi-bit signal and the master clock signal comprises: generating a delay signal according to the first multi-bit signal and the second multi-bit signal; generating an enable signal according to a master clock signal; and operation is performed on the delay signal and the enable signal to generate a delay interval signal.
Preferably, generating the time-delayed signal from the first multi-bit signal and the second multi-bit signal comprises: performing an exclusive-or operation on the first multi-bit signal and the second multi-bit signal to generate a third multi-bit signal; performing an or operation on each bit signal of the third multi-bit signal generates a delayed signal.
Preferably, generating the enable signal from the master clock signal comprises: when the phase of the first multi-bit signal leads the phase of the second multi-bit signal by the time of
Figure BDA0002427127360000213
Triggering the first timing circuit to output a fourth multi-bit signal according to the rising edge of the main clock signal, wherein f is the frequency of the main clock signal; when the phase of the first multi-bit signal lags behind the phase of the second multi-bit signal by a time of
Figure BDA0002427127360000214
Triggering a first timing circuit according to the falling edge of the main clock signal to output a fourth multi-bit signal, wherein f is the frequency of the main clock signal; and operation is performed on each bit signal of the fourth multi-bit signal to generate an enable signal.
Preferably, after performing and operation on each bit signal of the fourth signal to generate the enable signal, delaying the enable signal such that the interval signal is delayed
Figure BDA0002427127360000221
The high level of the periodic pulse width is continuously extracted by an enable signal, wherein f is the frequency of the master clock signal.
Preferably, the first timing circuit is an m-bit counter, where m is a natural number greater than or equal to 2.
Preferably, before generating the delay code between the flip edge of the first multi-bit signal and the rising edge of the master clock signal or generating the delay code between the flip edge of the second multi-bit signal and the falling edge of the master clock signal based on the latched value, calibrating the delay code is further included.
Preferably, the multi-phase clock signal is 2 k Bit clock signals in which any adjacent single bit signals have a phase difference of
Figure BDA0002427127360000222
Wherein k is a natural number greater than or equal to 1, and f is the frequency of the master clock signal.
Compared with the prior art, the beneficial effects of the delay measurement method provided by the embodiment of the invention are the same as those of the delay measurement circuit provided by the technical scheme, and are not repeated herein.
The embodiment of the invention provides electronic equipment. The electronic equipment comprises the delay measurement circuit provided by the technical scheme.
Compared with the prior art, the electronic device provided by the embodiment of the invention has the same beneficial effects as the delay measurement circuit provided by the technical scheme, and the details are not repeated herein.
The embodiment of the invention provides a chip. The chip stores instructions, and when the instructions are operated, the delay measurement method provided by the technical scheme is executed.
Compared with the prior art, the beneficial effects of the chip provided by the embodiment of the invention are the same as those of the delay measurement method provided by the technical scheme, and are not repeated herein.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims (20)

1. A delay measurement circuit is characterized by comprising a logic circuit, a latch circuit and an encoding circuit which are connected in sequence, wherein,
the logic circuit is configured to generate a delay interval signal based on the first multi-bit signal, the second multi-bit signal, and a master clock signal;
the latch circuit is configured to latch a multi-phase clock signal based on a rising edge of the delay interval signal, and obtain a latch value of the multi-phase clock signal, wherein the frequency of the master clock signal is the same as the frequency of the multi-phase clock signal;
the encoding circuit is configured to generate a delay code between the first multi-bit signal flip edge and the rising edge of the master clock signal or between the second multi-bit signal flip edge and the falling edge of the master clock signal based on the latched value.
2. The delay measurement circuit of claim 1, wherein:
the first multi-bit signal and the second multi-bit signal are respectively at the same frequency as the master clock signal;
said first multi-bit signal and said second multi-bit signal are multi-bit gray code counter signals of the same bit-width;
when the encoding circuit is configured to generate a delay code between a flip edge of the first multi-bit signal and a rising edge of the master clock signal based on the latched value, a phase of the first multi-bit signal leads a phase of the second multi-bit signal by a phase time of
Figure FDA0002427127350000011
Wherein f is the frequency of the master clock signal;
when the encoding circuit is configured to generate a delay code between a flip edge of the second multi-bit signal and a falling edge of the master clock signal based on the latched value, a phase of the first multi-bit signal lags a phase of the second multi-bit signal by a phase time of
Figure FDA0002427127350000021
Where f is the frequency of the master clock signal.
3. The delay measurement circuit of claim 2, wherein: the logic circuit comprises a delay signal generating circuit, an enable signal generating circuit and a first gate circuit which is respectively connected with the output end of the delay signal generating circuit and the output end of the enable signal generating circuit, wherein,
the delayed signal generation circuit is configured to generate a delayed signal based on the first multi-bit signal and the second multi-bit signal;
the enable signal generation circuit is configured to generate an enable signal based on the master clock signal;
the first gate circuit is configured to generate the delay interval signal by performing an and operation on the delay signal and the enable signal.
4. The delay measurement circuit of claim 3, wherein: the delay signal generating circuit comprises a third gate circuit and at least two second gate circuits, and the output ends of the at least two second gate circuits are connected with the input end of the third gate circuit;
at least two of the second gate circuits are configured to generate a third multi-bit signal by performing an exclusive-or operation on the first multi-bit signal and the second multi-bit signal;
the third gate circuit is configured to generate the time-delayed signal by performing an or operation on each bit signal of the third multi-bit signal.
5. The delay measurement circuit of claim 3, wherein: the enable signal generating circuit comprises a first timing circuit and a fourth gate circuit which are connected in sequence, wherein when the phase of the first multi-bit signal leads the phase of the second multi-bit signal by the time of
Figure FDA0002427127350000022
The first timing circuit is configured to trigger to output a fourth multi-bit signal according to a rising edge of the master clock signal, where f is a frequency of the master clock signal;
when the phase of the first multi-bit signal lags behind the phase of the second multi-bit signal by a time of
Figure FDA0002427127350000031
The first timing circuit is configured to trigger to output a fourth multi-bit signal according to a falling edge of the master clock signal, where f is a frequency of the master clock signal;
the fourth gate circuit is configured to generate the enable signal by performing an and operation on each bit signal of the fourth multi-bit signal.
6. The delay measurement circuit of claim 5, wherein: the enable signal generation circuit further comprises a fifth gate circuit,
the fifth gate circuit is configured to delay the enable signal by a delay time of the delay interval signal
Figure FDA0002427127350000032
The high level of the periodic pulse width is continuously extracted by the enable signal, wherein f is the frequency of the master clock signal.
7. The delay measurement circuit of claim 5 or 6, wherein: the first time sequence circuit is an m-bit counter, wherein m is a natural number greater than or equal to 2.
8. The delay measurement circuit according to any one of claims 1 to 6, wherein: the time delay measuring circuit also comprises a calibration circuit, and the calibration circuit is used for controlling the coding circuit to output the time delay code.
9. The delay measurement circuit according to any one of claims 1 to 6, wherein: the multiphase clock signal is 2 k Bit clock signals in which any adjacent single bit signals have a phase difference of
Figure FDA0002427127350000033
Wherein k is a natural number greater than or equal to 1, and f is the frequency of the master clock signal.
10. A method of delay measurement, comprising:
generating a delay interval signal based on the first multi-bit signal, the second multi-bit signal and the master clock signal;
latching the multi-phase clock signals based on the rising edge of the delay interval signal to obtain a latched value of the multi-phase clock signals, wherein the frequency of the main clock signal is the same as that of the multi-phase clock signals;
generating a delay code between the first multi-bit signal flip edge and the rising edge of the master clock signal or generating a delay code between the second multi-bit signal flip edge and the falling edge of the master clock signal based on the latched value.
11. The delay measurement method of claim 10,
the first multi-bit signal and the second multi-bit signal are each at the same frequency as the master clock signal,
said first multi-bit signal and said second multi-bit signal are multi-bit gray code counter signals of the same bit-width,
when generating a delay code between a flip edge of the first multi-bit signal and a rising edge of the master clock signal based on the latched value, a phase of the first multi-bit signal leads a phase of the second multi-bit signal by a phase time of
Figure FDA0002427127350000041
Wherein f is the frequency of the master clock signal;
when generating a delay code between a flip edge of the second multi-bit signal and a falling edge of the master clock signal based on the latched value, a phase of the first multi-bit signal lags a phase of the second multi-bit signal by a phase time of
Figure FDA0002427127350000042
Where f is the frequency of the master clock signal.
12. The delay measurement method of claim 11, wherein: the generating a delay interval signal based on the first multi-bit signal, the second multi-bit signal and the master clock signal includes:
generating a time-delayed signal based on the first multi-bit signal and the second multi-bit signal;
generating an enable signal based on the master clock signal;
and the delayed signal and the enabling signal are subjected to AND operation to generate the delayed interval signal.
13. The delay measurement method according to claim 12, characterized in that: said generating a delayed signal based on said first multi-bit signal and said second multi-bit signal comprises:
performing an exclusive-or operation on the first multi-bit signal and the second multi-bit signal to generate a third multi-bit signal;
performing an OR operation on each bit signal of the third multi-bit signal to generate the delayed signal.
14. The delay measurement method of claim 12, wherein: the generating an enable signal based on the master clock signal includes:
when the phase of the first multi-bit signal leads the phase of the second multi-bit signal by the time of
Figure FDA0002427127350000051
Triggering a first timing circuit to output a fourth multi-bit signal according to the rising edge of the master clock signal, wherein f is the frequency of the master clock signal;
when the phase of the first multi-bit signal lags behind the phase of the second multi-bit signal by a time of
Figure FDA0002427127350000052
Triggering a first timing circuit to output a fourth multi-bit signal according to the falling edge of the main clock signal, wherein f is the frequency of the main clock signal;
performing an AND operation on each bit signal of the fourth multi-bit signal to generate the enable signal.
15. According toThe delay measurement method of claim 14, wherein: after performing an and operation on each bit signal of the fourth multi-bit signal to generate the enable signal, delaying the enable signal such that the delay interval signal is
Figure FDA0002427127350000061
The high level of the periodic pulse width is continuously extracted by the enable signal, wherein f is the frequency of the master clock signal.
16. The delay measurement method according to claim 14 or 15, characterized in that: the first time sequence circuit is an m-bit counter, wherein m is a natural number greater than or equal to 2.
17. The delay measurement method according to any one of claims 10 to 15, characterized in that: generating a delay code preamble between a rising edge of the master clock signal and a falling edge of the second multi-bit signal or between a falling edge of the master clock signal based on the latched value, further comprising calibrating the delay code.
18. The delay measurement method according to any one of claims 10 to 15, characterized in that: the multiphase clock signal is 2 k Bit clock signals in which any adjacent single bit signals are out of phase by
Figure FDA0002427127350000062
Wherein k is a natural number greater than or equal to 1, and f is the frequency of the master clock signal.
19. An electronic device comprising the delay measurement circuit according to any one of claims 1 to 9.
20. A chip having stored therein instructions which, when executed, perform the delay measurement method of any one of claims 10 to 18.
CN202010224274.4A 2020-03-26 2020-03-26 Time delay measuring circuit, time delay measuring method, electronic equipment and chip Active CN111416619B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010224274.4A CN111416619B (en) 2020-03-26 2020-03-26 Time delay measuring circuit, time delay measuring method, electronic equipment and chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010224274.4A CN111416619B (en) 2020-03-26 2020-03-26 Time delay measuring circuit, time delay measuring method, electronic equipment and chip

Publications (2)

Publication Number Publication Date
CN111416619A CN111416619A (en) 2020-07-14
CN111416619B true CN111416619B (en) 2023-02-03

Family

ID=71494685

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010224274.4A Active CN111416619B (en) 2020-03-26 2020-03-26 Time delay measuring circuit, time delay measuring method, electronic equipment and chip

Country Status (1)

Country Link
CN (1) CN111416619B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116635724A (en) * 2020-11-18 2023-08-22 华为技术有限公司 Voltage monitoring circuit and chip
CN113297819B (en) * 2021-06-22 2023-07-07 海光信息技术股份有限公司 Timing sequence checking method and device of asynchronous clock, electronic equipment and storage medium

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1618027A (en) * 2001-12-12 2005-05-18 泰拉丁公司 Compact ate with timestamp system
CN102763337A (en) * 2010-02-24 2012-10-31 松下电器产业株式会社 Digital time difference conversion stage and digital time difference converter provided with same
WO2013122221A1 (en) * 2012-02-17 2013-08-22 国立大学法人北海道大学 Integral a/d converter and cmos image sensor
US8664994B1 (en) * 2012-10-10 2014-03-04 Department of Electronics and Information Technology System to generate a predetermined fractional period time delay
CN104300970A (en) * 2014-09-28 2015-01-21 东南大学 Voltage-control ring vibration type two-section type time digital conversion circuit based on DLL

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8164493B2 (en) * 2008-05-29 2012-04-24 Realtek Semiconductor Corporation High-resolution circular interpolation time-to-digital converter

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1618027A (en) * 2001-12-12 2005-05-18 泰拉丁公司 Compact ate with timestamp system
CN102763337A (en) * 2010-02-24 2012-10-31 松下电器产业株式会社 Digital time difference conversion stage and digital time difference converter provided with same
WO2013122221A1 (en) * 2012-02-17 2013-08-22 国立大学法人北海道大学 Integral a/d converter and cmos image sensor
US8664994B1 (en) * 2012-10-10 2014-03-04 Department of Electronics and Information Technology System to generate a predetermined fractional period time delay
CN104300970A (en) * 2014-09-28 2015-01-21 东南大学 Voltage-control ring vibration type two-section type time digital conversion circuit based on DLL

Also Published As

Publication number Publication date
CN111416619A (en) 2020-07-14

Similar Documents

Publication Publication Date Title
US4954824A (en) Sample rate conversion system having interpolation function with phase locked clock
US6262611B1 (en) High-speed data receiving circuit and method
US20030043926A1 (en) Circuit and method for generating a timing signal, and signal transmission system performing for high-speed signal transmission and reception between LSIs
US5903176A (en) Clock circuit for generating a high resolution output from a low resolution clock
CN111416619B (en) Time delay measuring circuit, time delay measuring method, electronic equipment and chip
US10177897B2 (en) Method and system for synchronizing and interleaving separate sampler groups
US6795514B2 (en) Integrated data clock extractor
JP6594420B2 (en) Time-to-digital converter and digital phase-locked loop
US20150054667A1 (en) Time-to-Digital Converter and Related Method
US3889186A (en) All digital phase detector and corrector
Szplet et al. A 45 ps time digitizer with a two-phase clock and dual-edge two-stage interpolation in a field programmable gate array device
US5550878A (en) Phase comparator
US7671649B2 (en) Apparatus and method for generating multi-phase clocks
CN114421967A (en) Phase interpolation circuit, phase-locked loop, chip and electronic device
JP2805604B2 (en) Manchester code decoding device
US7092471B2 (en) Digital phase synchronization circuit
US6661862B1 (en) Digital delay line-based phase detector
US7321647B2 (en) Clock extracting circuit and clock extracting method
KR100410555B1 (en) internal clock generating method for use in semiconductor memory device and circuit therefore
TWI469522B (en) Signal circuit
US6621307B1 (en) Method and circuit for determining frequency and time variations between electronic signals
US5942927A (en) Clock signal generator for a logic analyzer controlled to lock both edges to a reference clock signal
CN114204937B (en) Frequency divider circuit and frequency synthesizer
KR100212551B1 (en) An improved apparatus for generating sync-clock of video signals
WO2024040693A1 (en) Delay-locked loop and memory

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant