CN111416619A

CN111416619A - Delay measurement circuit, delay measurement method, electronic equipment and chip

Info

Publication number: CN111416619A
Application number: CN202010224274.4A
Authority: CN
Inventors: 杨洁; 赵野
Original assignee: Institute of Microelectronics of CAS
Current assignee: Institute of Microelectronics of CAS
Priority date: 2020-03-26
Filing date: 2020-03-26
Publication date: 2020-07-14
Anticipated expiration: 2040-03-26
Also published as: CN111416619B

Abstract

The invention discloses a delay measuring circuit, a delay measuring method, electronic equipment and a chip, and relates to the technical field of electronic circuits, in order to realize the delay between a turnover edge of a dynamic measuring counter and a trigger edge of a main clock, so that the sampling compensation is more accurate, and the consistency between channels is ensured. The delay measurement circuit includes a logic circuit for generating a delay interval signal based on a first multi-bit signal, a second multi-bit signal, and a master clock signal; the latch circuit is used for latching the multi-phase clock signals based on the rising edge of the delay interval signal to obtain the latch values of the multi-phase clock signals; and an encoding circuit for generating a delay code between a first multi-bit signal flip edge and a rising edge of the main clock signal or a delay code between a second multi-bit signal flip edge and a falling edge of the main clock signal based on the latch value. The time delay measuring method and the time delay measuring chip are applied to time delay measurement. The delay measurement circuit is applied to electronic equipment.

Description

Delay measurement circuit, delay measurement method, electronic equipment and chip

Technical Field

The present invention relates to the field of electronic circuit technologies, and in particular, to a delay measurement circuit, a delay measurement method, an electronic device, and a chip.

Background

A Time-to-digital converter (TDC) is widely used to measure a Time difference between two input signals and output the Time difference in a digital manner. However, due to the existence of non-ideal factors such as clock jitter, process, Voltage, Temperature (PVT), metastability, large fan-out, etc., an uncertain delay is generated between the counter of the key functional component of the time-to-digital converter and the trigger clock, which affects the timing result of the time-to-digital converter, and reduces the linearity and precision of the time-to-digital converter.

In order to solve the above problem, a common measurement method is to perform multiple time delays on a single input signal to obtain a set of excitation signals arriving at different times, and compare the set of excitation signals to estimate the true arrival time of the input signal without delay. Since each time-to-digital converter can only process one signal, the above-mentioned measurement method is not favorable for channel expansion, which not only doubles the number of channels, but also results in a sharp increase in cost. Moreover, since the high-precision time-to-digital converter is extremely sensitive to clock jitter, PVT variations, and the like, a simple calibration method is difficult to meet actual working requirements.

In the prior art, a programmable Delay (Delay) method can be adopted, a group of buffer (buffer) chains are used for interpolating the time length of more than 1 period, then an analog loop structure is used for locking the phase difference between a clock triggering edge and a counter overturning edge, and the buffer is adjusted to enable a multi-phase clock to carry out Delay with the same degree. However, this method requires a complex feedback loop, the circuit structure is complex, the occupied area is large, each channel needs to be adjusted independently, the reliability is poor, and the expansion of multiple channels is not facilitated. Furthermore, the phase difference between the lock clock trigger edge and the counter flip edge requires a long time, resulting in extremely low efficiency. And the phase difference is locked and then is not changed. However, the delay of the counter along with the clock may change due to PVT, clock jitter, etc., and the delay between the clock trigger edge and the counter flip edge cannot be updated in time.

Therefore, no matter a simple or complex measuring method is adopted, the influence of the time delay between the data turning edge and the clock triggering edge on the high-speed high-precision system is not fundamentally solved, and no measuring method aiming at the high-speed high-precision system is provided, which is simple, efficient, low in cost and free from the influence of non-ideal factors such as PVT (virtual volume transport) and the like.

Disclosure of Invention

The invention aims to provide a delay measuring circuit, which can dynamically measure the uncertain delay between the data turning edge of a first multi-bit signal or a second multi-bit signal and the triggering edge of a main clock signal, so that the sampling compensation is more accurate, and the consistency among multiple channels is ensured.

In order to achieve the above object, the present invention provides a delay measurement circuit comprising a logic circuit, a latch circuit and an encoding circuit connected in this order, wherein,

the logic circuit is configured to generate a delay interval signal based on the first multi-bit signal, the second multi-bit signal, and the master clock signal; the latch circuit is configured to latch the multi-phase clock signal based on a rising edge of the delay interval signal, and obtain a latch value of the multi-phase clock signal, wherein the frequency of the master clock signal is the same as the frequency of the multi-phase clock signal; the encoding circuit is configured to generate a delay code between a first multi-bit signal flip edge and a rising edge of the master clock signal or a delay code between a second multi-bit signal flip edge and a falling edge of the master clock signal based on the latched value.

Preferably, the first multi-bit signal and the second multi-bit signal are respectively at the same frequency as the master clock signal; the first multi-bit signal and the second multi-bit signal are multi-bit Gray code counter signals with the same bit width; when the encoding circuit is configured to generate the delay code between the flip edge of the first multi-bit signal and the rising edge of the master clock signal based on the latch value, the phase of the first multi-bit signal leads the phase of the second multi-bit signal by a phase time of

Wherein f is the frequency of the master clock signal; when the encoding circuit is configured to generate the delay code between the flip edge of the second multi-bit signal and the falling edge of the master clock signal based on the latched value, the phase of the first multi-bit signal lags behind the phase of the second multi-bit signal by a phase time of

Where f is the frequency of the master clock signal.

Preferably, the logic circuit comprises a delay signal generating circuit, an enable signal generating circuit, and a first gate circuit connected to an output of the delay signal generating circuit and an output of the enable signal generating circuit, respectively, wherein the delay signal generating circuit is configured to generate the delay signal based on the first multi-bit signal and the second multi-bit signal; the enable signal generation circuit is configured to generate an enable signal based on a master clock signal; the first gate circuit is configured to generate a delay interval signal by performing an and operation on the delay signal and the enable signal.

Preferably, the delay signal generating circuit comprises a third gate circuit and at least two second gate circuits, and the output ends of the at least two second gate circuits are connected with the input end of the third gate circuit; at least two second gate circuits configured to generate a third multi-bit signal by performing an exclusive-or operation on the first multi-bit signal and the second multi-bit signal; the third gate circuit is configured to generate a delay signal by performing an or operation on each bit signal of the third multi-bit signal.

Preferably, the enable signal generating circuit includes a first timing circuit and a fourth gate circuit connected in sequence, wherein when the phase of the first multi-bit signal leads the phase of the second multi-bit signal by a time of

The first timing circuit is configured to trigger to output a fourth multi-bit signal according to a rising edge of the master clock signal, wherein f is the frequency of the master clock signal; when the phase of the first multi-bit signal lags behind the phase of the second multi-bit signal by a time of

The first timing circuit is configured to trigger to output a fourth multi-bit signal according to a falling edge of the master clock signal, wherein f is the frequency of the master clock signal; the fourth gate circuit is configured to generate an enable signal by performing an and operation on each bit signal of the fourth multi-bit signal.

Preferably, the enable signal generating circuit further includes a fifth gate circuit configured to delay the interval signal by delaying the enable signal

The high level of the periodic pulse width is continuously extracted by an enable signal, wherein f is the frequency of the master clock signal.

Preferably, the first timing circuit is an m-bit counter, where m is a natural number greater than or equal to 2.

Preferably, the delay measuring circuit further comprises a calibration circuit, and the calibration circuit is used for controlling the encoding circuit to output the delay code.

Preferably, the multi-phase clock signal is 2^kBit clock signals in which any adjacent single bit signals have a phase difference of

Where k is a natural number greater than or equal to 1 and f is the frequency of the master clock signal.

Compared with the prior art, the delay measuring circuit provided by the invention comprises a logic circuit, a latch circuit and a coding circuit which are sequentially connected. And converting the time delay between the first multi-bit signal turning edge and the rising edge of the main clock signal or between the second multi-bit signal turning edge and the falling edge of the main clock signal into the rising edge information of the time delay interval signal through a logic circuit. When the rising edge of the delay interval signal output by the logic circuit arrives, the latch circuit latches the instantaneous level of the multi-phase clock signal, and the delay code between the first multi-bit signal turning edge and the rising edge of the main clock signal or between the second multi-bit signal turning edge and the falling edge of the main clock signal is obtained according to a plurality of instantaneous level information of the latched multi-phase clock signal. The latch circuit latches the multi-phase clock signals according to the rising edge of the delay interval signal to obtain the delay codes corresponding to the delay interval signal. The delay code of the present invention is dynamically changed according to the input first and second multi-bit signals. Although there is an indeterminate delay between the data flip edge of the first multi-bit signal or the second multi-bit signal and the trigger edge of the master clock signal in the prior art due to the influence of clock jitter, PVT, and other non-ideal factors. But through the technical scheme of the delay measuring circuit, uncertain delay between the data turning edge of the first multi-bit signal or the second multi-bit signal and the triggering edge of the main clock signal can be dynamically obtained, and compared with the condition that the phase difference is locked by a phase-locked loop and then is fixed, the delay can be dynamically fed back, so that the subsequent sampling compensation is more accurate, the consistency among multiple channels can be ensured, and the influence of any non-ideal factor is avoided. Compared with other slow latching processes, the multi-phase clock signal can be latched as long as the rising edge of the delay interval signal arrives at the latch, and the delay code is obtained by using the coding circuit according to the latching value, so that the method is fast and efficient, and the measurement of the delay code is accurate. Compared with a complex analog circuit with multiple parasitic effects, the digital circuit design is adopted, and the structure is simple.

The invention also provides a time delay measuring method, which comprises the following steps: generating a delay interval signal based on the first multi-bit signal, the second multi-bit signal and the master clock signal; latching the multi-phase clock signals based on the rising edge of the delay interval signal to obtain a latched value of the multi-phase clock signals, wherein the frequency of the main clock signal is the same as that of the multi-phase clock signals; a delay code between a first multi-bit signal flip edge and a rising edge of the master clock signal is generated based on the latched value, or a delay code between a second multi-bit signal flip edge and a falling edge of the master clock signal is generated.

Preferably, the first and second multi-bit signals have the same frequency as the master clock signal, respectively, are multi-bit gray code counter signals having the same bit width, and when the delay code between the inversion edge of the first multi-bit signal and the rising edge of the master clock signal is generated based on the latch value, the phase of the first multi-bit signal is advanced by the phase time of the second multi-bit signal by

Wherein f is the frequency of the master clock signal; when generating a delay code between a flip edge of the second multi-bit signal and a falling edge of the master clock signal based on the latched value, the phase of the first multi-bit signal lags behind the phase of the second multi-bit signal by a phase time of

Where f is the frequency of the master clock signal.

Preferably, generating the delay interval signal based on the first multi-bit signal, the second multi-bit signal and the master clock signal comprises: generating a delayed signal based on the first multi-bit signal and the second multi-bit signal; generating an enable signal based on a master clock signal; and operation is performed on the delay signal and the enable signal to generate a delay interval signal.

Preferably, generating the delayed signal based on the first multi-bit signal and the second multi-bit signal comprises: performing an exclusive-or operation on the first multi-bit signal and the second multi-bit signal to generate a third multi-bit signal; performing an or operation on each bit signal of the third multi-bit signal generates a delayed signal.

Preferably, generating the enable signal based on the master clock signal comprises: when the phase of the first multi-bit signal leads the phase of the second multi-bit signal by the time of

Triggering the first timing circuit to output a fourth multi-bit signal according to the rising edge of the main clock signal, wherein f is the frequency of the main clock signal; when the phase of the first multi-bit signal lags behind the phase of the second multi-bit signal by a time of

Triggering the first timing circuit to output a fourth multi-bit signal according to the falling edge of the master clock signal, wherein f is the frequency of the master clock signal; and operation is performed on each bit signal of the fourth multi-bit signal to generate an enable signal.

Preferably, after performing and operation on each bit signal of the fourth signal to generate the enable signal, delaying the enable signal such that the interval signal is delayed

The high level of the periodic pulse width is continuously extracted by an enabling signal, wherein f is the frequency of the main clock signal。

Preferably, generating the delay code preamble between the flip edge of the first multi-bit signal and the rising edge of the master clock signal or between the flip edge of the second multi-bit signal and the falling edge of the master clock signal based on the latched value further comprises calibrating the delay code.

Compared with the prior art, the beneficial effects of the delay measurement method provided by the invention are the same as those of the delay measurement circuit provided by the technical scheme, and are not repeated herein.

The invention also provides electronic equipment which comprises the delay measuring circuit provided by the technical scheme.

Compared with the prior art, the electronic device provided by the invention has the same beneficial effects as the delay measurement circuit provided by the technical scheme, and the detailed description is omitted here.

The invention also provides a chip, wherein the chip is stored with instructions, and when the instructions are operated, the time delay measuring method provided by the technical scheme is executed.

Compared with the prior art, the chip provided by the invention has the same beneficial effect as the time delay measuring method provided by the technical scheme, and the detailed description is omitted here.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:

fig. 1 shows a circuit diagram of a prior art scenario for generating and applying a delay signal;

FIG. 2 shows a timing diagram of the signals shown in FIG. 1 provided by the prior art;

FIG. 3 is a block diagram of a delay measurement circuit according to an embodiment of the present invention;

FIG. 4 is a circuit diagram for generating a first multi-bit signal according to an embodiment of the present invention;

FIG. 5 is a circuit diagram for generating a second multi-bit signal according to an embodiment of the present invention;

FIG. 6 is a circuit diagram of a logic circuit provided by an embodiment of the present invention;

FIG. 7 is a circuit diagram of a single latch in the latch circuit according to the embodiment of the present invention;

FIG. 8 is a timing diagram of signals established according to a delay measurement circuit according to an embodiment of the present invention;

fig. 9 is a flowchart of a delay measurement method according to an embodiment of the present invention.

The circuit comprises a logic circuit 1, a delay signal generating circuit 10, a second gate circuit 110, a third gate circuit 120, a third gate circuit 20, an enable signal generating circuit 210, a first timing circuit 220, a fourth gate circuit 230, a fifth gate circuit 2201, a buffer 30, a first gate circuit 2, a latch circuit 200, a latch 2001, a sensitive amplifier 2002, an SR latch 3, an encoding circuit 4, a calibration circuit 510, a first counter 520, a second counter 1001, a first D trigger 1002 and a second D trigger.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

FIG. 1 shows a circuit diagram of a prior art scenario for generating and applying a delay signal, as shown in FIG. 1, a clock C L K1 triggers a first D flip-flop 1001 to generate a first signal CNT1[ N:0], where the first signal CNT1[ N:0] is a multi-bit signal, a rising edge of an asynchronous clock C L K2 triggers a second D flip-flop 1002 to sample a first signal CNT1[ N:0], ideally, the second D flip-flop 1002 should sample a stable first signal CNT1[ N:0], but a deviation exists between the second signal CNT2[ N:0] actually sampled by the second D flip-flop 1002 and an original first signal CNT1[ N:0] due to the insertion of a buffer chain 2201, and the second signal CNT2[ N:0] is an original first signal CNT1[ N:0] obtained after the delay of the buffer chain 2201, where the second signal CNT2 is a multiple of bits, where the number of the N:0 is equal to a natural number of the multi-bit signal CNT 2.

Furthermore, due to the existence of non-ideal factors such as clock jitter, process, voltage, temperature (PVT), metastable state, large fan-out, etc. in the high-speed high-precision circuit system, the delay between the second signal CNT2[ N:0] obtained through the buffer 2201 chain and the original first signal CNT1[ N:0] is not fixed, where N is a natural number greater than or equal to 1.

Fig. 2 shows a timing diagram of the signals shown in fig. 1 provided by the prior art. As shown in FIG. 2, the first region A is a metastable region, the second region B is a stable region, and an indeterminate delay t exists between the first signal CNT1[ N:0] and the second signal CNT2[ N:0] due to the chain of the buffer 2201, wherein N is a natural number greater than or equal to 1.

It is known from the background art that asynchronous clock C L K2 can be delayed to the same extent by inserting and adjusting the number of buffers 2201 before asynchronous clock C L K2, but this method requires a complicated feedback loop, has a complicated circuit structure, occupies a large area, is adjusted independently for each channel, has poor reliability, and is not favorable for expansion of multiple channels, and it takes a long time to lock the phase difference between the flip edge of second signal CNT2[ N:0] and the flip edge of first signal CNT1[ N:0], resulting in extremely low efficiency, and at the same time, the phase difference is not changed any more after locking, so that the dynamic delay between second signal CNT2[ N:0] and first signal CNT1[ N:0] cannot be updated in time.

In view of the above problem, an embodiment of the present invention provides a delay measurement circuit, and fig. 3 shows a block diagram of the delay measurement circuit provided in the embodiment of the present invention.

As shown in fig. 3, the delay measuring circuit includes a logic circuit 1, a latch circuit 2, and an encoding circuit 3, which are connected in sequence. Wherein the first multi-bit signal PCNT [ n-1:0]]A second multi-bit signal NCNT [ n-1:0]]And a master clock signal f_PLLThe delay interval signal P _ Dly is output through the logical operation of the logic circuit 1, where n is a natural number greater than or equal to 2. It should be appreciated that the delay interval signal P _ Dly may be the first multi-bit signal PCNT [ n-1:0]]And a master clock signal f_PLLThe delay between the first and second multi-bit signals NCNT [ n-1:0] can be set to be]And a master clock signal f_PLLThe delay between them. For example, the delay interval signal P _ Dly may be the first multi-bit signal PCNT [ n-1:0]]The flip edge and the master clock signal f_PLLThe delay between rising edges may also be the second multi-bit signal NCNT [ n-1:0]]The flip edge and the master clock signal f_PLLThe delay between the falling edges may also be a delay of other phases, and is not limited in this respect.

As shown in FIG. 3, the rising edge of the delay interval signal P _ Dly is used to trigger the latch circuit 2 to latch the multiphase clock signal F [2 ]^k-1:0]Latching is performed, where k is a natural number equal to or greater than 1, that is, at the time of the rising edge of the delay interval signal P _ Dly, the latch circuit 2 latches the multiphase clock signal F [2 ]^k-1:0]Is latched to obtain a multi-phase clock signal F2^k-1:0]The latched value of (1). It will be appreciated that the latch circuit 2 latches the multi-phase clock signal F2^k-1:0]At various instantaneous levels of the rising edge of the delay interval signal P _ Dly, for example: multiphase clock signal F2^k-1:0]Is 2^kBit, then obtain 2^kAnd (c) instantaneous level values, where k is a natural number greater than or equal to 1.

As shown in FIG. 3, the latch circuit 2 obtains a multi-phase clock signal F [2 ]^k-1:0]Because each of the plurality of instantaneous levelsOne level corresponds to a binary code of 0 or 1, while a plurality of instantaneous levels correspond to a series of binary codes of 0 or 1. The latch circuit 2 thus latches the multiphase clock signal F2^k-1:0]A plurality of momentary binary codes. The delay codes corresponding to the plurality of instantaneous binary codes latched by the latch circuit 2 are found by the encoding circuit 3. For example, the plurality of instantaneous binary codes is 0011111111000000, and the corresponding delay code is 13.

Based on the technical scheme of the delay measurement circuit, the delay between the first multi-bit signal turning edge and the rising edge of the main clock signal or the delay between the second multi-bit signal turning edge and the falling edge of the main clock signal is converted into the rising edge information of the delay interval signal through the logic circuit. When the rising edge of the delay interval signal comes, the latch circuit latches the instantaneous level of the multi-phase clock signal, and obtains the delay code between the first multi-bit signal turning edge and the rising edge of the main clock signal or between the second multi-bit signal turning edge and the falling edge of the main clock signal according to the binary codes of a plurality of instantaneous levels of the latched multi-phase clock signal. The latch circuit latches the multi-phase clock signals according to the rising edge of the delay interval signal to obtain the delay codes corresponding to the delay interval signal. The delay code of the present invention is dynamically changed according to the input first and second multi-bit signals. Although there is an indeterminate delay t between the data flip edge of the first multi-bit signal or the second multi-bit signal and the trigger edge of the master clock signal due to the effects of clock jitter, PVT, and other non-ideal factors. But through the technical scheme of the delay measuring circuit, uncertain delay between the data turning edge of the first multi-bit signal or the second multi-bit signal and the triggering edge of the main clock signal can be dynamically obtained, compared with the condition that the phase difference is locked by a phase-locked loop and then is fixed, the delay can be dynamically fed back, the sampling compensation is more accurate, the consistency among multiple channels can be ensured, and the influence of non-ideal factors is not easily caused. Compared with other slow latching processes, the multi-phase clock signal can be latched as long as the rising edge of the delay interval signal arrives at the latching circuit, and the delay code is obtained by utilizing the coding circuit according to the latching value, so that the method is fast and efficient, and the delay measurement is accurate. Compared with a complex analog circuit with multiple parasitic effects, the digital circuit design is adopted, and the structure is simple.

As a possible implementation manner, fig. 4 shows a circuit diagram for generating a first multi-bit signal provided by an embodiment of the present invention, and fig. 5 shows a circuit diagram for generating a second multi-bit signal provided by an embodiment of the present invention.

As shown in fig. 4-5, the master clock signal f_PLLThe single-channel counter signals are respectively output after passing through the first counter 510 and the second counter 520, and because the single-channel counter signals have limited driving capability and a large number of channels, the single-channel counter signals need to be respectively driven by a plurality of buffers 2201 in an increasing manner, and simultaneously, the single-channel counter signals are respectively expanded into a plurality of output signals through a buffer tree composed of the buffers 2201 so as to be sampled by a plurality of channels.

Specifically, as shown in fig. 4, the master clock signal f_PLLThe one-way counter signal is output after passing through the first counter 510, for example, the first counter 510 may be an n-bit gray code counter, where n is a natural number greater than 1, such as an 11-bit gray code counter. The one-way counter signal passes through a buffer tree composed of buffers 2201 and then outputs at least two first signals PCNT [ n-1:0]]. It is understood that the first multi-bit signal PCNT [ n-1:0] is output]Is related to the number of buffers 2201 and the buffer tree, e.g. outputting 8 first multi-bit signals PCNT [ n-1:0] in FIG. 4]Of course, other number of first multi-bit signals PCNT [ n-1:0] may be output by changing the number of buffers 2201 and the buffer tree]。

Illustratively, as shown in FIG. 4, if the first counter 510 is an n-bit Gray code counter, the first multi-bit signal PCNT [ n-1:0] output after passing through a buffer tree composed of buffers 2201 in FIG. 4]For an n-bit gray code counter signal, where n is a natural number greater than 1, for example, an 11-bit gray code counter signal may be used. Due to the first multi-bit signal PCNT [ n-1:0]Is by a master clock signal f_PLLTriggered by a Gray code counter, so that the first multi-bit signal PCNT [ n-1:0]]And a master clock signal f_PLLThe frequencies are the same. It should be understood that when measuringFirst multibit signal PCNT [ n-1:0]]The flip edge and the master clock signal f_PLLDelay code timing between rising edges, first multi-bit signal PCNT [ n-1:0]Phase-advanced second multi-bit signal NCNT [ n-1:0]]The time of the phase is

Where f is the frequency of the master clock signal.

Specifically, as shown in fig. 5, the circuit configurations of fig. 5 and fig. 4 are identical, and only the differences between fig. 5 and fig. 4 are described herein, if the second counter 520 is an n-bit gray code counter, the second multi-bit signal NCNT [ n-1:0] output after passing through the buffer tree composed of the buffers 2201 in fig. 5]For an n-bit gray code counter signal, where n is a natural number greater than 1, for example, an 11-bit gray code counter signal may be used. First multibit signal PCNT [ n-1:0]]And the second multi-bit signal NCNT n-1:0 may be a multi-bit gray code counter signal of the same bit-width. Due to the second multi-bit signal NCNT [ n-1:0]]Is by a master clock signal f_PLLTriggered by a Gray code counter, so that the second multi-bit signal NCNT [ n-1:0]]And a master clock signal f_PLLThe frequencies are the same, it being understood that when measuring the second multi-bit signal NCNT [ n-1:0]]The flip edge and the master clock signal f_PLLThe first multi-bit signal PCNT [ n-1:0] at the time of delay code between rising edges]Phase-delayed second multi-bit signal NCNT [ n-1:0]The time of the phase is

Where f is the frequency of the master clock signal.

Fig. 6 shows a circuit diagram of a logic circuit provided in an embodiment of the present invention as a possible implementation method. Fig. 8 shows a timing diagram of signals established according to a delay measurement circuit provided by an embodiment of the present invention. As shown in fig. 6, the logic circuit 1 includes a delayed signal generating circuit 10, an enable signal generating circuit 20, and a first gate circuit 30 connected to an output terminal of the delayed signal generating circuit 10 and an output terminal of the enable signal generating circuit 20, respectively.

As shown in FIG. 6, the delay signal generating circuit 10 is used forAccording to a first multi-bit signal PCNT [ n-1:0]And a second multi-bit signal NCNT [ n-1:0]]The delayed signal P _ Dly _ Tmp is extracted, it being understood that the delayed signal P _ Dly _ Tmp can be the first multi-bit signal PCNT [ n-1:0]]The flip edge and the master clock signal f_PLLThe delay between rising edges may also be the second multi-bit signal NCNT [ n-1:0]]The flip edge and the master clock signal f_PLLThe delay between falling edges. The enable signal generating circuit 20 is used for generating a master clock signal f according to the master clock signal_PLLThe enable signal En is output. The delay signal P _ Dly _ Tmp and the enable signal En are anded by the first gate circuit 30 to output a delay interval signal P _ Dly. It should be appreciated that the delay interval signal P _ Dly occurs every several master clock cycles.

Specifically, as shown in fig. 6, the delay signal generating circuit 10 includes a third gate circuit 120 and at least two second gate circuits 110, and the output terminals of the at least two second gate circuits 110 are connected to the input terminals of the third gate circuit 120. The first and second multi-bit signals PCNT [ n-1:0] and NCNT [ n-1:0] are respectively input to at least two second gate circuits, and since the first and second multi-bit signals PCNT [ n-1:0] and NCNT [ n-1:0] are n-bit gray code counter signals, n second gate circuits 110 are required, where n is a natural number greater than 1. The gray code counter signal for each bit of the first multi-bit signal PCNT [ n-1:0] and the second multi-bit signal NCNT [ n-1:0] is exclusive-ored by a second gate circuit 110 to generate a bit signal corresponding to the third signal PNT [ n-1:0 ]. The third multi-bit signal PNT [ n-1:0] obtained by performing an exclusive-or operation on each corresponding bit gray code counter signal of the first multi-bit signal PCNT [ n-1:0] and the second multi-bit signal NCNT [ n-1:0] by the second gate circuit 110 is also an n-bit gray code counter signal, and each bit signal of the third multi-bit signal PNT [ n-1:0] is subjected to an or operation by the third gate circuit 120 to obtain the delay signal P _ Dly _ Tmp _. The first and second multi-bit signals PCNT [ n-1:0] and NCNT [ n-1:0] are preliminarily extracted as the delay signal P _ Dly _ Tmp _bylogical operations of n second gate circuits 110 and a third gate circuit 120, respectively.

Illustratively, as shown in FIG. 8, the first multi-bit signal PCNT [ n-1:0]]Phase ofAdvanced second multi-bit signal NCNT [ n-1:0]]Has a phase time of

For example, the first multi-bit signal PCNT [ n-1:0]]The flip edge and the master clock signal f_PLLThe time delay between rising edges is

Wherein

T is the master clock signal f_PLLPeriod of (d), f being the master clock signal f_PLLOf (c) is detected. According to the master clock signal f_PLLA first multi-bit signal PCNT [ n-1:0]]And a second multi-bit signal NCNT [ n-1:0]]Preliminary extraction and processing by the delay signal generating circuit 10

Is delayed by the corresponding delay signal P _ Dly _ Tmp _.

As shown in fig. 6, the enable signal generating circuit 20 includes a first timing circuit 210, a fourth gate circuit 220, and a fifth gate circuit 230 connected in sequence. Wherein, when the first multi-bit signal PCNT [ n-1:0]]Is advanced by the phase of the second multi-bit signal NCNT [ n-1:0]]Has a phase time of

According to a master clock signal f_PLLThe rising edge triggers the first timing circuit 210 to output a fourth multi-bit signal Cnt [ m-1:0]When the first multi-bit signal PCNT [ n-1:0]]Is delayed by the phase of the second multi-bit signal NCNT [ n-1:0]]Has a phase time of

According to a master clock signal f_PLLThe falling edge triggers the first timing circuit to output a fourth multi-bit signal Cnt [ m-1:0 [ ]]Where f is the frequency of the master clock signal and m is a natural number greater than or equal to 2.

Illustratively, the first multi-bit signal PCNT [ n-1:0]]Phase lead ofBit signal NCNT [ n-1:0]]Has a phase time of

Thus according to the master clock signal f_PLLThe rising edge triggers the first timing circuit 210 to output a fourth multi-bit signal Cnt [ m-1:0]。

Specifically, the first timing circuit 210 is an m-bit counter, where m is a natural number greater than or equal to 2. For example, it may be a 3-bit counter. Master clock signal f_PLLThe rising edge triggers the first timing circuit 210 to output a fourth multi-bit signal Cnt [ m-1:0]Because the first timing circuit 210 is an m-bit counter, the fourth multi-bit signal Cnt [ m-1:0]]For m-bit counter signals, e.g. 3-bit counter signals, Cnt [ 0] respectively]、Cnt[1]And Cnt [2 ]]. Fourth multi-bit signal Cnt [ m-1:0]]And each of the bit signals is and-operated by the fourth gate circuit 220 and outputs an initial enable signal Cnt _ En, which is output after being delayed by the fifth gate circuit 230.

Further, as shown in fig. 6 and 8, the fifth gate 230 may include a plurality of buffers 2201, and it is understood that the delay time is related to the number of buffers 2201. For example, if the arrival time of the rising edge of the enable signal En is not during the low level of the delay signal P _ Dly _ Tmp, the number of buffers 2201 is increased in the fifth gate circuit 230, that is, the arrival time of the rising edge of the enable signal En is during the low level of the delay signal P _ Dly _ Tmp by increasing the delay. Because the delay interval signal P _ Dly can be enabled only when the rising edge of the enable signal En arrives during the low level of the delay signal P _ Dly _ Tmp

The high level of the periodic pulse width is extracted continuously by the enable signal En, where f is the frequency of the master clock signal, so that the rising edge of the delay interval signal P _ Dly can be obtained.

Illustratively, as shown in FIG. 8, the first multi-bit signal PCNT [ n-1:0] and the second multi-bit signal NCNT [ n-1:0] are 11-bit Gray code counter signals, and the fourth multi-bit signal Cnt [ m-1:0] is a 3-bit counter signal. Therefore, the rising edge of the delay interval signal P _ Dly output by the logic circuit 1 occurs once through 8 main clock cycles, i.e., the delay interval signal P _ Dly is updated once through 8 main clock cycles.

Based on the technical scheme, compared with the situation that the phase difference is fixed after being locked by the phase-locked loop, and compared with other slow latching processes, the time delay code is updated once every 8 periods, so that the method and the device are quick and efficient, and the time delay code is accurately measured.

As a possible implementation manner, as shown in FIG. 7 and FIG. 8, after the logic circuit 1 extracts the rising edge of the interval signal P _ Dly that occurs once in 8 clock cycles, the rising edge of the delay interval signal P _ Dly is used to trigger the latch circuit 2 to latch the multi-phase clock signal F [2 ]^k-1:0]Latching is performed, wherein a multi-phase clock signal F2^k-1:0]Frequency of and master clock signal f_PLLAre the same.

Illustratively, as shown in FIG. 8, the multi-phase clock signal F [2 ]^k-1:0]Is 2^kBit clock signal, multiphase clock signal F2^k-1:0]May be 2, 4, 8, 16 …, wherein any adjacent single-bit signal has a phase difference of

Where k is a natural number greater than or equal to 1 and f is the frequency of the master clock signal. For example, a multi-phase clock signal F2^k-1:0]May be a 16-bit clock signal, may be generated by a phase-locked loop circuit, wherein any adjacent single-bit signal is out of phase by

Where f is the frequency of the master clock signal.

As shown in FIGS. 7 and 8, due to the multi-phase clock signal F [2 ]^k-1:0]For multi-bit clock signals, the latch circuit of FIG. 7 has only two differential inputs for a single latch, and thus, it is necessary to compare the multi-phase clock signals F [2 ]^k-1:0]Latching is performed, and 2 is required in each latch circuit 2^k-1A latch as shown in FIG. 7, wherein k is greater thanA natural number equal to 1. For example, a multi-phase clock signal F2^k-1:0]Is a 16-bit clock signal, whereas the latch circuit of fig. 7 has only two differential inputs for a single latch, and therefore requires 8 latches as shown in fig. 7.

Specifically, as shown in FIGS. 7 and 8, latch 200 includes a sense amplifier 2001 and an SR latch 2002, Fi]And F [ i +2 ]^k-1]For differential input signals, the rising edge of the delay interval signal P _ Dly triggers the SR latch 2002 to couple the differential input signal F [ i ]]And F [ i +2 ]^k-1]Latching, outputting latched value Dly _ L at [ i ]]Equal to the level value of the differential input signal sampled at the instant when the rising edge of the delay interval signal P _ Dly comes, Dly _ L at _ N [ i [ ]]Is Dly _ L at [ i ]]Wherein i is 0 or more and 2 or less^k-1K is a natural number of 1 or more.

As shown in FIG. 8, the latch circuit 2 is triggered to latch the multiphase clock signal F [2 ] at the rising edge of the delay interval signal P _ Dly^k-1:0]Latching to obtain multi-phase clock signal F2^k-1:0]A plurality of instantaneous levels, i.e., a plurality of binary codes, corresponding to the rising edge of the delay interval signal P _ Dly. Illustratively, as shown in FIG. 8, a multi-phase clock signal F [2 ]^k-1:0]From F [ 0]]To F [15 ]]The instantaneous level latched by the latch circuit 2 corresponds to a binary code of 0011111111000000. Based on the latched binary code, the corresponding delay code is found to be 13 in Table 1, and the first multi-bit signal PCNT [ n-1:0]]The flip edge and the master clock signal f_PLLThe delay between rising edges is between 13/16T-14/16T and is substantially the same as the delay of 13/16T actually set in the figure, because the gate circuit has a smaller delay, the delay interval signal P _ Dly is not strictly switched at the rising edge of the counter, so the measured delay is slightly larger than the actual delay, so long as the delay is within the error range.

TABLE 1 corresponding relationship table of delay code and latch value

As a possible implementation manner, as shown in fig. 3, the delay measuring circuit further includes a calibration circuit 4, and when the output of the delay Code Dly _ Code does not coincide with the actual delay, the calibration circuit 4 is required to calibrate the delay Code Dly _ Code.

Illustratively, the adjustable control line Adjust of the calibration circuit is used to Adjust the output of the delay Code Dly _ Code of Table 1 when the output of the delay Code Dly _ Code does not coincide with the actual delay. Illustratively, the calibration circuit may be an I2C module. Specifically, when the output of the delay Code Dly _ Code is inconsistent with the actual delay, the calibration circuit 4 performs an plus 1 loop operation on Adjust, and adjusts the delay Code Dly _ Code from large to small, with an adjustment step size of 1. For example, if the delay Code Dly _ Code in table 1 is 13 and does not coincide with the actual delay, Adjust 1, the calibration circuit 4 adjusts 13 in table 1 to 12, and further compares with the actual delay until finding the delay Code within the error range, and then keeps the value of the adjustable control line Adjust unchanged.

Based on the above technical scheme of the calibration circuit in the delay measurement circuit, it can be known that by setting the external calibration circuit 4, the system error can be eliminated, and a more accurate delay code can be obtained.

It should be understood that the present embodiment provides for a first multi-bit signal PCNT [ n-1:0]]And the flip edge of (f) and the master clock signal f_PLLDelay between rising edges, and extracting the rising edge of the delay interval signal P _ Dly which occurs once in 8 main clock cycles, upon arrival of the rising edge of the delay interval signal P _ Dly, the multiphase clock signal F [2 ]^k-1:0]Latching is performed, and the delay Code Dly _ Code is obtained from the encoding circuit 3 based on the latched value of the binary encoding.

However, the technical scheme provided by the embodiment of the invention can measure the second multi-bit signal NCNT [ n-1:0] as well]And the flip edge of (f) and the master clock signal f_PLLDelay between falling edges when measuring the second multi-bit signal NCNT [ n-1:0]]And the flip edge of (f) and the master clock signal f_PLLExtracting the time delay between falling edges, occurring once in 8 cyclesThe falling edge of the delay interval signal P _ Dly is reflected as a rising edge by the inverter, and when the falling edge of the delay interval signal P _ Dly comes, the rising edge outputted by the inverter is reflected to the multiphase clock signal F [2 ]^k-1:0]Latching is performed, and the delay Code Dly _ Code is obtained from the encoding circuit 3 based on the latched value of the binary encoding.

The embodiment of the invention also provides a time delay measuring method. As shown in fig. 9, the delay measuring method includes the following steps:

step 101, generating a delay interval signal based on the first multi-bit signal, the second multi-bit signal and the master clock signal.

And 102, latching the multi-phase clock signal based on the rising edge of the delay interval signal to obtain a latched value of the multi-phase clock signal, wherein the frequency of the main clock signal is the same as that of the multi-phase clock signal.

And 103, generating a delay code between the first multi-bit signal turning edge and the rising edge of the main clock signal or generating a delay code between the second multi-bit signal turning edge and the falling edge of the main clock signal based on the latched value.

Where f is the frequency of the master clock signal.

Preferably, generating the delay interval signal based on the first multi-bit signal, the second multi-bit signal and the master clock signal comprises: generating a delay signal according to the first multi-bit signal and the second multi-bit signal; generating an enable signal according to a master clock signal; and operation is performed on the delay signal and the enable signal to generate a delay interval signal.

Preferably, generating the delayed signal from the first multi-bit signal and the second multi-bit signal comprises: performing an exclusive-or operation on the first multi-bit signal and the second multi-bit signal to generate a third multi-bit signal; performing an or operation on each bit signal of the third multi-bit signal generates a delayed signal.

Preferably, generating the enable signal from the master clock signal comprises: when the phase of the first multi-bit signal leads the phase of the second multi-bit signal by the time of

Preferably, before generating the delay code between the flip edge of the first multi-bit signal and the rising edge of the master clock signal or generating the delay code between the flip edge of the second multi-bit signal and the falling edge of the master clock signal based on the latched value, calibrating the delay code is further included.

Compared with the prior art, the beneficial effects of the delay measurement method provided by the embodiment of the invention are the same as those of the delay measurement circuit provided by the technical scheme, and are not repeated herein.

The embodiment of the invention provides electronic equipment. The electronic equipment comprises the delay measurement circuit provided by the technical scheme.

Compared with the prior art, the electronic device provided by the embodiment of the invention has the same beneficial effects as the delay measurement circuit provided by the technical scheme, and the details are not repeated herein.

The embodiment of the invention provides a chip. The chip stores instructions, and when the instructions are operated, the delay measurement method provided by the technical scheme is executed.

Compared with the prior art, the beneficial effects of the chip provided by the embodiment of the invention are the same as those of the delay measurement method provided by the technical scheme, and are not repeated herein.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims

1. A delay measurement circuit is characterized by comprising a logic circuit, a latch circuit and an encoding circuit which are connected in sequence, wherein,

the logic circuit is configured to generate a delay interval signal based on the first multi-bit signal, the second multi-bit signal, and a master clock signal;

the latch circuit is configured to latch a multi-phase clock signal based on a rising edge of the delay interval signal, and obtain a latch value of the multi-phase clock signal, wherein the frequency of the master clock signal is the same as the frequency of the multi-phase clock signal;

the encoding circuit is configured to generate a delay code between the first multi-bit signal flip edge and the rising edge of the master clock signal or between the second multi-bit signal flip edge and the falling edge of the master clock signal based on the latched value.

2. The delay measurement circuit of claim 1, wherein:

the first multi-bit signal and the second multi-bit signal are respectively at the same frequency as the master clock signal;

the first multi-bit signal and the second multi-bit signal are multi-bit gray code counter signals with the same bit width;

when the encoding circuit is configured to generate a delay code between a flip edge of the first multi-bit signal and a rising edge of the master clock signal based on the latched value, a phase of the first multi-bit signal leads a phase of the second multi-bit signal by a phase time of

Wherein f is the frequency of the master clock signal;

when the encoding circuit is configured to generate a delay code between a flip edge of the second multi-bit signal and a falling edge of the master clock signal based on the latched value, a phase of the first multi-bit signal lags a phase of the second multi-bit signal by a phase time of

Where f is the frequency of the master clock signal.

3. The delay measurement circuit of claim 2, wherein: the logic circuit comprises a delay signal generating circuit, an enable signal generating circuit and a first gate circuit which is respectively connected with the output end of the delay signal generating circuit and the output end of the enable signal generating circuit, wherein,

the delayed signal generation circuit is configured to generate a delayed signal based on the first multi-bit signal and the second multi-bit signal;

the enable signal generation circuit is configured to generate an enable signal based on the master clock signal;

the first gate circuit is configured to generate the delay interval signal by performing an and operation on the delay signal and the enable signal.

4. The delay measurement circuit of claim 3, wherein: the delay signal generating circuit comprises a third gate circuit and at least two second gate circuits, and the output ends of the at least two second gate circuits are connected with the input end of the third gate circuit;

at least two of the second gate circuits are configured to generate a third multi-bit signal by performing an exclusive-or operation on the first multi-bit signal and the second multi-bit signal;

the third gate circuit is configured to generate the delay signal by performing an or operation on each bit signal of the third multi-bit signal.

5. The delay measurement circuit of claim 3, wherein: the enable signal generating circuit comprises a first timing circuit and a fourth gate circuit which are connected in sequence, wherein when the phase of the first multi-bit signal leads the phase of the second multi-bit signal by the time of

The first timing circuit is configured to trigger to output a fourth multi-bit signal according to a rising edge of the master clock signal, where f is a frequency of the master clock signal;

when the phase of the first multi-bit signal lags behind the phase of the second multi-bit signal by a time of

The first timing circuit is configured to trigger to output a fourth multi-bit signal according to a falling edge of the master clock signal, where f is a frequency of the master clock signal;

the fourth gate circuit is configured to generate the enable signal by performing an and operation on each bit signal of the fourth multi-bit signal.

6. The delay measurement circuit of claim 5, wherein: the enable signal generation circuit further comprises a fifth gate circuit,

the fifth gate circuit is configured to delay the enable signal by delaying the delay interval signal

The high level of the periodic pulse width is continuously extracted by the enable signal, wherein f is the frequency of the master clock signal.

7. The delay measurement circuit of claim 5 or 6, wherein: the first time sequence circuit is an m-bit counter, wherein m is a natural number greater than or equal to 2.

8. The delay measurement circuit according to any one of claims 1 to 6, wherein: the time delay measuring circuit also comprises a calibration circuit, and the calibration circuit is used for controlling the coding circuit to output the time delay code.

9. The delay measurement circuit according to any one of claims 1 to 6, wherein: the multiphase clock signal is 2^kBit clock signals in which any adjacent single bit signals have a phase difference of

Wherein k is a natural number greater than or equal to 1, and f is the frequency of the master clock signal.

10. A method of delay measurement, comprising:

generating a delay interval signal based on the first multi-bit signal, the second multi-bit signal and the master clock signal;

latching the multi-phase clock signals based on the rising edge of the delay interval signal to obtain a latched value of the multi-phase clock signals, wherein the frequency of the main clock signal is the same as that of the multi-phase clock signals;

generating a delay code between the first multi-bit signal flip edge and the rising edge of the master clock signal or generating a delay code between the second multi-bit signal flip edge and the falling edge of the master clock signal based on the latched value.

11. The delay measurement method of claim 10,

the first multi-bit signal and the second multi-bit signal are each at the same frequency as the master clock signal,

said first multi-bit signal and said second multi-bit signal are multi-bit gray code counter signals of the same bit-width,

when generating a delay code between a flip edge of the first multi-bit signal and a rising edge of the master clock signal based on the latched value, a phase of the first multi-bit signal leads a phase of the second multi-bit signal by a phase time of

Wherein f is the frequency of the master clock signal;

when generating a delay code between a flip edge of the second multi-bit signal and a falling edge of the master clock signal based on the latched value, a phase of the first multi-bit signal lags a phase of the second multi-bit signal by a phase time of

Where f is the frequency of the master clock signal.

12. The delay measurement method of claim 11, wherein: the generating a delay interval signal based on the first multi-bit signal, the second multi-bit signal and the master clock signal includes:

generating a delayed signal based on the first multi-bit signal and the second multi-bit signal;

generating an enable signal based on the master clock signal;

and the delayed signal and the enabling signal are performed to generate the delayed interval signal.

13. The delay measurement method of claim 12, wherein: said generating a delayed signal based on said first multi-bit signal and said second multi-bit signal comprises:

performing an exclusive-or operation on the first multi-bit signal and the second multi-bit signal to generate a third multi-bit signal;

performing an OR operation on each bit signal of the third multi-bit signal to generate the delayed signal.

14. The delay measurement method of claim 12, wherein: the generating an enable signal based on the master clock signal includes:

when the phase of the first multi-bit signal leads the phase of the second multi-bit signal by the time of

Triggering a first timing circuit to output a fourth multi-bit signal according to the rising edge of the master clock signal, wherein f is the frequency of the master clock signal;

Triggering a first timing circuit to output a fourth multi-bit signal according to the falling edge of the main clock signal, wherein f is the frequency of the main clock signal;

performing an AND operation on each bit signal of the fourth multi-bit signal to generate the enable signal.

15. The delay measurement method of claim 14, wherein: after performing an and operation on each bit signal of the fourth signal to generate the enable signal, delaying the enable signal such that the delay interval signal is

16. The delay measurement method according to claim 14 or 15, characterized in that: the first time sequence circuit is an m-bit counter, wherein m is a natural number greater than or equal to 2.

17. The delay measurement method according to any one of claims 10 to 15, characterized in that: generating a delay code preamble between a rising edge of the master clock signal and a falling edge of the second multi-bit signal or between a falling edge of the master clock signal based on the latched value, further comprising calibrating the delay code.

18. The delay measurement method according to any one of claims 10 to 15, characterized in that: the multiphase clock signal is 2^kBit clock signals in which any adjacent single bit signals have a phase difference of

19. An electronic device comprising the delay measurement circuit according to any one of claims 1 to 9.

20. A chip having instructions stored therein, wherein when executed, the method of measuring delay time according to any one of claims 10 to 18 is performed.