JP2733528B2 - Partial pulse height reference frequency generator for phase locked loop - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a partial lock height type reference frequency generating circuit for a phase locked loop for generating a reference input signal of a phase locked loop.

[0002]

2. Description of the Related Art A frequency synthesizer using a phase-locked loop (PLL) uses a high-precision fixed reference frequency generator, and has been used in many fields as a means for generating almost any frequency while maintaining its frequency accuracy. Used in
And as a high-precision reference frequency generator, ambient temperature,
When it is required to maintain a constant value with respect to a wide range of circuit load, power supply voltage, etc., a combination of a so-called crystal oscillation circuit with a TTL-IC, a CMOS-IC, or the like is often used. I have. However, such a frequency synthesizer changes the frequency divider in the phase locked loop to obtain the desired output frequency, so that the loop gain changes and the settling time greatly changes depending on the frequency division ratio. . Also, fast settling
Since it is difficult to obtain stability in time, it is usually difficult to obtain an arbitrary frequency freely in such a combination by using over-damping, so it was usually necessary to use an extremely high clock source .

FIG. 9 shows a conventional example of a frequency synthesizer using a phase locked loop. That is, as is well known, the phase locked loop is composed of a phase comparator (PC) 1, a low-pass filter (LPF) 2, an amplifier (A) 3, a voltage controlled oscillator (VCO) 4, and the like. The oscillation frequency f _O of the voltage controlled oscillator 4 in the frequency synthesizer using the loop is as follows, and the single frequency from the crystal oscillation circuit 7 is determined by the division ratios m and n of the frequency division circuits 5 and 6. Various oscillation frequencies can be obtained based on the oscillation frequency fr.

[0004]

(Equation 1)

In a conventional frequency synthesizer using a phase-locked loop, since there is no requirement for high-speed settling, an arbitrary frequency can be set by a combination of the dividing ratio n in the dividing circuit 6 and the dividing ratio m in the dividing circuit 5. Is occurring. However, there is also a problem that the stability and settling time of the phase-locked loop change depending on the frequency division ratio m of the frequency divider 5 in the phase-locked loop.

For this reason, in recent years, a method for realizing a frequency synthesizer using a stable variable frequency source instead of the fixed frequency source which is the crystal oscillation circuit 7 as shown in FIG. 9 is disclosed in, for example, US Pat. No. 4,965,533. And US Patent No. 5
No. 028887 and the like. That is, a reference frequency is generated by a direct digital synthesizer (DDS) as a stable variable frequency source. A frequency synthesizer in which a phase locked loop is driven by the direct digital synthesizer, a so-called DDS drive type frequency synthesizer Is the emergence of

FIG. 10 shows a conventional example of a DDS drive type frequency synthesizer. This DDS drive type frequency synthesizer is a direct digital synthesizer 10
A phase lock loop including a phase detector 11, a loop filter 12, a voltage controlled oscillator (VOC) 13, and a fixed frequency divider 14 connecting the voltage controlled oscillator 13 and the phase detector 11 is connected to the next stage. It is the structure which was done. However, the direct digital synthesizer 10
Therefore, the desired frequency cannot be generated only by the digital circuit because the frequency step required for the operation is a decimal point dividing operation.

FIG. 11 shows the direct digital data of FIG.
FIG. 13 is a block diagram showing the synthesizer 10 in more detail, and shows an accumulator 3 composed of an accumulator (accumulator) 30a and a register 30b as shown in FIG.
The following is a description of a simplified model in which 0 is 4 bits. That is, when used in f _CL = 16MH _Z clock, setting the accumulator 30 a phase increment Δθ as binary data, the reference frequency f _R is

[0009]

(Equation 2) Given by

Therefore, in order to obtain an arbitrary frequency, the phase increment Δθ may be varied. This can be called an accumulator frequency divider.
Fig. 3 shows the frequency division mechanism and the sawtooth wave as its output waveform. As is apparent from FIG. 13, the increment value / clock differs depending on the phase increment value Δθ.

Therefore, when the phase increment value Δθ is changed from 24 ° to 44 °, the sine LUT shown in FIG.
The output waveform of the (look-up table) 31 is shown in FIG.
The digital value of the step-like sine wave shown in FIG. 4 is obtained. FIG. 15 shows the state of the clock shift based on the generated waveform with the phase increment value Δθ set to 22.5 °.

The accumulator frequency divider only functions as a periodic function generator, passes the digital value of the stepped sawtooth wave, which is the accumulator output, through the sine LUT 31, and reads the digital data value of the sine wave.

Next, the digital data value of the sine wave is applied to the D / A converter 32 in the next stage to convert the sine wave into an analog waveform, and the analog-converted output signal is converted to a high-order L in the next stage.
The signal is supplied to a PF (high-order low-pass filter) 33 to perform smoothing (interpolation) and remove a clock frequency component.

The output from the high-order LPF 33 is applied to a high-pass filter (HPF) 34 at the next stage, where the D / D
Eliminates in-band jitter due to quantization errors and other errors during A-conversion. And this high-pass filter 3
The output from 4 is converted to a digital signal again,
The signal is supplied to a high gain AC coupling comparator 35 which is connected to the next stage and includes a capacitor C and an analog voltage comparator 35a. An output signal from the AC coupling comparator 35 becomes a reference frequency output f _{R of the} direct digital synthesizer 10. , Driving the phase locked loop.

In this case, the higher the gain of the AC coupling comparator 35 is, the smaller the jitter can be.
A point, B point, C point, and D in FIG.
Each output waveform at the point (MSB at point A) is the waveform shown in FIG. Further, when the decimal point division N = 7.2, the waveform similarly becomes as shown in FIG. 17, and the waveform is different for each cycle at the same time as the start point and the end point are shifted. As shown by 18, the MSB bit output in FIG. 12 draws the same sequence every five periods, and it can be seen that periodicity exists. Therefore, if this is the case, the frequency differs for each cycle, and the reference frequency f
Since it cannot be used as _R , the signal is once converted to an analog signal using the sine LUT 31 and the D / A converter 32 to correct this. This analog signal is converted into a signal having phase continuity at the same time as the clock is removed by the subsequent high-order LPF 33. The signal is further reduced to a digital signal through the subsequent high-pass filter 34, and then converted to a digital signal again. A frequency reference signal is generated through the AC coupling comparator 35 for returning. The conventional DDS drive type frequency synthesizer that operates as described above can also divide a decimal point, so that an arbitrary frequency can be generated.

[0016]

By the way, in the direct digital synthesizer 10 shown in FIG. 11, the sign L is calculated based on the accumulated phase value regardless of the generation cycle.
The digital data value of the sine wave is read from the UT 31 to perform D / A conversion. However, a D / A converter 32 that performs this conversion requires a high-speed and high-resolution converter.
There is a problem that the cost increases. The frequency accuracy in the case of accumulator frequency division and the accumulator 30
The relationship of the bit width of

[0017]

[Equation 3] Number of bits = INT [0.5 + L _{Og 2} (1 / frequency accuracy)]

, The frequency accuracy is 1 ppm
If (10 ^-6 ), the bit width of the accumulator 30 becomes 20 bits. Since the output waveform of the D / A converter 32 is a step-like sine wave, the D / A converter 3
After 2 is a high-order LPF which is a high-performance low-pass filter
33 is required. In the near future, the reference frequency will be generated by a direct digital synthesizer using a limited number of sample pulses, and the settling time for switching the frequency with high stability in the phase locked loop will be 1 m.
The spread of digital cellular telephones, digital cordless telephones, digital PBXs, and the like that require S or less is expected.

The present invention has been made in view of such circumstances, and as a reference frequency generating circuit for driving a phase locked loop, it is possible to further increase the processing speed by hardware processing as compared with the related art. It is another object of the present invention to provide a partial pulse height type reference frequency generating circuit for a phase locked loop which is effective for reducing costs.

[0020]

In order to achieve the above object, a reference frequency signal Hig based on an MSB output signal of a phase accumulator is used to enable decimal point frequency division.
High level cycle detector for detecting h level cycle, Low level cycle detector for detecting Low level cycle of reference frequency signal, Exclusive OR of MSB output signal delayed by one clock and MSB output signal Analogly, a control unit including a zero-crossing period detector for detecting a clock period in which a true zero-crossing point located at 180 ° × n points including 0 ° is present;
The control signal from the control unit converts the digital signal of the zero-cross period into an analog signal, and applies the signal to the zero-cross period, applies a full-scale to the high-level period, and similarly applies a zero value to the low-level period. Then, a partial pulse height signal is generated, an unnecessary noise component is removed from the signal by a subsequent low-pass filter, and a true zero cross located at 180 ° × n points including 0 ° is obtained. An analog section which converts the signal into a digital signal again through a comparator, and wherein an output signal from the analog section is input to a subsequent phase-locked loop. A phase lock loop that locks or follows the reference frequency by receiving the reference frequency signal and comparing the phase with its own oscillation output waveform and controlling the oscillation output frequency in a direction to reduce the error. A phase accumulator that accumulates a phase increment value Δθ that is a set value corresponding to a given reference frequency, and an output value MS that is an accumulation result in the phase accumulator.
High for detecting High level period from B bit output
an h-level cycle detector, a low-level cycle detector for detecting a low-level cycle from an MSB bit output of an output value as an accumulation result in the phase accumulator, and an MSB
By taking an exclusive OR of the signal obtained by delaying the output signal by one clock and the MSB output signal, a clock period in which a true zero cross located at 180 ° × n points including 0 ° is detected analogously is detected. A zero-crossing period detector, a phase remainder extractor for extracting a phase remainder from the lower bit output excluding the MSB bit of the output value as the accumulation result in the phase accumulator, and an output of the phase remainder extraction result. Switch means for selecting a zero-cross period from L → H and a zero-cross period from H → L based on the phase increment value Δθ, and 180 ° × n including 0 ° within the zero-cross period A scaler for scaling the preceding or following data with reference to the true zero crossing located at the point, and the preceding or following data of the above zero crossing period The input to scaling unit, a D / A converter which converts the output into an analog signal,
The analog signal output converted by the D / A converter is applied to a zero-cross period, a full-scale is applied to a high-level cycle, and a zero value is similarly applied to a low-level cycle to generate a partial pulse height signal. A low-pass filter that makes this a sine wave free of clock noise, an output signal from the low-pass filter, and a high-pass filter that removes a subharmonic component of the output signal; An output signal from the band-pass filter is input, and a comparator for converting the output signal into a digital signal as a reference frequency signal is provided. The reference frequency signal is output to the phase lock loop as the reference frequency, thereby driving the phase lock loop. Is performed. Minute pulse height type reference frequency generation circuit. Also, a digital circuit means for performing a pipeline delay in accordance with the number of waveform generation samples is provided before the D / A converter, or a three-series buffer is provided before the D / A converter to provide an output. Each signal sequence can be selected by an enable signal.

[0021]

According to the present invention, when a phase increment Δθ, which is a set value corresponding to a reference frequency to be generated, is given to a phase accumulator, a digital signal as a stepped sawtooth wave is generated as an accumulator frequency divided output. And
From the MSB bit output of the phase accumulator output,
The detection of the high level period is performed in the same manner as the Lo level period.
The detection of whether or not the period is the w-level period is also performed for the zero-cross period. Further, the low-order bit output of the phase accumulator output excluding the MSB bit output is recorded and held by extracting a phase surplus value based on the detected value of the above-mentioned zero cross period. It is converted to a value (at 180 ° H → L) or a phase remainder value (a
t0 ° or 360 ° L → H) itself is selected and output as a scaling value by the scaling device, and the value is given to the D / A converter within the zero cross period.

The output signal from the D / A converter is applied during a zero-cross period, and a full-scale cycle is applied to a high-level cycle and a zero value is applied to a low-level cycle to generate a partial pulse height waveform output signal. The signal is input to a steep low-pass filter and output as a clean sine wave without clock noise, and is input to a high-pass filter to remove subharmonics. The signal is converted to a signal and input to the phase-locked loop.
This will drive the loop. When the pipeline delay circuit means is inserted before the D / A converter, it works so as to reduce the speed of the D / A converter in the next stage.

Next, a preferred embodiment of the present invention will be described with reference to the accompanying drawings. FIG. 1 is a block diagram showing a basic configuration of the present invention, which is roughly divided into a control unit 40 and an analog unit 50. That is, the control unit 4
0 is provided with a phase accumulator 41 to which a phase increment value Δθ is inputted as a set value corresponding to a reference frequency to be generated, and a High level cycle detector 42, L
ow level period detector 43, zero cross period detector 4
4 are connected. Separately from this, a phase remainder value extractor 45 (V
_CC = post data) and a subtracter (Δθ) between the output of the phase remainder value extractor 45 and the phase increment value Δθ
−V _ACC = previous data) 46 is connected. Reference numeral 47 denotes a scaling unit (V _ACC / Δθ) for adjusting the analog voltage of the High level cycle and the Low level cycle to the scaling of the analog voltage of the data before or after given to the zero-cross cycle. The analog unit 50 includes a High level cycle detector 42, a Low level cycle detector 43, a zero
And switch _(SW 1 ~SW ₃₎ is provided which is controlled by the output signal from the cross period detector 44 _also has a buffer 51 which receives an input signal inputted via the SW 1 to SW _3, A low-pass filter (LPF) 52 and a high-pass filter (H
PF) 53 and a comparator 54 are connected. 55
Is a D / A converter, which converts the values of the scaling unit 47 and the reference voltage source V _REF from digital to analog to S
And outputs it to the W _3.

Next, the operation of the control unit 40 will be described with reference to the circuit diagram shown in FIG. FIG. 3 is a timing chart of an output waveform inside the control unit 40. The phase increment value Δθ as a set value corresponding to the reference frequency to be generated is given to a phase accumulator 41 composed of an accumulator (ALU) 41a and a register 41b as a accumulator to obtain a divided output. MSB, MSB of the digital signal which is the accumulator frequency divided output
The 1-bit waveform is converted to a D flip-flop (D-F
F) 401, NAND (NAND) 402, Noah (NO)
R) High level period detector 42 composed of 403
Thus, an output signal having a High level period is generated. This High level period signal has the waveform shown in FIG. 3F.
Similarly, a D flip-flop (D-FF) 401 and a NAND (NAND) based on the MSB, MSB-1 bit output
An output signal, which is a Low-level period signal, is generated by a Low-level period detector 43 composed of a 402 and an OR (OR) 404. This Low level period signal has the waveform shown in FIG. 3G. Furthermore, a D flip-flop (D-FF) 40 based on the MSB, MSB-1 bit output.
1, NAND (NAND) 402, inverter (INV)
An output signal which is a zero-cross period signal is generated by a zero-cross period detector 44 constituted by 405. This zero-crossing period signal has the waveform shown in FIG. 3e. FIG. 3A
Indicates the waveform of the system clock. FIG. 3B shows the waveform of the MSB. FIG. 3C shows the waveform of MSB-1. FIG. 3D
Outputs the MSB-1 bit output to the D flip-flop (D-
FF) 401 indicates that the waveform is delayed by one clock of the system clock.

Incidentally, the accumulator frequency-divided output becomes (H →) at the end of the zero-cross cycle period shown in FIG.
L) or (L → H), but the true zero cross (0 °, 180 °,
That is, FIG. 7 shows how much the position is shifted from the position of 180 ° × n including 0 °) and the start and end of the zero-cross period. The table of FIG. 7 shows an example when Δθ is 50 °. From this table, the zero cross in the case of 0 ° in the first cycle has no deviation, and thus rises to the High level as it is. It can be seen that the zero cross in the case of に な る is at the position of 20 ° before the MSB bit inversion. When there is a true zero cross at 180 °, the clock advances from 150 ° to 200 °, so that the front / rear duty ratio is 30:20. (H → L)
In the case of the cross, the output signal of the subtractor 46 that outputs the operation result of the previous data (Δθ−V _ACC ) is selected and input to the scaling unit 47. In the case of 30:20, the scaling unit 47 performs scaling as an amplitude level of 30/50, and sets this scaling value to zero.
Input is made to the D / A converter 55 of the next stage only during the cross period.

It can be seen from the table of FIG. 7 that the zero cross at 0 ° in the second cycle is advanced by 40 °. In this case, the front / rear duty ratio in the clock is 10:40.
In the case of (L → H) cross, the post data (V _ACC ) signal is selected and input to the scaling unit 47. Similarly, the scaling unit 47 uses 40/5 for 10:40.
The scaling is performed as an amplitude level of 0, and this scaling value is input to the D / A converter 55 of the next stage only during the zero-cross period. That is, (H
In the case of (L) cross, the previous data of the front / rear duty ratio is scaled and applied to the D / A converter 55 of the next stage during the zero cross period, and in the case of (L → H) cross, the front / rear duty ratio is calculated. The subsequent data is scaled and applied to the D / A converter 55 in the next stage during the zero cross period. Further, during the High level period, “H” level data is
During the Low level period, the “L” level data is transferred to this D / A
This is given to the converter 55.

Thus, the waveform input to the D / A converter 55 of the analog section 50 is as shown in FIG. 8, and the previous data is generated by the subtractor 46 as the previous data = (Δθ−post data). The signal of FIG. 8 is digital-to-analog converted by a D / A converter 55, input to a low-pass filter (LPF) 52 at the next stage, and further input to a high-pass filter (HPF) 55 at the next stage. Becomes After unnecessary components are removed by these two-stage filters 52 and 53, they are input to a comparator 54 and converted into a digital signal f _R as a reference frequency signal, and drive a phase lock loop (not shown) at a subsequent stage. Will be done.

As shown in FIG. 1, in order to reduce the load on the D / A converter 55, the signals from the high-level cycle detector 42 and the low-level cycle detector 43 are directly supplied to the analog switch, and the signals are set to zero. A partial pulse height waveform can be generated by adding the cross period detector 44, the scaling unit 47, and the analog signal supplied from the D / A converter 55. To match the operation timings of the switches SW ₁ to SW ₃ and D / A converter 55, D latch 410 is a digital circuit means for causing pipe line delay
To 417 may be inserted to reduce the sampling rate of the D / A converter 55. Also,
The analog section 50 includes buffers 500 to 5 in front of the D / A converter 55 as shown in FIG.
02 may be provided, and each signal sequence may be selectively input to the D / A converter 55 by output enable. In this case, the High level cycle detector 42
Outputs a signal indicating a High level period. When this output signal is "1", a digital signal for setting all bits to "H" level is supplied to the input line of the D / A converter 55. In addition, since the High level is exactly the level of 2 ⁿ −1, an error of 2 ⁿ − (2 ⁿ −1) is included in the High level. For this reason, at the High level, MSB is increased by one bit to be 1, and lower data excluding the MSB is made to correspond to all zeros. Low level cycle detector 43
Outputs a signal indicating a Low level period. When this output signal is "1", a digital signal for setting all bits to "L" level is applied to the input line of the D / A converter 55.

Further, since the zero-cross period detector 44 outputs a signal indicating the zero-cross period, when the output signal is "1", the output from the scaling unit 47 is applied to the input line of the D / A converter 55. A digital signal corresponding to the scaled value is given. As can be seen from FIG. 6, the High level period, the zero cross period, L
Since the ow level period and the zero-cross period are sequentially repeated, these periods do not exist at the same time.
Therefore, the output signal of the high-level cycle detector 42, the output signal of the low-level cycle detector 43, and the output signal of the zero-cross period detector 44 do not simultaneously become "1". All bits of the input line of the A converter 55 are “H” during a High level period.
All bits are selectively input to the D / A converter 55 in sequence during the Low level period, and all bits are set to the “L” level during the zero cross period.

[0030]

As described above, the reference frequency generation circuit of the phase locked loop according to the present invention does not use a sine LUT after a phase accumulator as in the prior art. Since a D / A converter with high speed and high resolution is not required, any frequency for driving the phase locked loop can be easily generated while reducing cost. In addition, since the signal having a digital value and the signal having an analog value are sequentially selectively switched to generate a partial pulse height waveform, the area of each cycle of the generated frequency can be all equal, and the signal can be passed to a subsequent filter group. It is possible to obtain a clear comparator output waveform without jitter. As described above, the partial pulse height type reference frequency generation circuit for the phase locked loop according to the present invention is very important because it provides a technique for compensating the generation of the reference frequency in which only a small number of sampling pulses can be used in the generation cycle. Digital cellular telephones, digital cordless telephones, and the like, which require highly stable and frequency-switching settling times of 1 ms or less in the near future.
This is particularly effective for digital PBX applications and the like.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic configuration of the present invention.

FIG. 2 is a circuit diagram showing one embodiment of a control unit according to the present invention.

FIG. 3 is a diagram showing timing of an output waveform inside a control unit.

FIG. 4 is a block diagram showing another embodiment of the analog unit in the present invention.

FIG. 5 is an MSB bit output waveform diagram of an accumulator frequency divider output at the time of decimal point frequency division.

FIG. 6 is an explanatory diagram that defines each cycle in an accumulator frequency divider output signal.

FIG. 7 is a diagram showing a deviation between each zero cross and a target zero cross.

FIG. 8 is a diagram showing an output waveform of a partial pulse height type.

FIG. 9 is a block diagram of a conventional frequency synthesizer using a phase locked loop.

FIG. 10 is a block diagram showing a conventional DDS drive type frequency synthesizer.

FIG. 11 is a block diagram showing details of a direct digital synthesizer in FIG. 10;

FIG. 12 is an explanatory diagram in which the accumulator portion of FIG. 11 is simplified to 4 bits.

FIG. 13 is a diagram illustrating a mechanism of accumulator frequency division.

14 is a diagram showing a generated waveform based on a clock of the direct digital synthesizer in FIG.

FIG. 15 is a diagram showing a clock shift based on a generated waveform.

FIG. 16 is a waveform chart in the case of integer frequency division.

FIG. 17 is a waveform chart in the case of decimal point division.

FIG. 18 is an MBS output waveform chart in the case of decimal point frequency division.

[Explanation of symbols]

 REFERENCE SIGNS LIST 40 Control unit 41 Phase accumulator 42 High level cycle detector 43 Low level cycle detector 44 Zero cross period detector 45 Phase remainder value extractor 46 Subtractor 50 Analog unit 52 Low pass filter 53 High pass filter 54 Comparator

Claims (4)

(57) [Claims] 1. A high-level period detector for detecting a high-level period of a reference frequency signal based on an MSB output signal of a phase accumulator and a low-level period of the reference frequency signal to enable decimal point frequency division. L
ow level cycle detector, delays MSB output signal by one clock
Exclusive ON of extended signal and MSB output signal
And place it at 180 ゜ × n point including 0 ゜
A control unit composed of a zero-cross period detector that detects a clock period in which a true zero-cross exists, and a digital signal of the zero-cross period converted from analog to analog by a control signal from the control unit. A signal is provided during the zero crossing period, a full scale is applied to the High level period, and a zero value is similarly applied to the Low level period to generate a partial pulse height signal. An analog section which removes by a band-pass filter and obtains a true zero cross located at 180 ° × n points including 0 °, and then converts it again into a digital signal through an analog comparator; A part for a phase locked loop, wherein an output signal is input to a subsequent phase locked loop. Pulse height type reference frequency generation circuit. 2. A phase for locking or following the reference frequency by receiving the reference frequency signal and comparing the phase with its own oscillation output waveform and controlling the oscillation output frequency in a direction to reduce the error. In the reference frequency generation circuit of the lock loop, a phase increment value Δ which is a set value corresponding to a given reference frequency.
a phase accumulator for accumulating θ, and an H for detecting a High level period from an MSB bit output of an output value as an accumulation result in the phase accumulator.
An output level which is an accumulation result in the high level period detector and the phase accumulator.
Lo for detecting Low level period from MSB bit output
w-level period detector, MSB output signal delayed by one clock and MSB output
By taking the exclusive or of the force signal,
True zero cross , standing at 180 ° × n points including 0 °
A zero-cross period detector for detecting a clock period in which a phase difference exists; a phase remainder extractor for extracting a phase remainder from lower bit outputs excluding MSB bits of an output value as an accumulation result in the phase accumulator; Output of extra phase extraction result and the above phase increment value Δθ
Based on the door, zero-cross period to the L → H and H → L
Switch means for selecting a zero-cross period to a point, and 180 ° × n points including 0 ° within the zero-cross period
A scaler for scaling the preceding or succeeding data with reference to the true zero crossing, and a D / D for inputting the preceding or following data of the zero-crossing period to the scalingr and converting the output to an analog signal. An A converter and an analog signal output converted by the D / A converter are provided in a zero cross period, a high level cycle is given a full scale, and a low level cycle is given a zero value in the same manner. A low-pass filter that generates a height signal and converts the signal into a sine wave having no clock noise; a high-pass filter to which an output signal from the low-pass filter is input and that removes a subharmonic component of the output signal And an output signal from the high-pass filter is input, and this is used as a reference frequency signal to generate a digital signal. A phase-locked loop-type partial pulse height reference frequency, wherein the reference frequency signal is output as a reference frequency to a phase-locked loop to drive the phase-locked loop. Generator circuit. 3. The partial pulse height type for a phase locked loop according to claim 2, further comprising digital circuit means for performing a pipeline delay in accordance with the number of waveform generation samples before the D / A converter. Reference frequency generation circuit. 4. The system according to claim 2, wherein three series of buffers are provided in a preceding stage of the D / A converter, and each signal series can be selected by an output enable signal.
A partial pulse height type reference frequency generator for a phase locked loop as described.