JPH0629745A - Partial pulse height type reference frequency generating circuit for phase locked loop - Google Patents

Abstract

PURPOSE:To provide the partial pulse height type reference frequency generating circuit for phase locked loop which has a reference frequency generating circuit driving a phase locked loop and can increase the hardware processing speed in comparison with conventional circuit and is effective to reduce the cost. CONSTITUTION:This circuit consists of a control part 40 and an analog part 50, and the control part 40 generates a digital signal synthesized by a high level period detector 42 which detects the high level period of a reference input signal based on an output signal capable of decimal point frequency division, a low level period detector 43 which detects the low level period, a zero-crossing period detector 44 which detects the zero-crossing period, or the like, and the analog part 50 converts the digital signal from the control part 40 into an analog signal and converts it into a digital signal again after eliminating unnecessary noise components, and the output signal from the analog part 50 is inputted to the phase locked loop.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase-locked loop partial pulse height type reference frequency generating circuit for generating a reference input signal of a phase-locked loop.

[0002]

2. Description of the Related Art A frequency synthesizer using a phase-locked loop (PLL) uses a high-precision fixed reference frequency generator and has been used in many fields as a means for generating almost any frequency with its frequency accuracy maintained. It is used in.
Then, as a highly accurate reference frequency generator, the ambient temperature,
When it is required to maintain a constant value for a wide range of fluctuations in circuit load and power supply voltage, a so-called crystal oscillation circuit combined with a TTL-IC or CMOS-IC is often used. There is. However, in such a frequency synthesizer, the frequency divider in the phase-locked loop is varied to obtain the desired output frequency, so that the loop gain changes and the settling time greatly changes depending on the frequency division ratio. . Also, fast settling
Since it is difficult to obtain stability in time, it is usually difficult to use it with over-damping, and it is difficult to obtain any frequency freely in such a combination, so it was usually necessary to use an extremely high clock source. .

FIG. 9 shows a conventional example of a frequency synthesizer using a phase locked loop. That is, as is well known, the phase lock loop is composed of a phase comparator (PC) 1, a low pass filter (LPF) 2, an amplifier (A) 3, a voltage controlled oscillator (VCO) 4, etc. The oscillation frequency f _O of the voltage controlled oscillator 4 in the frequency synthesizer using the loop is as follows, and the frequency division ratios m and n of the frequency division circuits 5 and 6 respectively cause the single oscillation from the crystal oscillation circuit 7. Various oscillation frequencies can be obtained based on the oscillation frequency fr.

[0004]

[Equation 1]

Since the conventional frequency synthesizer using the phase-locked loop does not require high-speed settling, any frequency can be selected by combining the frequency division ratio n in the frequency division circuit 6 and the frequency division ratio m in the frequency division circuit 5. Has been generated. However, there is also a problem in that the stability and settling time of the phase-locked loop change depending on the frequency division ratio m of the frequency dividing circuit 5 in the phase-locked loop.

Therefore, in recent years, a method of realizing a frequency synthesizer using a stable variable frequency source instead of the fixed frequency source which is the crystal oscillation circuit 7 as shown in FIG. 9 has been disclosed in, for example, US Pat. No. 4,965,533. And US Patent No. 5
No. 028887 has been proposed. That is, a reference frequency is generated by a direct digital synthesizer (DDS) as a stable variable frequency source, and a frequency synthesizer that drives a phase locked loop by this direct digital synthesizer, a so-called DDS drive type frequency synthesizer. Is the appearance of.

FIG. 10 shows a conventional example of a DDS drive type frequency synthesizer. This DDS drive type frequency synthesizer is a direct digital synthesizer 10
The phase-locked loop including the phase detector 11, the loop filter 12, the voltage controlled oscillator (VOC) 13, and the fixed frequency divider 14 connecting the voltage controlled oscillator 13 and the phase detector 11 is connected to the next stage of It has been configured. However, direct digital synthesizer 10
Since the frequency step required for 1 is a decimal point frequency division operation, the desired frequency cannot be generated only by the digital circuit.

FIG. 11 shows the direct digital circuit of FIG.
FIG. 13 is a block diagram showing the synthesizer 10 in more detail. As shown in FIG. 12, the synthesizer 10 is composed of an accumulator (accumulator) 30a and a register 30b.
The following is a description of a simplified model in which 0 is 4 bits. That is, when f _CL = 16 MH _Z clock is used, when the phase increment value Δθ is set in the accumulator 30 as binary data, the reference frequency f _R becomes

[0009]

[Equation 2] Given in.

Therefore, in order to obtain an arbitrary frequency, the phase increment value Δθ may be varied. This can be said as an accumulator frequency divider, as shown in FIG.
Shows the frequency division mechanism and the sawtooth wave which is the output waveform. As is apparent from FIG. 13, the increment value / clock differs depending on the phase increment value Δθ.

Therefore, when the phase increment value Δθ is changed from 24 ° to 44 °, the sine LUT shown in FIG.
The output waveform of the (lookup table) 31 is shown in FIG.
The digital value of the stepped sine wave shown in 4 is obtained. Then, FIG. 15 shows a state of clock shift based on the generated waveform with the phase increment value Δθ set to 22.5 °.

This accumulator frequency divider functions as a periodic function generator, and passes the digital value of the staircase sawtooth wave, which is the output of the accumulator, through the sine LUT 31 to read the digital data value of the sine wave.

Next, the digital data value of the sine wave is applied to the D / A converter 32 in the next stage to be converted into an analog waveform, and the analog-converted output signal is output in the higher order L in the next stage.
It is applied to a PF (high-order low-pass filter) 33 to perform smoothing (interpolation) and remove clock frequency components.

The output from the high-order LPF 33 is given to the high-pass filter (HPF) 34 at the next stage, and the D /
In-band jitter due to quantization error and other errors during A conversion is removed. And this high pass filter 3
The output from 4 is converted to a digital signal again,
The output signal from the AC coupling comparator 35, which is connected to the next stage and is composed of the capacitor C and the analog voltage comparator 35a, having a high gain, is the reference frequency output f _{R of the} direct digital synthesizer 10. , Will drive the phase-locked loop.

In this case, the higher the gain of the AC coupling comparator 35, the smaller the jitter, and the integer frequency division N =
In the case of 64, points A, B, C, and D in FIG.
Each output waveform at the point (MSB at point A) becomes the waveform shown in FIG. Further, when the decimal point division N = 7.2 is set, the waveform becomes like that shown in FIG. 17, and the waveform changes every cycle at the same time when the start point and the end point shift. As shown by 18, the MSB bit output in FIG. 12 draws the same sequence every 5 cycles, so it can be seen that there is periodicity. Therefore, if this is left as it is, the frequency is different for each cycle, and the reference frequency f
Since it cannot be used as _R, it is once converted into an analog signal by using the sine LUT 31 and the D / A converter 32 in order to correct this. Then, the analog signal is made into a signal having phase continuity at the same time as the clock is removed by the subsequent high-order LPF 33, and the signal is further reduced in jitter through the subsequent high-pass filter 34, and then converted into a digital signal again. A frequency reference signal is generated through an AC coupled comparator 35 for return. Since the conventional DDS drive type frequency synthesizer which operates in this way is also capable of dividing the decimal point, it is possible to generate an arbitrary frequency.

[0016]

By the way, in the direct digital synthesizer 10 shown in FIG. 11, the sine L is calculated based on the accumulated phase value regardless of the generation period.
The sine wave digital data value is read from the UT 31 and D / A conversion is performed. However, since the D / A converter 32 that performs this conversion needs to have high speed and high resolution,
There is a problem that the cost increases. The frequency accuracy and the accumulator 30 in the case of the accumulator frequency division
The bit width relationship of

[0017]

[Equation 3] Number of bits = INT [0.5 + L _{Og 2} (1 / frequency accuracy)]

Since the frequency accuracy is 1 ppm,
If it is (10 ⁻⁶ ), the bit width of the accumulator 30 becomes 20 bits. Further, since the output waveform of the D / A converter 32 is a stepped sine wave, the D / A converter 3
Higher-order LPF that is a high-performance low-pass filter after 2
33 is required. However, in the near future, the reference frequency is generated by a direct digital synthesizer using a limited number of sample pulses, and the settling time for frequency switching the phase lock loop with high stability is 1 m.
It is expected that digital cellular telephones, digital cordless telephones, digital PBXs, and the like that require S or less will become popular.

The present invention has been made in view of the above circumstances, and as a reference frequency generation circuit for driving a phase locked loop, higher speed processing can be achieved by hardware processing as compared with the prior art. Another object of the present invention is to provide a partial pulse height type reference frequency generation circuit for a phase locked loop, which is effective for cost reduction.

[0020]

In order to achieve the above object, in order to enable division of a decimal point, a high frequency of a reference frequency signal is generated based on an MSB output signal of a phase accumulator.
High level cycle detector for detecting the h level cycle, L
A control unit composed of a Low level period detector for detecting a low level period and a zero cross period detector for detecting a zero cross period, and a digital signal of the zero cross period is analogized by a control signal from the control unit. The signal is converted, and the signal is applied to the zero-cross period, the high-level period is given a full scale, and the low-level period is similarly given a zero value to generate a partial pulse height signal. Is removed by a subsequent low-pass filter and is then converted into a digital signal again through an analog comparator, and the output signal from the analog section is input to a phase lock loop at a subsequent stage. To do. Also, at the same time as receiving the reference frequency signal, it compares the phase with its own oscillation output waveform, and controls the oscillation output frequency in the direction of reducing the error to lock or follow the reference frequency. In the reference frequency generation circuit, a high level cycle is detected from the phase accumulator that accumulates the phase increment value Δθ that is the set value corresponding to the given reference frequency and the MSB bit output of the output value that is the accumulation result of this phase accumulator. High level cycle detector, Low level cycle detector for detecting Low level cycle and zero
A zero-cross period detector that detects a cross period, a phase remainder value extractor that extracts a phase remainder value from the lower bit output except the MSB bit of the output value that is the accumulation result in the phase accumulator, and the phase remainder Based on the output of the value extraction result and the phase increment value Δθ, L →
Switch means for generating H and H → L zero cross signals, a scaling device for scaling the front data or the back data based on the true zero cross within the zero cross period, and the zero cross period D / A converter for inputting the pre-data or post-data of the above into a scaling device and converting the output thereof into an analog signal;
The analog signal output converted by the converter is applied to the zero-cross period, the full scale is applied to the high level period, and the zero value is applied to the low level period in the same manner to generate the partial pulse height waveform output signal, which is clocked. -A low-pass filter that produces a sine wave with no noise, and a high-pass filter that receives the output signal from the low-pass filter and removes the subharmonic component of this output signal, and the high-pass filter from the high-pass filter. The output signal is input, and it is composed of a comparator that converts this into a digital signal as a reference frequency signal, and outputs the reference frequency signal as a reference frequency to the phase lock loop to drive the phase lock loop. Characterize.
Further, it is characterized in that a digital circuit means for performing pipeline delay according to the number of samples of waveform generation is provided in the preceding stage of the D / A converter, or in the preceding stage of the D / A converter.
A series buffer is provided so that each signal series can be selected by an output enable signal.

[0021]

According to the present invention, when the phase increment value Δθ which is the set value corresponding to the reference frequency to be generated is given to the phase accumulator, a digital signal as a stepped sawtooth wave is generated as the accumulator frequency division output. And
From the MSB bit output of the phase accumulator output,
Similarly, the detection of whether or not it is the high level period is performed by Lo
The zero cross period is also detected to detect whether or not it is the w level period. Further, the low-order bit outputs other than the MSB bit output of the phase accumulator output are recorded / held by extracting the phase remainder value according to the detection value of the zero cross period described above. The value (at 180 ° H → L) of the result calculated by the subtractor or the phase remainder value (a
(t0 ° or 360 ° L → H) itself is selected and output as a scaling value by the scaling device, and the value is given to the D / A converter within the zero crossing period.

The output signal from the D / A converter is applied to the zero crossing period, the high level period is subjected to the full scale, and the low level period is applied to the zero value in the same manner to generate the partial pulse height waveform output signal. Then, the signal is input to a steep low-pass filter and is output as a clean sine wave with no clock noise, and is input to a high-pass filter to remove subharmonics, and the comparator is used as a digital reference frequency signal. The signal is converted to a signal and input to the phase-locked loop.
It will drive the loop. Further, when the pipeline delay circuit means is inserted and arranged in the preceding stage of the D / A converter, it works to reduce the speed of the D / A converter in the next stage.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will now be described with reference to the accompanying drawings. FIG. 1 is a block diagram showing the basic configuration of the present invention, which is roughly divided into a control section 40 and an analog section 50. That is, the control unit 40 is provided with the phase accumulator 41 to which the phase increment value Δθ is input as the set value corresponding to the reference frequency to be generated, and the High level period detector 42, Lo is provided at the subsequent stage.
w level period detector 43, zero cross period detector 44
Are connected. Separately from this, the phase remainder value extractor 45 (V _CC
= After data) is connected and the phase remainder value extractor 4
Of the output of FIG. 5 and the phase increment value Δθ (Δθ-V
_ACC = previous data) 46 is connected. Reference numeral 47 is a scaling unit (V _ACC / Δθ) for adjusting the scaling of the analog voltage of the High level cycle and the Low level cycle and the analog voltage of the previous data or the subsequent data given to the zero crossing period. The analog section 50 is provided with switches (SW _{1 to} SW ₃ ) controlled by output signals from the high level cycle detector 42, the low level cycle detector 43, and the zero-cross period detector 44 of the control section 40. , Again SW ₁ ~ S
A buffer 51 that receives an input signal that is input via W _3.
A low pass filter (LPF) 52, a high pass filter (HPF) 53, and a comparator 54 are connected to the subsequent stage of the buffer 51. Reference numeral 55 denotes a D / A converter, which is a scaling device 47 and a reference voltage source V _REF.
The value of is converted from digital to analog and output to SW ₃ .
Next, the operation of the control section 40 will be described with reference to the circuit diagram shown in FIG. Note that FIG. 3 shows the control unit 40.
FIG. 6 is a timing diagram of output waveforms in the inside of the. The phase increment value Δθ is set as a set value corresponding to the reference frequency to be generated, and an accumulator (ALU) 41 that is an accumulator is used.
It is applied to the phase accumulator 41 composed of a and a register 41b to obtain a frequency-divided output. The waveform of the MSB bit of the digital signal which is the frequency-divided output of the accumulator is inverted by the inverter 400 to obtain the waveform shown in FIG. 3A. Then, the MSB bit output is output to the inverter 4
D flip-flop (D-FF) 4
01, Exclusive OR (EX-OR) Gate 4
02, inverter 403, and (AND) gate 40
In the high level period detector 42 configured by
An output signal which is a gh level period signal is generated. This Hi
The gh level period signal has the waveform shown in FIG. 3D. Similarly, based on the MSB bit output, an inverter 400, a D flip-flop (D-FF) 401, an exclusive
A low level period detector 43 composed of an OR (EX-OR) gate 402 and a NOR (NOR) gate 405,
An output signal that is a low level period signal is generated. This L
The ow level period signal has the waveform shown in FIG. 3E.

Further, the inverter 400 and the D flip-flop (D-FF) 4 are also based on the MSB bit output.
01, Exclusive OR (EX-OR) Gate 4
A zero-crossing period detector 44 constituted by 02 generates an output signal which is a zero-crossing period signal. This zero
The cross period signal has the waveform shown in FIG. 3C. In the waveform shown in FIG. 3B, the MSB bit output is output from the inverter 40.
Invert at 0 and D flip-flop (D-FF)
Reference numeral 401 indicates that the waveform is delayed by one clock of the system clock. The waveform shown in FIG. 3F is the lower bits except the MSB bit of the above accumulator frequency division output, that is, (MSB-1) bit to LSB.
Waveform up to bit is shown. Then, using the zero-cross period signal as a trigger signal, the lower bit output signal excluding the MSB bit of the accumulator frequency division output is fetched into the D latch 45 and used as the V _ACC signal.

By the way, the accumulator frequency-divided output is (H → H) at the end of the zero-cross period period shown in FIG.
MSB changes to L) or (L → H), but the true zero cross (0 °, 180 °) within the zero cross period
The table in FIG. 7 shows how much the time is different from the start and end of the zero-cross period. The table in Figure 7 is Δ
An example of the case where θ is 50 ° is shown. From this table, there is no deviation in the zero cross in the case of the first cycle of 0 °, so it rises to High level as it is, but 180 °
In case of 0 is before MSB bit inversion 2
It can be seen that the position is 0 °. True zero at 180 °
When there is a cross, the clock advances from 150 ° to 200 °, so the front / rear duty ratio is 30:20. (H
→ L) In the case of cross, the output signal of the subtractor 46 that outputs the calculation result of the previous data (Δθ−V _ACC ) is selected and input to the scaling unit 47. In the scaler 47, in the case of 30:20, scaling is performed as an amplitude level of 30/50, and this scaling value is set to zero.
Input is made to the D / A converter 55 at the next stage only during the cross period.

It can be seen from the table of FIG. 7 that the zero cross in the case of 0 ° in the second cycle is advanced by 40 °. In this case, the front / rear duty ratio in the clock is 10:40,
In the case of (L → H) cross, the post data (V _ACC ) signal is selected and input to the scaling unit 47. Similarly, in the scaling device 47, in the case of 10:40, 40/5
Scaling is performed as an amplitude level of 0, and this scaling value is input to the D / A converter 55 in the next stage only during the zero crossing period. That is, (H
→ In the case of L) cross, the front data of the front / rear duty ratio is scaled and given to the D / A converter 55 in the next stage during the zero crossing period, and in the case of (L → H) cross, the front / rear duty ratio The post data is scaled and given to the D / A converter 55 at the next stage during the zero cross period. Further, during the High level period, the “H” level data is
During the Low level period, "L" level data is transferred to this D / A
It will be given to the converter 55.

Thus, the waveform input to the D / A converter 55 of the analog section 50 has a waveform as shown in FIG. 8, and the previous data is created by the subtractor 46 as previous data = (Δθ−post data). The signal in FIG. 8 is digital-analog converted by the D / A converter 55, input to the low pass filter (LPF) 52 in the next stage, and further input to the high pass filter (HPF) 55 in the next stage. Becomes After the unnecessary components are removed by these two-stage filters 52 and 53, they are input to the comparator 54 and converted into a digital signal f _R as a reference frequency signal, which drives a phase-locked loop at the latter stage (not shown). Will be done.

As shown in FIG. 1, in order to reduce the load on the D / A converter 55, the signals from the high level period detector 42 and the low level period detector 43 are directly applied to the analog switch, and zero is applied to the analog switch. The partial pulse height waveform can be generated by adding the analog signals provided from the D / A converter 55 and the cross period detector 44 and the scaling device 47. A D-latch 410 which is a digital circuit means for performing a pipeline delay in order to match the operation timing of each of the switches SW _{1 to} SW ₃ and the D / A converter 55.
˜417 may be inserted and arranged to reduce the sampling rate of the D / A converter 55. Also,
In addition to the configuration shown in FIG. 1, the analog section 50 has buffers 500 to 5 in front of the D / A converter 55 as shown in FIG.
02 may be provided in three series, and each signal series may be selectively input to the D / A converter 55 by output enable. In this case, the high level period detector 42
Outputs a signal indicating a High level period, and when this output signal is "1", a digital signal for setting all bits to "H" level is applied to the input line of the D / A converter 55. Incidentally, since the level of the High-level 2 ⁿ -1 exactly 2 ⁿ - error of (2 ⁿ -1) are included in the High level. Therefore, at the High level, the MSB is increased by 1 bit and the lower data excluding the MSB is set to all zeros to correspond. Low level period detector 43
Outputs a signal indicating a Low level period, and when this output signal is "1", a digital signal for setting all bits to "L" level is applied to the input line of the D / A converter 55.

Further, since the zero-cross period detector 44 outputs a signal indicating the zero-cross period, when this output signal is "1", the scaling unit 47 outputs it to the input line of the D / A converter 55. It will give a digital signal which is the scaled value. As can be seen from FIG. 6, High level period, zero cross period, L
Since the ow level period and the zero-cross period are sequentially repeated, these periods do not exist at the same time.
Therefore, since the output signal of the high level period detector 42, the output signal of the low level period detector 43, and the output signal of the zero cross period detector 44 do not simultaneously become "1", D / All the bits of the input line of the A converter 55 are “H” during the high level period.
The level, all the bits at the “L” level during the Low level period, and the scaling value during the zero-cross period are sequentially and selectively input to the D / A converter 55.

[0030]

As described above, since the reference frequency generating circuit of the phase locked loop according to the present invention does not use the sine LUT after the phase accumulator as in the conventional case, the ROM having a huge capacity to refer to the LUT is used. , And a high-speed, high-resolution D / A converter is not required, it is possible to easily generate an arbitrary frequency for driving the phase-locked loop while reducing the cost. In addition, since the partial pulse height waveform is generated by selectively selectively switching between the digital value signal and the analog value signal, the area of each cycle of the generated frequency can be made equal and can be passed to the subsequent filter group. It is possible to obtain a clean comparator output waveform without jitter. As described above, the partial pulse height type reference frequency generation circuit for the phase locked loop according to the present invention is very important because it provides a technique for compensating the generation of the reference frequency in which only a few sampling pulses can be used in the generation period. , A digital cellular phone, a digital cordless phone, which requires a stable and highly stable frequency switching settling time of 1 mS or less in the near future.
It is particularly effective for digital PBX applications and the like.

[Brief description of drawings]

FIG. 1 is a block diagram showing the basic configuration of the present invention.

FIG. 2 is a circuit diagram showing an embodiment of a control unit according to the present invention.

FIG. 3 is a diagram showing timing of output waveforms inside a control unit.

FIG. 4 is a block diagram showing another embodiment of the analog section in the present invention.

FIG. 5 is an MSB bit output waveform diagram of an accumulator frequency divider output during decimal point frequency division.

FIG. 6 is an explanatory diagram that defines each cycle in the output signal of the accumulator frequency divider.

FIG. 7 is a diagram showing a deviation between each zero cross and a target zero cross.

FIG. 8 is a diagram showing an output waveform of a partial pulse height type.

FIG. 9 is a block diagram of a conventional frequency synthesizer using a phase-locked loop.

FIG. 10 is a block diagram showing a conventional DDS drive type frequency synthesizer.

11 is a block diagram showing details of the direct digital synthesizer in FIG.

12 is an explanatory diagram in which the accumulator portion of FIG. 11 is simplified to 4 bits.

FIG. 13 is a diagram showing a mechanism of accumulator frequency division.

14 is a diagram showing a waveform generated based on the clock of the direct digital synthesizer shown in FIG.

FIG. 15 is a diagram showing clock shift based on a generated waveform.

FIG. 16 is a waveform chart in the case of integer division.

FIG. 17 is a waveform chart in the case of decimal point division.

FIG. 18 is an MBS output waveform diagram in the case of decimal point division.

[Explanation of symbols]

 40 Control Section 41 Phase Accumulator 42 High Level Period Detector 43 Low Level Period Detector 44 Zero Crossing Period Detector 45 Phase Residual Value Extractor 46 Subtractor 50 Analog Section 52 Low Pass Filter 53 High Pass Filter 54 Comparator

Claims (4)

[Claims] 1. A high level period detector for detecting a high level period of a reference frequency signal based on an MSB output signal of a phase accumulator for enabling decimal point frequency division, and a low level period detection for detecting a low level period. And a control unit configured with a zero-cross period detector that detects the zero-cross period, and a control signal from the control unit described above converts the digital signal of the zero-cross period into an analog signal, and that signal is converted into the zero-cross period. To a high level cycle and a low level cycle with a zero value in the same manner to generate a partial pulse height signal, and remove unnecessary noise components from the signal with a subsequent low pass filter. After that, the analog section that converts the digital signal again through the analog comparator In the configuration, a phase locked loop for sub-pulse-height type reference frequency generation circuit an output signal, characterized in that to input to a subsequent phase-locked loop from the analog section. 2. A phase that locks or follows the reference frequency by receiving the reference frequency signal and comparing the phase with its own oscillation output waveform and controlling the oscillation output frequency in a direction to reduce the error. In the lock loop reference frequency generation circuit, the phase increment value Δ which is the set value corresponding to the given reference frequency
A phase accumulator that accumulates θ, a high level cycle detector that detects a high level cycle from the MSB bit output of the output value that is the accumulation result in this phase accumulator, a low level cycle detector that detects a low level cycle, and zero. A zero-cross period detector for detecting the cross period, a phase remainder value extractor for extracting the phase remainder value from the lower bit output excluding the MSB bit of the output value which is the accumulation result in the phase accumulator, and the above phase Output of the residual value sampling result and the phase increment value Δ
Switch means for generating L → H and H → L zero cross signals based on θ, and a scaling device for scaling the front data or the back data based on the true zero cross within the zero cross period. And a D / A converter for inputting the data before or after the zero crossing period to the scaling device and converting the output to an analog signal, and an analog signal output converted by the D / A converter for zero crossing. A low-pass filter that generates a partial pulse height waveform output signal by applying a full scale to the high level period and a zero value to the low level period in the same manner as the period signal, and generates this as a sine wave with no clock noise. And the output signal from the above low-pass filter is input, and the high-pass filter that removes the subharmonic component of this output signal is input. And a comparator that receives the output signal from the high-pass filter and converts it into a digital signal as a reference frequency signal. By outputting the reference frequency signal as a reference frequency to the phase-locked loop, Partial pulse height type reference frequency generation circuit for phase locked loop, which drives the phase locked loop. 3. A partial pulse height type for a phase locked loop according to claim 2, further comprising digital circuit means for performing a pipeline delay according to the number of samples of waveform generation in the preceding stage of the D / A converter. Reference frequency generation circuit. 4. The D / A converter is provided with a buffer of three series in the preceding stage, and each signal series can be selected by an output enable signal.
Partial pulse height type reference frequency generation circuit for the described phase locked loop.