JP3218720B2 - Input signal edge time measuring circuit and digital PLL device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input signal edge time measuring circuit and a digital PLL device, and more particularly, to detecting an edge position of an input signal waveform and digitally controlling a PLL operation based on the detected edge position. And a digital PLL device.

[0002]

2. Description of the Related Art Generally, a PLL (Phase Locked Loop) circuit is a phase locked loop circuit that follows the phase of an input signal, and is configured using an analog phase comparator, a low-pass filter, a voltage controlled oscillator, and the like. In recent years, digital PLL circuits have been proposed in which the operation inside the PLL circuit is performed digitally.

In this digital PLL circuit, for example, a configuration is often adopted in which the phase difference between a PLL output signal and an input signal is measured using a high-speed (high-rate) master clock. That is, the time difference between the edge (transient) of the input signal and the output clock generated inside the PLL circuit, that is, the phase difference, is detected and counted with the accuracy of the high-speed master clock, and the phase of the output clock from inside the circuit is detected. It is controlled to synchronize with the clock of the input signal. In this case, the master clock is required to have an accuracy higher by one digit or more than the bit clock of the input signal.

However, when the clock frequency of the input signal increases, it becomes difficult to increase the frequency of the master clock by one digit or more. This is because the operating clock frequency cannot be extremely increased due to the limitation of the semiconductor process. Therefore, it is desired to configure a digital PLL device capable of detecting an effective phase difference without extremely increasing the master clock frequency.

That is, in a digital PLL device, an input signal is first sampled by a master clock. The edge time of the input signal obtained in this process includes an error in the width of the period of the master clock. Therefore, unless sampling is performed at a cycle as small as possible and edge times are not accurately captured, errors in data due to the PLL increase. In order to solve the situation where the required reproduction clock frequency increases but the master clock frequency cannot be increased unnecessarily due to the limitation of the semiconductor process, for example, the ratio of the master clock frequency / PLL output clock frequency is 2 It is desired to provide a circuit that can secure a good error rate even if the error rate slightly exceeds.

[0006]

SUMMARY OF THE INVENTION Here, the present inventor
In JP-A-63-292825, a period during which N clock pulses of a PLL output clock are output is detected by using a master clock having a predetermined frequency, and the period is reduced by 1 / N to obtain the PLL clock cycle. Is obtained with N times the accuracy of the master clock. Also,
In Japanese Patent Application Laid-Open No. 64-19826, periods during which N / K pulses of a PLL output clock are output are sequentially and successively detected, and a continuous K period of each of these detected periods is detected.
A technique is disclosed in which batches are sequentially shifted by one period and added, and the addition result is 1 / N to obtain the output clock cycle data. According to these techniques, a digital PLL can be configured using a master clock having a relatively low frequency.

However, the PLL output clock (reproduced clock) increases with the performance of the system, and as described above, a clock having a ratio of master clock frequency / PLL output clock frequency of about 2 to 3 is required. Is coming. In such a situation, problems such as an increase in an error rate occur in the above-mentioned prior art, and further improvement is desired.

The present invention has been made in view of such circumstances, and a normal PLL is used even when the ratio of the master clock frequency to the clock frequency of the input signal is about 2 to 3.
The present invention provides a digital PLL device capable of ensuring a good error rate even when the operation is performed and the ratio of the master clock frequency to the reproduction clock frequency is greater than 1, and a preferable input signal applied to the digital PLL device. An object is to provide an edge time measuring circuit.

[0009]

According to the input signal edge time measuring circuit of the present invention, a ring oscillator (for example, the ring oscillator 30 in FIG. 1) formed by connecting an odd number of inverting elements in a ring is provided. Means for detecting signal edge (delay element 21 and exclusive OR circuit 22 in FIG. 1)
First latch means (flip-flop circuit 23) for taking in the state of each stage of the ring oscillator at the timing of the detected edge of the input signal; and timing of the master clock for each stage of the ring oscillator. The second latch means (flip-flop circuit unit 27), the state of each stage of the ring oscillator captured by the first latch means, and the state of each of the ring oscillators captured by the second latch means. Edge position calculating means (subtractor 2
6, the multiplier 36) solves the above-mentioned problem.

Here, the edge position calculating means takes in the output from the first latch means (for example, the flip-flop circuit section 23 in FIG. 15) at the rising timing of the master clock. And a fourth latch means (flip-flop circuit part 24B in FIG. 15) for taking in the output from the first latch means at the falling timing of the master clock. When the signal edge is in the "H" (high level) section of the master clock, the output from the third latch means is in the "L" (low level) section of the master clock. Sometimes, the output from the fourth latch means is selected and compared with the output from the second latch means. It is preferable to.

The ring oscillator comprises an inverting element having a variable delay time (for example, the configuration shown in FIG. 20), and switches the delay time according to a ratio between a master clock cycle and an oscillation operation cycle of the ring oscillator. It is preferable to select.

Next, in the digital PLL device according to the present invention, the input signal edge time measuring circuit having the above-described features samples the input signal with a master clock and detects the presence or absence of an edge of the input signal in master clock units. (For example, flip-flops 13 and 14 and exclusive OR circuit 15 in FIG. 1)
And a reproduction clock generating means (for example, adder 62, latch circuit 63,
An adder 64 and the like, and phase error detecting means (shift register in FIG. 7) for obtaining phase error data between the reproduced clock and the input signal edge based on the edge position signal and the edge detection signal and transmitting the data to the reproduced clock generating means. 51, window circuit 52, latch circuit 53, decoder 54, subtractor 5
5, a shift register 56, a selector 57, etc.), and a reproduction clock cycle detection means (for example, the configuration shown in FIG. 13) which detects the reproduction clock cycle data from the reproduction clock generation means and sends the data to the reproduction clock generation means. By doing so, the above-mentioned problem is solved.

The edge position calculating means includes a third latch means for taking in an output from the first latch means at a rising timing of the master clock, and an output from the first latch means to the master. And fourth latch means for taking in at the falling timing of the clock, wherein when the edge of the input signal is in the "H" (high level) section of the master clock, the output from the third latch means is output to the third latch means. When the edge of the input signal is in the "L" (low level) section of the master clock, the output from the fourth latch means is selected and compared with the output from the second latch means. Is preferred.

It is preferable that the ring oscillator includes an inverting element having a variable delay time, and that the delay time is switched and selected according to a ratio of an oscillation operation cycle of the ring oscillator to a cycle of the master clock.

[0015]

The state (set of states) of each stage of the ring oscillator is obtained by dividing the oscillation operation cycle of the ring oscillator by the number of stages (the number of the inverting elements) (this is referred to as a measurement unit time τ _UN ). Is changed in units of
The difference between the states captured by the second latch means can be represented by the measurement unit time τ _UN , whereby the edge position within the master clock cycle can be represented with high accuracy using the measurement unit time τ _UN as a unit. Can be.

[0016] can be obtained by also the accuracy of the measurement unit time tau _UN a phase error between the input edge and the reproduction clock based on the input edge position represented the measurement unit time tau _UN units, a master clock period Can maintain a good PLL operation even when the clock approaches the reproduction clock cycle.

[0017]

FIG. 1 is a block circuit diagram showing a schematic configuration of an input signal edge time measuring circuit used in a digital PLL device according to an embodiment of the present invention.

[0018] In FIG. 1, the input terminal 11 RF (radio frequency) input signal RF _in is supplied to be reproduced clock, the master clock signal MCK as a reference is supplied to the input terminal 12. The RF input signal RF _in is
The master clock signal MCK is supplied to the data input terminal D of the flip-flop 13, which is input as a clock, and is taken in at the timing of the master clock. The output signal from the flip-flop 13 is an exclusive OR (Ex) of the signal and the signal delayed by one master clock cycle in the flip-flop 14.
-OR) circuit 15 to perform edge detection. The detection signal ED for the presence / absence of an input edge synchronized with the master clock signal MCK is taken out via the output terminal 16.

An RF input signal RF from the input terminal 11
_in is the exclusive OR (Ex-OR) with the delay element 21 having a delay time sufficiently shorter than the master clock cycle T _MC.
The edge is detected by the circuit 22 and sent to the clock input terminal of the flip-flop circuit unit 23. The flip-flop circuit unit 23 includes the number n of stages of the ring oscillator 30.
According to (n is an odd number, for example, n = 15), n flip-flops are provided in parallel. That is, the flip-flop circuit 23 having these n pieces of flip-flops, the inverting element n stages formed by connecting in a ring (n bits) edge of the input signal RF _in the state of each stage of the ring oscillator 30 Each data input terminal D according to the detection output
It is to take in. In this embodiment, n = 1
It is assumed that the ring oscillator 30 is 5 bits, that is, 15 bits, and the flip-flop circuit unit 23 is provided with 15 flip-flops in parallel in order to capture the internal 15 stages.

Here, the ring oscillator 30 will be described with reference to FIG. In the example of FIG. 2, a ring oscillator 30 'in which the number of stages n is 5 is shown to simplify the description. As shown in FIG. 2, a five-stage (generally an odd-number stage) or a five-bit ring oscillator 30 ′ includes five inverting elements (inverters) 3.
1 _a , 31 _b , 31 _c , 31 _d , and 31 _e are connected in a ring shape. Since an odd number of inverting elements are connected, even if the input changes to, for example, "H", there is always one logically inconsistent element whose output has the same polarity, for example, "H" and remains unchanged. If the output changes to "L" after the delay time of the element, the logical contradiction moves to the next element. In this way, stable oscillation can be obtained. Here, in the example of FIG. 2, in order to start and stop the oscillation operation of the ring oscillator 30 ′, _a two-input NAND (negation of logical product) gate is used as the element 31a, and this NAND gate 31 _a
One end sends an output signal from the inverter 31 _e, the signal STOP to the other end (STOP represents the signal obtained by inverting the polarity of the stop signal STOP) is sending.

FIG. 3 illustrates the operation of the configuration of FIG.
FIG. 3 is a diagram showing signal waveforms of various parts forSTOP
And each element 31_a, 31_b, 31_c, 31_d, 31_eOr
These output signals a, b, c, d, and e are shown. This
Here, each element 31_a, 31_b, 31_c, 31_d, 31_e
Τ_a, Τ_b, Τ_c, Τ_d, Τ_eWhen
are doing. The above signalSTOPRises, the time τ_aPassage
Later element 31_aThe inverted output signal a from
Each element 31 in descending order_b, 31_c, 31_d, 31_eBy anti
To obtain output signal waveforms as shown in FIG.
Can be One cycle T of these output signals_RNIs a ring os
Two rotations of the logic contradiction propagating through the five elements of the
Equivalent, T_RN= 2 (τ_a+ Τ_b+ Τ_c+ Τ_d+ Τ_e). Delay time of each element τ_a, Τ_b, Τ_c, Τ_d, Τ
_eAre equal to each other, for example, τ₀(Τ_a= Τ_b= Τ_c= Τ
_d= Τ_e= Τ₀), T_RN= 10τ₀ The time required for this logical contradiction to return to its original state after two rotations (ring
The time for one rotation of the oscillator's oscillation operation, that is, oscillation
Operation cycle) T_RNIs the period T of the master clock MCK._MCYo
Delay and the number of stages per element are set so that
Is done. This is because the ring oscillator is included in the master clock MCK.
If the same state of the data appears more than once, the time cannot be determined.
Because it is.

The rise of each of the output signals a to e in FIG.
Focusing on only (see the arrow in the figure), the signal b and the signal
d, signal a, signal c, and signal e appear in this order.
Rolling is one cycle T_RNBecomes These signals b, d, a,
c and e are sequentially output from the ring oscillator S₁, S_Two, S_Three,
S_Four, S_FiveAs each output terminal 32₁, 32_Two, 3
2_Three, 32_Four, 32_FiveMore out. These out
Force signal S₁~ S_FiveConstitutes the flip-flop circuit section.
A plurality of (in this case, for example, five) flips to be formed
Each is sent to the flop. Embodiment of FIG.
Then, the ring oscillator 30 has 15 stages (15 elements).
And 15 output signals S from each element ₁~ S_Fifteen
To the 15 flip-flop circuits of the flip-flop circuit section 23.
Is sent to each data input terminal D of the
is there. In the flip-flop circuit unit 23, the ring oscillator
Output signal S from the data 30₁~ S_FifteenThe above RF input signal
Issue RF_inAt the timing of each flip-flop.
By doing so, fine time measurement described later, especially
Input signal to the rising edge of
The position of the carriage is detected. in this way,
The state of each element (each output signal) of the ring oscillator
Therefore, as described above, for example, attention is focused only on the rising edge of the signal.
When measuring the input signal edge position described later.
Unit measurement time τ_UNIs the element delay time τ₀
(Τ_UN= 2τ₀).

Next, FIG. 4 shows signal waveforms for explaining an input edge detecting operation in units of a master clock by the flip-flops 13 and 14 and the Ex-OR circuit 15 of FIG. In FIG. 4, the flip-flop 13 is connected to an RF input signal from the input terminal 11 of FIG.
The RF _in and outputs a signal FF ₁₃ takes in at the rising edge of the master clock signal MCK. The flip-flop 14 outputs a signal FF ₁₄ the output signal FF ₁₃ is delayed by one clock (master clock) period T _MC content. The Ex-OR circuit 15 outputs these signals FF ₁₃ , FF
Taking an exclusive OR of _14, it sends a signal EX ₁₅ to the output terminal 16. "H" (high level) state of this output signal EX ₁₅ is, represents the edge detection state at clock period immediately before. This makes it possible to detect the presence or absence of an edge of the input signal in master clock units.

Next, referring to the signal waveform shown in FIG.
The operation of measuring the edge time by the 15-element ring oscillator 30 of FIG. 1, that is, the operation of measuring a fine edge position within the master clock cycle _TMC will be described. In FIG. 5, a 15-element ring oscillator 3
0 is ticked by the measurement unit time τ _UN which is finer than the master clock MCK like the output signal RS. At this time, the rising edge of the master clock MCK and the RF
Input signal RF _in of the rise or fall time difference d of the ring oscillator output signal RS of the edge by measuring by the measuring unit time tau _UN.

More specifically, the master clock MCK from the input terminal 12 is provided in the flip-flop circuit section 27 composed of flip-flops of the number of elements (15) for capturing the state of each element of the ring oscillator 30. Is supplied as a clock, and the state of each element of the ring oscillator 30 is captured (latched) by each flip-flop at the timing of the rising edge of the master clock MCK. An example of an output from the flip-flop circuit unit 27 is shown as a signal FF ₂₇ in FIG.

The exclusive OR (E)
x-OR) edge detection of the RF input signal RF _in from the input terminal 11 by the circuit 22 is made, the edge detection signal
When EX ₂₂ is sent to the clock input terminal of each flip-flop of the flip-flop circuit unit 23, the state of each element of the ring oscillator is taken into each flip-flop at the timing of the edge of this input signal.
An output signal FF ₂₃ from each flip-flop of the flip-flop circuit unit ₂₃ is output to the next-stage flip-flop circuit unit 24.
, And the flip-flop circuit section 24 supplies the master clock MCK
Is supplied as a clock, the signal FF is generated at the timing of the rising edge of the master clock MCK.
Re-acquisition (re-latch) of ₂₃ is performed, and an output signal FF ₂₄ is obtained from the flip-flop circuit section 24.

Here, the output signal of the ring oscillator shown in FIG.
Regarding RS, a number (15 states) corresponding to each state inside the ring oscillator of 15 elements, that is, each state (15 states) obtained by dividing one cycle (oscillation operation cycle) T _{RN of} the ring oscillator by the number of elements. 1 to 15), and output signals FF ₂₃ , FF ₂₄ ,
FF ₂₇ is also shown with a numeral corresponding to the internal state of the ring oscillator. For example, the state of the ring oscillator output RS at the rising time t ₁ of the master clock MCK in FIG. 5 is “1”, and this state “1” is taken in by the flip-flop circuit unit 27 (15 flip-flops). Therefore, the output from the flip-flop circuit unit 27 after this time t ₁ (the output of the 15 flip-flops) is “1”.

[0028] In FIG. 5, as one specific example of the measurement operation of the fine position in the master clock period T in _MC, the rising edge time t ₁₁ of the input signal RF _in to the rising time t ₂ of the next master clock MCK The operation of measuring the time d1 will be described.

[0029] In the edge time t ₁₁ of the input signal RF _in,
The state of the ring oscillator output RS is “2”, and this state “2” is taken in by the flip-flop circuit section 23 and the output becomes “2”. The output “2” from the flip-flop circuit section 23 is taken into the flip-flop circuit section 24 at the time t ₂ and sent to the binary conversion circuit 25. The state of the ring oscillator output RS at time t ₂ is “9”, and this state “9” is captured by the flip-flop circuit unit 27, so that the output “9” is sent to the binary conversion circuit 28. The outputs from these flip-flop circuit units 27 and 24 are plural (15
Output state of each flip-flop,
These states are converted into numerical data BN ₂₈ and BN ₂₅ by binary conversion circuits ₂₈ and ₂₅ , respectively, and are sent to the subtracter 26 as numerical values “9” and “2” in the example of FIG. Note that a specific configuration example of the binary conversion circuits 28 and 25 will be described later with reference to FIG.

The time d1 at which the value of the output from the subtractor 26 indicates the fine position of the input edge is referred to as the measurement unit time τ.
Corresponds to the values expressed in _UN, during the period from the time t ₂ to the rise time t ₃ of the next master clock MCK is "7"
(= 9-2). That is, the input edge time t
Time d from ₁₁ to master clock rise time t ₂
1 is the measurement unit time τ of the ring oscillator 30
Delay time 7τ _UN (= 7) corresponding to seven _UN (= 2τ ₀ )
14τ ₀ ).

[0031] Similarly, the time d2 between the falling edge time t ₁₂ of the input signal RF _in to the next rising time t ₄ of the master clock MCK, the ring oscillator output RS at each time t _12, t ₄ The states “7” and “10” are fetched and subtracted by the subtractor 26 after time t ₄ , thereby obtaining an output value “3” (= 10−7) from the subtractor 26.

Next, a specific configuration example of the binary conversion circuits 27 and 25 will be described with reference to FIG. In FIG. 6, in order to simplify the description, 7
A configuration for performing binary conversion of seven states from a ring oscillator composed of element inverters is shown.

[0033] In FIG. 6, seven flip-flops F1~F7 is equivalent to the flip-flop circuit 24 or 27, these flip-flops F1~F7 of each input signal S ₁ to S ₇ The state is acquired at the timing of the rising edge of the master clock MCK. Each output from these flip-flops F1~F7 is first sent to a detection circuit 41 (the rising portion of the signal), and has a rising immediately after the portion of the respective signal S ₁ to S ₇ (top) A signal is detected. That is, among the signals S _{1 to} S ₇ , only the output corresponding to the first signal is “1”, and the other outputs are “0”. This is because the signals S _{1 to} S ₇ are arranged in the order in which the signals rise as time elapses, so that one signal S _k is “H” and the next signal S _{k + 1} is “L”. , The signal _Sk is the top (the part immediately after the rise). Here, k is a value of 1 to 7, and when k = 7, k + 1 = 1.
Becomes Thus, in order to determine the condition that one signal S _k is “H” and the next signal S _{k + 1} is “L”, the negation gates (inverters) N1 to N7 and AND Gates A1 to A7 are provided.

As for the output from the head detection circuit 41, only the output corresponding to the signal whose head is detected among the signals S _{1 to} S ₇ becomes “H” (“1”), and the other outputs Are all "L"("0"). To convert this into a binary (binary) representation, the AND gate A1
A 7-3 encoder 42 including 0 to A12 is provided. The 7-3 encoder 42 outputs the least significant bit (L
Top AND gate A10 of SB) B ₀ side detecting circuit section H
D second, fourth, and sixth AND gates A2, A4, A6
And the output from the third, fourth, and seventh AND gates A3, A4, and A7 of the head detection circuit section 41 is supplied to the next digit AND gate A11, and the most significant bit (MSB) The head detection circuit unit H is connected to the AND gate A12 on the side.
D fifth, sixth, and seventh AND gates A5, A6, A7
Is supplied to convert the input of 7 lines into a 3-bit binary code. Therefore, when the output from the AND gate A1 of the head detection circuit unit 41 becomes "1", the 3-bit output from the 7-3 encoder 42 becomes "000", and thereafter, the outputs of the AND gates A2 to A7 sequentially become "000". When it becomes "1", the 3-bit output sequentially becomes "001" to "110".

As described above, each of the flip-flops 2
The state of the output from each of the binary conversion circuits 2 and 7 is
Converted to binary (binary) values at 8, 25 respectively
These values are sent to the subtractor 26, and the output value of the binary conversion circuit 25 is subtracted from the output value of the binary conversion circuit 28. The output value from the subtracter 26 is calculated based on the input signal
The time from the edge of RF _in to the next rise of the master clock MCK (the above-mentioned time d1 or d2 in FIG. 5) is a value represented by the above-mentioned measurement unit time τ _UN of the ring oscillator 30, and this subtracted output value Is sent to the multiplier 36.

The multiplier 36 calculates the input edge fine position times d1 and d2 by multiplying the subtraction output value by the measurement unit time τ _UN based on each element state of the ring oscillator 30 in principle. I do. Since the fine position time is convenient for processing in a subsequent block, it is represented by a number with the master clock period T _MC being 1. Here, in the present embodiment, one cycle T _RN of the operation of the ring oscillator 30 from the ring delay time measuring circuit 33.
Is sent to the multiplier 36. Digit multiplication output by 1/0 inverted in the inverter 37, into a time between the input edge time and the master clock MCK of the rising edge of the immediately preceding (e.g. T _MC -d1, T _MC -d2 etc.) . This is output terminal 3 as edge position signal EP.
Take out from 8. For example, the edge position signal EP
Is a 6-bit value, the master clock cycle T _{MC is set} to 1, and from the rising edge of the master clock MCK to the next rising edge, the binary decimal value of (0.) 000000 to (0.) 111111 (however, actually Does not use the leading integer part 0).

Next, an example of the configuration of the phase locked loop will be described with reference to FIG. In FIG. 7, terminal 1
The master clock MCK to 2, the edge detection signal ED to the terminal 16 which detects the presence or absence of the input signal RF _in edges
The terminal 38 is supplied with an edge position signal EP representing the input edge position with the master clock period T _MC being 1.

The edge detection signal ED supplied to the terminal 16 is input to a shift register 51 of a plurality of bits, for example, 9 bits, and a plurality of bits (9 bits) are output in parallel in the order of time. Circuit 5
2 to the reproduction clock cycle latch circuit 53. The 9-bit output from the reproduction clock cycle latch circuit 53 is converted into, for example, a 4-bit binary value by the edge position integer part decoder 54 and sent to the subtractor 55. Further, the edge position signal EP supplied to the terminal 38
Is data representing the edge position when the master clock period T _{MC is set} to 1 as described above by a plurality of bits (for example, 6 bits). To the shift register 56. The output of the shift register 56, for example, 6-bit parallel and 9-stage parallel, is sent to the selector 57, and the edge position data of a plurality of bits (6 bits) of the stage corresponding to the bit where the input edge exists is selected. Then, it is sent to the reproduction clock cycle latch circuit 53. This is coupled to the lower part of the integer part data (4 bits) from the edge position integer part decoder 54 as decimal part data (6 bits) of the edge position, and sent to the subtractor 55.

Next, the terminal 61 is supplied with reproduced clock cycle data T _RC described later, and this reproduced clock cycle data T _RC is sent to the adder 62. The adder 62 forms a loop including a latch circuit 63 and an adder 64, and this loop corresponds to a VCO (Voltage Controlled Oscillator) which is also the heart of the PLL. That is, during one round of this loop, the reproduction clock cycle data is added by the adder 62, and the phase error correction data is added by the adder 64. The phase error correction data to the adder 64 is
The signal is supplied from the subtracter 55 through, for example, a 回路 circuit 58 and a flip-flop circuit unit 59. The in-window edge detection signal from the edge position integer part decoder 54 is supplied to the adder 64 as an addition control signal. When an edge exists in the window, the output data of the latch circuit 63 and the flip-flop circuit The error correction signal data from 59 is added and output, and when there is no edge in the window, the output data from latch circuit 63 is output as it is.

The reproduced clock cycle data T from the terminal 61
_{The RC} is halved by the 回路 circuit 65 to be half-cycle data T _RC / 2 of the reproduction clock, and is sent to the adder 66 via the latch circuit 63. The adder 66 is supplied with, for example, the lower 6 bits of the 9-bit output data from the adder 64, and outputs the addition result to the window generator 67. The window generator 67 is supplied with data of the lower four stages (input stage side) of the 6-bit parallel 9-stage parallel shift register 56, that is, data of 24 bits. It is sent to the cycle length window circuit 52.

Next, the upper 3 bits in the output of, for example, 9 bits from the adder 64 are sent to the comparator 71. Further, the master clock MCK from the terminal 12 is sent to the 3-bit counter 72, and the output signal from the 3-bit counter 72 is sent to the comparator 71. When these two inputs of the comparator 71 match, a match output is sent as a recovered clock cycle enable signal RCE to each enable terminal of the recovered clock cycle latch circuit 53, the latch circuit 63, and the output terminal 73. Further, the reproduced clock cycle enable signal RCE is taken out from the output terminal 75 via the flip-flop 74 as the reproduced clock output signal RCK. Further, the coincidence output from the comparator 71 (the above-described recovered clock cycle enable signal RCE) is sent to the AND gate 76, and the shaped RF signal is output through the flip-flops 77 and 78.
It is taken out from the output terminal 79 as an output signal RF _out .
The clock input terminals of the flip-flops 74, 77 and 78 are supplied with the master clock MCK from the terminal 12,
The AND gate 76 is supplied with an in-window edge detection signal from the edge position integer part decoder 54.

Here, in general, the digital PLL detects how much the input edge is from “the position (time) of the input edge that should be originally” in units of a master clock,
The reproduction clock phase is changed according to the shift amount. The above-mentioned “input edge position that should be originally” can be finely calculated by measuring one cycle length more finely than the master clock and integrating it, but since the minimum unit of the input edge time is the master clock, one master clock period T _Includes time error in _MC width. The edge is the master clock period T
Calculate as if it is exactly at the center of _MC , but eventually 1
The error of the width of the period of the master clock period T _MC remains included. In contrast, in the embodiment of the present invention, a fine edge position can be determined by the edge position signal EP. The use of this has two advantages. One is accurate edge position error calculation, and the other is accurate window boundary calculation. The operation will be described below focusing on these advantages.

The edge detection signal ED supplied to the terminal 16 in FIG.
1 is input and is made a parallel output of 9 bits in time order.
The signal is sent to the reproduction clock cycle latch circuit 53 via the reproduction clock 1 cycle length window circuit 52. When the PLL is locked and the phase error of the input edge is 0, the 9-bit parallel output from the shift register 51 is latched at the timing when the edge-present signal rises at the output bit at a predetermined position (normal center position). The latching interval is the reproduction clock R
CK is the period T _RC of.

The edge position signal EP of, for example, 6 bits supplied through the terminal 38 of FIG. 7 is supplied to the shift register 5 of a plurality of stages (for example, 9 stages) in parallel with the 6 bits.
6 has been entered. 6 from this shift register 56
The bit-parallel and nine-stage parallel outputs are sent to the selector 57, and the bits having the edge-existing polarity in the output of the edge detection signal ED obtained from the shift register 51 via the window circuit 52 are output. Is selected as the 6-bit parallel output of the stage corresponding to. Selector 5
6-bit parallel output 7 is taken into the reproducing clock period latch circuit 53 in the period T _RC of the reproduction clock RCK.

The latch timing is set so as to match the edge rate and phase of the input signal by the phase synchronization circuit. When the rate matches the phase, the shift register output (usually at the center) of the edge presence / absence signal is output. When an edge presence signal appears at a predetermined position, the input edge has a relationship of a predetermined timing with no phase error. In other words, if there is no time lag such as a peak shift in the input edge, the input edge is always latched when a signal indicating an edge is output at a predetermined position of the shift register. Therefore, when the latched edge presence / absence signal is shifted by one bit from the predetermined position, it means that there is a phase shift (time shift) of about one bit in the unit of the master clock cycle _TMC . 1
The expression “before and after the bit” indicates that an accurate position cannot be determined by this alone. However, since the edge position signal latched at the same time is at the timing when the edge presence / absence signal has an edge, it can be seen from this that the position in the master clock is located.

Here, the position of the edge in the unit of master clock is set to 1, 2,...
It is represented by an integer such as 1, -2, .... On the other hand, the edge position signal representing the position in the master clock is represented by a decimal number from 0 to less than 1 from the earlier to the later according to the flow of time. By combining the integer part and the decimal part, the input edge position can be represented as a numerical value. For example, as shown in FIG. 8, the earliest temporal position in the center bit is 0.0. In addition,
In the specific example of FIG. 8, for simplicity of illustration, the number of stages of the shift register is seven, the integer part is represented by 3 bits, and the edge position signal is represented by 4 bits (0000 to 1111). .

On the other hand, the latch timing is calculated not in units of bits but in more detail. That is, the reproduction clock cycle _TRC is, for example, 5T in the master clock cycle _TMC.
It is not a value represented by an integer multiple such as _MC or 6T _MC , but a value with a decimal part. This is integrated to create a timing at which the integer part of the integration result is latched, but naturally there is also a decimal part, and when latched, the input edge without phase error is
The edge presence / absence signal is captured at the center position, and the edge position signal coincides with the position of the decimal part of the numerical value forming the latch timing. FIG. 9 shows a specific example of this. In the specific example of FIG. 9, for simplicity of illustration, the integer part is 3 bits, the decimal part is 3 bits, and one cycle length T of the reproduced clock is set.
_RC is set to 100.111.

Therefore, by subtracting the decimal part of the numerical value forming the latch timing from the numerical value representing the position of the edge previously obtained, it is possible to know how much the edge has shifted from the time when the edge should be essential. The reason that the value to be subtracted is only a decimal part is that the integer part is used to determine the latch timing, and the position of the signal of the master clock unit of the latched edge is adjusted to be centered when the error is 0. Because it is equivalent to being already drawn. In this way, the phase error of the edge can be obtained with the accuracy of the input edge position signal (accuracy sufficiently higher than the master clock).

To summarize the above operation, the output from the shift register 51 to which the edge detection signal ED has been input is latched by the latch circuit 53 for each reproduction clock cycle enable signal RCE via the window circuit 52,
Separately, an edge position signal EP corresponding to a bit for which an edge detection flag is set in the output of the shift register is selected from the shift register 56 via the selector 57, and is similarly latched by the latch circuit 53. In addition,
The reproduction clock cycle enable signal RCE is an enable signal generated in accordance with the "edge position" which is calculated inside the phase locked loop. If the output from the shift register 51 taken into the latch circuit 53 is P
When the LL is locked and the input edge is just (just) timing (at the same position as the above “desired position”), be sure to set the center bit (for example, the fifth bit of a 9-bit shift register). I'm standing. In the decoder 54 that receives the output from the latch circuit 53, the center position is set to 0, and the center position is set earlier (right side).
A numerical value increases to the negative side such as -1, -2, ... as the bit shifts, and a positive value increases as the value shifts to a slower (left) bit, such as +1, +2, ... Is output. The decoder 54 also outputs a window edge presence / absence detection result indicating whether or not any bit in the window has an edge detection flag. Then, an accurate input edge position is obtained by adding the value of the edge position signal, which is simultaneously latched by the latch circuit 53, to the value of the edge bit position below the decimal point. This number is 0.0 at the beginning of the time of the center bit. By subtracting the above-mentioned “edge position that should be” from this number (however, only the decimal part is subtracted because the integer part is 0), the error of the input edge can be obtained with high accuracy. This error amount is appropriately attenuated in order to obtain an appropriate loop gain, for example, is attenuated to 1/4 by a 1/4 circuit 58 to generate an error correction signal, and is added to a loop for calculating "the position of an originally expected edge". Phase control. In this case, since the error amount of the edge is accurate, the response of the phase control does not become slow or too sensitive.

The following describes another advantage of using the edge position signal EP, which is accurate window boundary calculation.

The edge detection signal ED supplied to the terminal 16 in FIG.
1 is input and is made a parallel output of 9 bits in time order.
The signal is sent to the reproduction clock cycle latch circuit 53 via the reproduction clock 1 cycle length window circuit 52. When the PLL is locked and the phase error of the input edge is 0, the 9-bit parallel output from the shift register 51 is latched at the timing when the edge-present signal rises at the output bit at a predetermined position (normal center position). The latching interval is the reproduction clock R
CK is the period T _RC of. Since it is not latched at every reproducing clock period T _RC, since the shift register 51 until the next fetching only travels regeneration clock period T _RC content only when the output is capturing all bits (9 bits), the latch The edge once captured by the circuit 53 is captured again in the next capture, and one edge is counted twice. To avoid this, the playback clock 1
A cycle length window circuit 52 is inserted between the shift register 51 and the latch circuit 53, and a bit corresponding to ± 1/2 reproduced clock cycle (± _TRC / 2) centered on a predetermined bit of the shift register 51. Only through the output of
The outside is not allowed to pass.

The latch timing signal is obtained from the phase synchronization circuit (comparator 71) as a recovered clock cycle enable signal RCE. The recovered clock cycle enable signal RCE is not a unit of the master clock cycle _TMC. To the position within the master clock period _TMC in the unit of the measurement unit time τ _UN . This is because, when the master clock cycle _{TMC is set} to 1, the reproduced clock cycle _TRC can be obtained by a numerical value having a decimal part, and the phase correction signal also moves the reproduced clock RCK in small units after the decimal point. It is. Therefore, when the input edge presence / absence signal to be latched next has no error, it is taken in a predetermined (center) bit, but the position of the edge in the master clock is further predicted, which should be the original. This is the position of the edge (with zero phase error).

Reproduction clock 1 cycle length window circuit 52
Is located at ± 1/2 recovered clock cycle (± T _RC / 2) from the original edge position. The left boundary in FIG. 7 is created by adding a 1/2 recovered clock period ( _TRC / 2), while the right boundary is the difference between the number of bits between the previous latch and the current latch on the left boundary of the previous latch. You can use the location shifted by. The right boundary can be omitted by unifying the signal for shifting the shift register to the polarity having no edge (eliminating the edge) for the bit that has passed through the window at the time of the previous latch.

It is conceivable to determine whether or not to include, in the window, a bit corresponding to the boundary of the result of adding the 1/2 reproduced clock, by rounding off. In this embodiment, the bit located at the boundary is determined by the edge position. Looking at the position of the input edge with the signal EP, if it is smaller than the fractional part of the boundary value, it is included in the window, and if larger, the bit is outside the window and is taken in the next latch so as to be taken in the next latch. In this way, the window is obtained with the same accuracy as that of the edge position signal.

FIGS. 10 and 11 show a window generator 67 for calculating the window range as described above.
FIG. 3 is a block circuit diagram showing a specific example of FIG. First, as described with reference to FIG. 7, the adder 66 shown in FIG. 10 includes the half cycle T of the reproduced clock obtained from the half circuit 65 via the latch circuit 63.
And data X _A indicating the _RC / 2, and the data X _B representing a certain should edge position of the 9-bit output within the central bit of the lower 6 bits of the from the adder 64 is supplied. Of the 9 bits of these addition results, the upper three bits of data X
_C is information indicating a bit having the boundary, and
The bit data _XD is information indicating the position of the boundary within the boundary bit. Each of these data values X _A to X _D is shown in Figure 11.

The four left 6-bit parallel outputs that are temporally slower than the center position (JUST) of the shift register 56 in FIG. 10 are output from comparators 68a, 68b, 68c, respectively.
68d. These comparators 68a, 68
b, 68c, the 68d, the lower 6-bit output of the 9-bit output from the adder 66, that is, compared respectively data X _D indicating the position of the boundary in the boundary bit, when towards the X _D is large “H” (high level or “1”) is output. The data X _C indicating the above-mentioned bounded bit, which is the upper 3 bits output from the adder 66, is sent to the decoder 68 e, and is supplied to the AND gate 69 a when the data X _C is 1 or more, and to the AND gate 69 a when X _C is 2 or more. When X _C is 3 or more, “H” is sent to the AND gate 69c and the OR gate 69f, respectively, and when X _C is 4, “H” is sent to the AND gate 69d and the OR gate 69g. The output from the comparator 68a is sent to an AND gate 69a via an OR gate 69e, the output from the comparator 68b is sent to the AND gate 69b via an OR gate 69f, and the output from the comparator 68c is sent via an OR gate 69g. The output from the comparator 68d is sent directly to the AND gate 69d. Outputs from these AND gates 69a to 69d are taken out as window signals W1 to W4,
The reproduced clock is sent to the one-cycle length window circuit 52 shown in FIG.

In FIG. 11, when the previous desired edge position is at point p2 in the input edge information sequence, the 9 bits to be latched last time are 4 bits before and after the bit (center bit) including this point p2. From point p1 to point p
The range is up to 5. In this case, the boundary of the left side of the window (time slow future side), by making by adding the reproduction clock half-period data X _A content in the edge position to a said center bit (point p2), 11 Point p4
Is obtained. The right boundary may be the same as the previous left boundary. here,
Position to a current edge is substantially reproduced clock period T _RC from the point p2, i.e. as by twice adding the point p7, and the bit with the point p7 center of the half-period data X _A, is now latched The target 9 bits range from point p3 to point p9. This position should a current edge (point p7) points obtained by adding the half-cycle data X _A on the left side (the future side) from p8 is the position of the left boundary. The position of the right boundary may use the point p4 which is the previous left boundary.

It is impossible to determine whether or not to include such a bit corresponding to the above boundary in the window, for example, by rounding off. Is compared with the position in the bit of the boundary calculated as described above (the component after the decimal point). If the edge is inside the boundary, the bit is included in the window. I take in at the timing of. Even if the boundary bit has no edge and the edge position signal has a random value, it is meaningless whether or not the boundary bit is within the window because there is no edge. This is effective only when there is an edge in. An actual reproduction random error is caused by an edge shift due to a peak shift phenomenon, and when the noise rides in a direction to increase the shift, the edge is shifted by one.
In most cases, the error occurs due to detection at a position shifted by the reproduction clock cycle _TRC . The accuracy of the window boundaries thus improves the error rate.

The right boundary is defined by unifying the signal for shifting the shift register to the polarity having no edge, that is, erasing the edge for the bit that has passed through the window at the time of the previous latch. Can be omitted. FIG. 12 shows a specific configuration example for this purpose. In FIG. 12, the edge detection signal that has passed through the window circuit 52 and is latched by the latch circuit 53 is transmitted to the next stage of the shift register 51 after being cleared to 0 (without an edge). The signal with the edge once latched is not transmitted further by the shift register 51, so that the window circuit configuration on the right side of the center can be omitted.

Since an accurate window can be created in this way, the phase of the input edge can be compared with the phase of the recovered clock at the correct timing. In other words, it can be regarded as an edge corresponding to a reproduced clock which is correct in timing, and a signal error generated by the PLL by bit shift is reduced.

Returning to FIG. 7 again, the error amount of the high-precision input edge obtained by the subtractor 55 is
The signal is attenuated to / 4, so that an appropriate loop gain is obtained and an error correction signal is sent to the adder 64 via the flip-flop circuit unit 59. The adder 64, the adder 62 constitutes a also loops PLL heart with the latch circuit 63, the reproduction clock one period T _RC to the adder 62, the exact error correction amount to the adder 64 Are added respectively. Latch circuit 63, a flip-flop that is enabled signal reproducing clock period enable signal RCE, incorporate data for each reproduction clock period T _RC. If the error correction amount is always 0, the number in this loop simply increases by one period of the reproduction clock period _TRC .

On the other hand, for example, a 3-bit counter 72 is provided which counts up for each master clock MCK, and this is a measure of time. When the output from the counter 72 matches the bit unit amount (the above-mentioned integer part of the upper 3 bits) of the output value (9 bits) from the loop, the comparator 71 outputs the reproduced clock cycle enable signal RC.
E is output to take in the output signal of the shift register 51 of the edge detection signal ED or the like, or update the value in the loop to a value increased by one cycle length of the reproduction clock. The updated numerical value in the loop (adder 64
Is the value of the time at which the next recovered clock cycle enable signal is to be output, and when the count value of the counter 72 reaches that value, the comparator 71 sets the next recovered clock cycle enable signal RCE. Is output.

The numerical value of the above-mentioned loop is also a value indicating “a position where an edge should be originally”. That is, of the 9 bits output from the adder 64 of the loop, the upper 3 bits of the integer part controls the time at which the reproduced clock cycle enable signal RCE is output, so that the just input edge of the shift register 51 The timing of taking in when it comes to the center is the timing, and the decimal part of the lower 6 bits is used to calculate the error amount by subtracting it from the value of the position of the input edge. In the window generator 67, a half cycle of the reproduction clock is added to the numerical value of the loop, and the integer part indicates the window boundary in bits, and the decimal part indicates the detailed boundary value in bits.

The final reproduced clock RCK is obtained by converting the reproduced clock cycle enable signal RCE into the master clock MCK.
I make it with CK. That is, the master clock M
By sending the reproduction clock cycle enable signal RCE to the flip-flop 74 clocked by CK, a reproduction clock output RCK synchronized with the master clock MCK is obtained from the flip-flop 74. As a data output, the in-window edge presence / absence detection signal from the edge position integer part decoder 54 is generated by hitting the reproduction clock cycle enable signal RCE with the master clock MCK. The output from the AND gate 76 is supplied to the shaped RF output signal RF _out via flip-flops 77 and 78.
From the terminal 79.

Next, a reproduction clock 1 for obtaining one cycle length data ( _TRC ) of the reproduction clock supplied to the terminal 61 is described.
A specific example of the cycle length measurement circuit will be described with reference to FIG.

In FIG. 13, the master clock MCK from the terminal 12 is sent to each clock input terminal of a 6-bit counter 81, a 10-bit counter 82 and a 10-bit latch circuit 83, respectively. The recovered clock cycle enable signal RCE from the terminal 73 is sent to the enable terminal of the 6-bit counter 81,
The count output from 1 is sent to the load terminal of the 10-bit counter 82 and the enable terminal of the 10-bit latch circuit 83, respectively. “1” is always supplied to the data input terminal of the 10-bit counter 82. The output from the 10-bit counter 82 is a 10-bit latch circuit 8
3 are sent to the comparator 84 and the selector 85, respectively. Or to the comparator 84, the constant K ₁ as a comparative minimum (lowest) value from the constant generator 86, constant K ₂ to the maximum (upper limit) value are sent respectively, are within these ranges The comparison output of whether or not the signal is sent to the selector 85.
The selector 85 switches and selects the output from the 10-bit latch circuit 83 and the constant K ₃ from the constant generator 88 in accordance with the output from the comparator 84, and outputs the reproduced clock 1 cycle length data to the terminal 61. ( _TRC ).

Next, the operation will be described. The reproduction clock one cycle length data ( _TRC ) is represented by a number with the master clock cycle _TRC being one. Looking at only one cycle of the playback clock,
Since the number of master clocks among them is not large, highly accurate measurement cannot be performed. Therefore, the number of master clocks included in a plurality of reproduction clocks, preferably 2 ⁿ (n is an integer of 2 or more) is counted, and the value is divided by 2 ⁿ . To divide by 2 ⁿ , it is sufficient to shift by n bits, and highly accurate measurement can be easily performed.

The value is not directly used as one cycle of the reproduction clock, but it is checked whether or not the value is within the lock range. That is, the comparator 84 compares the values with the lower limit value K ₁ and the upper limit value K ₂ of the preset cycle, and compares these values K ₁ to K ₁ .
If it is within the range of K ₂ , the output from the 10-bit latch circuit 83 is selected by the selector 85, and if it is outside the range, the preset center cycle value K ₃ from the constant generator 88 is changed. Instead of the measured value, it is selected and output as one cycle length data of the reproduction clock. If the lock range is not limited, there are adverse effects such as a long time until locking or a so-called pseudo lock is likely to occur. It is needless to say that a specific example of the reproduction clock 1 cycle length measuring circuit is not limited to the example of FIG.

Returning to FIG. 1, the difference between the value of the ring oscillator 30 taken at the input edge (the state of the output RS) and the value of the ring oscillator 30 taken at the master clock MCK is calculated. In order to obtain the difference, the signal fetched at the input edge by the flip-flop circuit unit 23 is further transferred to the master clock MCK by the flip-flop circuit unit 24.
It is necessary to re-acquire as a master clock synchronization signal. However, the signal recaptured by the master clock is a signal that changes at the timing of the input edge that is asynchronous with the master clock. For this reason, if the input to the flip-flop circuit section 24 changes during the setup time or the hold time of the flip-flop circuit section 24 for re-fetching the master clock, either of the input before and after the change is changed. It is uncertain whether to import. Since the flip-flop circuit section 24 is composed of flip-flops of the same number as the number of stages of the ring oscillator 30 as described above, new and old data are mixed for each bit.

That is, for example, FIG.
Output from flip-flop circuit unit 23 for RF _in
FF ₂₃ , master clock MCK, flip-flop circuit 2
4 shows the output FF _24, and “a”, “b”, “c”, etc. in FIG.
(State). In FIG. 14, for example, the master clock MCK rises at time t ₁ while the flip-flop circuit unit 23 is taking in the ring oscillator value (state) “a” and the flip-flop circuit unit 2
4 takes on the value "a". Flip-flop circuit 23 at the rising edge time t ₁₁ of the input signal RF _in takes in the ring oscillator value "b", this flip-flop circuit 24 is capturing the rising time t ₂ of the master clock MCK. Here, if the master clock MCK rises at time t ₃ immediately after the falling edge time t ₁₂ of the input signal RF _in, the ring oscillator value "c" at time t ₁₂ the flip-flop circuit 23 captures During the hold time between, the fetch by the flip-flop circuit unit 24 is performed, and the time t
The output from the flip-flop circuit unit 24 after ₃ may be a mixture of the value “b” and the value “c” on a bit-by-bit basis.

Therefore, in the embodiment of the present invention, FIG.
By using the circuit configuration shown in (1), the drawback caused by the asynchronous signal capture is avoided. In this FIG.
The parts changed from the configuration in FIG. 1 are the configuration between the flip-flop circuit unit 23 and the subtractor 26, and the configuration from the flip-flops 13A and 13B to the OR gate 15C. About the other part, the same part as the above-mentioned each part structure of FIG. Note that the ring delay selection circuit 34 includes the ring oscillator 3
This is for switching and selecting the element delay time of 0, and will be described later.

In FIG. 15, the output from the flip-flop circuit unit 23 is sent to a flip-flop circuit unit 24A which takes in at the rise of the master clock MCK and a flip-flop circuit unit 24B which takes in at the fall of the master clock MCK. The output from the flip-flop circuit unit 24A passes through a binary conversion circuit 25A, and the output from the flip-flop circuit unit 24B passes through a binary conversion circuit 25B.
Sent to The output from the selector 25C is sent to the subtracter 26, and is subtracted from the output of the binary conversion circuit 28.
Further, the input RF signal RF _in from the input terminal 11 are sent respectively to the flip-flop 13B to capture the falling of the flip-flops 13A and a master clock MCK to capture at the rising edge of the master clock MCK. The output from the flip-flop 13A is the flip-flop 1
4A and the exclusive OR (Ex-OR) circuit 15A, and the output from the flip-flop 13B is sent to the flip-flop 14B. The output from the flip-flop 14A is sent to the Ex-OR circuit 15B,
The outputs from the flip-flop 14B are sent to the circuits 15A and 15B, respectively. Ex-OR circuit 15A,
The output from 15B is sent to the selector 25C as a selection control signal, and is also sent to the OR gate 15C. The output from the OR gate 15C is the edge detection signal E
It is taken out from the terminal 16 as D.

The basic concept of the above configuration is such that the latch output data at the input edge from the flip-flop circuit unit 23 is changed at an error-prone timing when it is captured at the rising edge of the master clock MCK. Takes into account that an error does not occur if the data is taken in at the next falling edge of the master clock MCK. Here, if the data is simply taken in only at the falling edge of the master clock MCK, data at the timing of being taken in at the falling edge and causing an error becomes a new problem. The data that is fetched is selected at the timing that does not occur.

That is, FIG. 16 is a time chart showing the waveforms and states (values) of the signals at various parts in FIG.
₂₃ such shows an output from the flip-flop circuit 23 or the like, the signal EX _15B, etc. indicates the output from the Ex-OR circuit 15B, etc., the signal SL _25C shows the output from the selector 25C. In the example of FIG. 16, the master clock MCK at time t ₀₂ immediately after the fall time t ₁₂ of the input edge
Falls, and the rising time t _{13 of the} input edge
The master clock MCK is up to time t ₄ immediately after.

[0075] In the example shown in this FIG. 16, the master clock MCK is "L" (low level) and going on interval, i.e. between time t ₀₁ ~t _2, input transition between t ₀₂ ~t ₃ etc. latching data from the flip-flop circuit 23 by the edge (e.g., time t ₁₃ between the time t ₀₃ ~t ₄
Flip-flop circuit section 2 at the input edge rising at
When the master clock MCK rises (time t ₄ ) and the input edge is immediately before the master clock rises, the setup time of the flip-flop circuit unit 23 (data “d”) taken in by the master clock MCK rises (time t ₄ ). Since the hold time is not satisfied and the data cannot be correctly captured, the data is captured in the flip-flop circuit unit 24B at the next falling edge of the master clock MCK (time t ₀₄ ).

[0076] On the contrary, the master clock MCK is "H" (high level) and going on interval, i.e. between time t ₁ ~t _01, latch data by the input edge transition between t ₂ ~t ₀₂ etc. (For example, a time t between times t _{2 and} t _02
With respect to the data “c” captured by the flip-flop circuit unit 23 at the input edge falling at ₁₂ ), when the master clock MCK falls again (time t ₀₂ ), the input edge becomes immediately before the master clock falls. when there, since it may not be captured correctly not satisfy the setup time, the flip-flop circuit 24A at the rising edge of the next master clock MCK (time t ₃₎
Take in.

To summarize these ideas, for example, the latch data due to the input edge in the section in which the master clock MCK is "L" is left in the section in which the master clock MCK is "H" and re-latched at the next falling edge. Therefore, if there is an input edge in the section where the master clock MCK is "L", it is assumed that the edge of the input signal does not come in the next section where the master clock MCK is "H". Since the direction of the master clock period T _MC than the playback clock cycle T _RC should not be longer, the edge interval of the input signal is essentially longer than the master clock period T _MC. at least,
The ratio of master clock frequency / reproduction clock frequency is 1
The larger the better, the more than 2 this effect is not decisive.

Here, the master clock half cycle ( _TMC /
2) When the input edges are continuous (two continuous) in unit, both edges can be canceled by using, for example, a circuit as shown in FIG. The circuit shown in FIG. 17 shows only a portion corresponding to the configuration of the terminals 11 and 12 to the terminal 16 in FIG. 15, and FIG. 18 shows output signals from each flip-flop circuit.

17 and 18, four Ex-OR (exclusive OR) circuits 91, 92, 93,
Of the 94, the Ex-OR circuit 93 is the Ex-OR circuit 15A of FIG. 15, and the Ex-OR circuit 92 is the Ex-OR circuit of FIG.
The circuit corresponds to the circuit 15B, and the edges before and after the master clock half cycle ( _TMC / 2) are also seen. The AND gate 96 calculates the logical product of the negation of the output of the Ex-OR circuit 91, the output of the Ex-OR circuit 92, and the negation of the output of the Ex-OR circuit 93, so that the “H” period of the master clock MCK is obtained. , And the AND gate 96 determines that the output of the Ex-OR circuit 92 is negated,
By taking the logical product of the output of the Ex-OR circuit 93 and the negation of the output of the Ex-OR circuit 94, the edge detection in the "L" section is performed. In this way, only when there is no edge in the section before and after the half cycle section where the edge was,
The edge detection signal ED rises.

Next, the ring delay selection circuit 34 shown in FIG. 15 will be described. As described above, the ring oscillator 3
If 0 is applied to a digital PLL, it is possible to accurately measure the input edge time, and there is an advantage that a master clock having a low frequency is sufficient. However, this ring oscillator uses the delay of the inverting gate element, and this delay greatly changes depending on variations in the semiconductor manufacturing process, the power supply voltage used, the temperature used, and the like. Also, if the rate of the digital signal input to the PLL changes, responding to the change in the reproduction clock by the change in the center frequency of the circuit causes a large increase in the circuit. It is preferable to change the ratio. Here, a specific example of the rate of change of the rate of the digital signal input to the PLL is assumed to be about 1: 8, and the rate of change of the master clock frequency at this time may be about 1: 4. preferable.

As described above, in a system where the delay of the inverting gate element and the master clock cycle T _MC are not constant,
When the master clock period _TMC is short, a short gate delay that has sufficient resolution when the master clock period _TMC is short, and when the master clock period _TMC is long, one cycle time that is so long that the ring oscillator does not make one turn within the master clock period _TMC . It is not realistic to have a ring oscillator with a huge number of stages. Therefore, a ring oscillator having a function of switching the delay amount per stage in a stepwise manner is used, and the ring delay amount selection circuit 34 sets the ring oscillator to a maximum within a range in which the ring oscillator does not make one or more rounds within the master clock cycle _TMC . The small delay amount per stage is selected.

The automatic switching or automatic selection of the delay amount of the ring oscillator will be described with reference to FIGS. FIG. 19 is a block circuit diagram showing a specific example of the ring delay time measurement circuit 33 and the ring delay selection circuit 34 of FIG. In FIG. 19, the input terminal 101 of the ring delay time measurement circuit 33 is
5 ring oscillator 30 (a specific configuration is shown in FIG.
An output signal from any one element is preferably supplied from the ring oscillator 30 ″ of 0). For example, an 11-bit measurement output from the output terminal 109 is sent to the multiplier 36 in FIG. 20 shows a specific configuration example of a ring oscillator 30 "whose delay time is selectively controlled by the ring delay selection circuit 34 of FIG. 19, and FIG. 21 can be used for the ring oscillator 30". One specific example of the inversion element is shown.

Here, the ring delay time measuring circuit 33 calculates one cycle (one rotation) T _RN of the operation of the ring oscillator,
It is measured in units of the master clock cycle T _MC . As a measurement waveform, an output waveform of any one inversion element of the ring oscillator is used. However, since accuracy is not obtained with one waveform (one cycle), the length of a plurality of waveforms (a plurality of cycles) is measured and divided by the number of waveforms to obtain one waveform (one cycle). In practice, the time of 2 ^N (N is a natural number) waveforms may be measured, and the values may be shifted by N bits to obtain a value obtained by ^{N N.} In the example of FIG. 19, N =
The number is set to 6, and the number of master clocks between 64 waveforms is measured.

That is, in FIG. 19, the output signal from any one element of the ring oscillator supplied via the terminal 101 is supplied to, for example, a 6-bit counter 102, and its MSB (most significant bit) output (so-called Q
₆ ) is sent to the flip-flop 103 and latched,
Flip-flop 104, inverter (inverting element) 10
5. An edge (falling edge) is detected by differentiation by the AND gate 106. Each flip-flop 1
As the clocks 02 and 103, the master clock MCK
Is used. The output signal from the AND gate 106 has a pulse cycle of 64 of the ring oscillator cycle T _RN .
Double 64T _RN , pulse width is one master clock period T _MC
It has become. This output signal is supplied to, for example, a load terminal of an 11-bit counter 107 and an 11-bit latch circuit 108.
, The number of master clocks MCK within the time of 64 T _RN is obtained. Specifically, the 11-bit counter 107 is loaded with "1" (reset to the initial value "1") by the output pulse from the AND gate 106, and the value immediately before the reset is taken into the latch circuit 108. ing. Assuming that a portion between the sixth and seventh bits from the LSB (least significant bit) of the 11-bit output from the latch circuit 108 is a decimal point, the position of the decimal point of the 11-bit integer value output is shifted upward by 6 bits. This means that it has shifted, and has been multiplied by 1/64. This is one of the operations of the ring oscillator.
This means that the rotation period T _RN is measured with an accuracy of 1/64 of the master clock period T _MC .

The ring delay selection circuit 34 is for selecting the delay amount of the ring oscillator to an appropriate value.
For example, when the value measured by the ring delay time measurement circuit 33 is 1 or less, the ring oscillator rotates one or more times within one cycle _TMC of the master clock, so it is necessary to select a delay amount one rank larger. It is. At this time, even if the measured value does not reach 1, it is preferable to perform switching with a margin so as to switch to a delay amount larger by one rank when the measured value falls below a predetermined lower limit value k _MIN of about 1.2, for example. . Also, if the measured value is too large, the period T _RN of one rotation of the ring oscillator operation is unnecessarily large, so that the measurement unit time τ _UN obtained by dividing this by the number of ring oscillator stages becomes large. The accuracy (the resolution within the master clock cycle _TMC ) will be reduced. Therefore, an upper limit value k _MAX is also set, and the upper limit value k _MAX is set.
It is preferable to control switching to a delay amount smaller by one rank when _{exceeding MAX} .

In the ring delay selection circuit 34 shown in FIG. 19, the comparator 111 compares the measured output value from the latch circuit 108 with the lower limit value k _MIN of, for example, about 1.2 and the upper limit value k _MAX (for example, of about 2). ) Is compared with the lower limit value k _MIN to the upper limit value k _MAX , “0” is set, and when it is smaller than the lower limit value k _MIN, “+1” is set.
Is transmitted to the adder 112 when the value is larger than the upper limit value k _MAX . The addition output from the adder 112 is the above-mentioned 6 from the AND gate 106.
The pulse output of the 4T _RN cycle is sent to the latch circuit 113 input to the enable terminal, and the output from the latch circuit 113 is sent to the adder 112 and the decoder 114. The decoder 114 decodes the output signal from the latch circuit 113 into, for example, five signals X _{1 to} X ₅ and outputs the signals.

FIG. 20 shows an example of a ring oscillator 30 "whose delay amount is switched and controlled by the signals X _{1 to} X ₅ , wherein n (n is an odd number) inverting (inverter) circuits 31
₁ to 31 _n are connected in a ring, the output signal S ₁ to S _n from each connection point has been removed. Each of these inverting circuits 31 _{1 to} 31 _n has a configuration in which the delay time can be switched to five stages by the signals X _{1 to} X ₅ from the ring delay selecting circuit 34 in FIG. FIG. 2 shows a specific example of the inverting circuit 31 capable of switching the delay time in five stages.
It is shown in FIG.

Input terminal 120 of inverting circuit 31 in FIG.
Is a delay element 1 having delay times τ ₁ , τ ₂ , τ ₃ respectively.
21, 122, and 123, and AND gate 124 and AND gate 12
5 respectively. The output terminal of the delay element 121 is connected to the AND gate 126, the output terminal of the delay element 122 is connected to the AND gate 127, and the output terminal of the delay element 123 is connected to the AND gate 128. The AND gates 124 to 128 have the above signals X ₁ to X ₁ respectively.
X ₅ are supplied, the AND gate is turned any one of the signals X ₁ to X ₅ is to "H".
Each output from the AND gates 125 to 128 is sent to the NOR gate 130 via the OR gate 129, and the output from the AND gate 124 is sent to the NOR gate 130. The output from the NOR gate 130 is the inverted circuit 31
Is taken out from the terminal 131 as an output.

In the configuration of FIG. 21, when the delay times of the AND gates 124 to 128 are equal to each other, τ _AND , the delay time of the _OR gate 129 is τ _OR, and the delay time of the NOR gate 130 is τ _NOR , The delay amount τ _X1 of the inverting circuit 31 when X ₁ is selected and becomes “1” is τ _X1 = τ _AND + τ _NOR . Similarly, the delay amounts τ _X2 , τ _X3 , τ _X4 , τ _X5 of the inverting circuit 31 when the signals X ₂ , X ₃ , X ₄ , X ₅ are respectively selected and become “1” are τ _X2 = τ _AND + τ _OR + τ _NOR τ _X3 = τ ₁ + τ _AND + τ _OR + τ _NOR τ _X4 = τ ₁ + τ ₂ + τ _AND + τ _OR + τ _NOR τ _X5 = τ ₁ + τ ₂ + τ ₃ + τ _AND + τ _OR + τ _NOR Therefore, the amount of delay increases in the order in which X ₁ , X ₂ , X ₃ , X ₄ , and X ₅ are selected from X ₁ .

In this case, each of the above-mentioned delay amounts τ selectable for switching.
When setting the _{X1 ~τ X5} is Tonaria' delay amount ratio, for example, tau _X2 / tau _X1, the tau _X3 / tau _X2, etc., preferably aligned below the predetermined value R. The switching condition of the ring delay time is such that, for example, when the measured value of the ring oscillator cycle T _RN (the value when the master clock cycle T _MC is 1) is equal to or less than the lower limit value k _{MIN, the} delay amount is increased by one step. If the delay amount is reduced by one step when the delay time is larger than the upper limit value k _MAX, it is necessary to satisfy the relationship of k _MAX / k _MIN > R. This means that if this relationship is not satisfied, for example, R = 2, k _MIN = 1.2, k _MAX =
In the case of 2.0, the delay time is increased by one step when the ring delay time measurement output becomes smaller than the lower limit value k _MIN = 1.2 but very close to 1.2 from the above X ₁ selection. Then, the above X ₂ is selected, but R = τ _X2 /
Since τ _X1 = 2, the ring delay time measurement output is 2.4
It becomes a slightly smaller value. This is the upper limit value k _MAX =
Since the value is larger than 2.0, switching control for reducing the delay time by one step is automatically performed, and the measured output again becomes smaller than the lower limit value k _MIN = 1.2 but closer to 1.2. The above operation is repeated. That is, the delay amount switching operation becomes unstable. From this, the above k
_The need to satisfy the relationship _MAX / k _MIN > R is apparent.

As described above, by automatically switching the delay time of the ring oscillator, a normal PLL operation can be performed even if there are variations in semiconductors, variations in elements due to temperature changes, power supply voltage variations, and the like. For example, mass production design as an LSI can be actually performed. Further, when applied to a PLL, it is possible to cope with a change in the input signal rate of the PLL by changing the master clock, thereby simplifying the circuit configuration.

The present invention is not limited to only the above-described embodiment. For example, the number of bits (the number of stages and the number of elements) of a ring oscillator, the number of bits of a ring delay time measurement output, an edge position signal, an edge detection signal, and the like. The number of bits and the number of stages of a shift register, a latch circuit, and the like for capturing data, the number of bits of other data, and the like are not limited to the illustrated example. In addition, it goes without saying that various changes can be made without departing from the spirit of the present invention.

[0093]

As is apparent from the above description, according to the input signal edge time measuring circuit according to the present invention, the internal state of the ring oscillator formed by connecting an odd number of inverting elements in a ring shape is represented by RF. the first latch means in edge detection timing of the input signal RF _in, also takes in each second latching means at the timing of the master clock MCK, the first of these, the difference in the state of being incorporated into the second latch means Is expressed as time and taken out as an edge position signal, so that the input edge position (edge time ) Can be measured, and the edge time of the input signal can be measured with high accuracy.

By applying this input signal edge time measuring circuit to a digital PLL device, good operation is possible regardless of the master clock frequency (even if the frequency is close to the reproduction clock frequency). Even if the clock frequency is low, the accuracy of the edge time does not change, so that it is possible to provide a digital PLL device in which the error rate does not deteriorate as compared with the case where the master clock is high.

Here, the output from the first latch means is used as an edge position calculating means for determining the difference between the states taken in the first and second latch means at the rising timing of the master clock. The third latch means for taking in and the fourth latch means for taking in the output from the first latch means at the falling timing of the master clock, and the edge of the input signal is "H"("H") of the master clock. The output from the third latch means is provided during the high level section, and the output from the fourth latch means is provided when the edge of the input signal is in the "L" (low level) section of the master clock. By selecting and comparing the output with the output from the second latch means, the master clock edge approaches the input edge. It is possible to prevent malfunction due to.

Further, the ring oscillator is constituted by using an inverting element having a variable delay time, and the delay time is switched and selected according to the ratio between the master clock cycle and the oscillation operation cycle of the ring oscillator. Normal operation is guaranteed even if the delay time varies, and the LSI
Mass production design becomes possible.

[Brief description of the drawings]

FIG. 1 shows a digital PL as an embodiment according to the present invention.
FIG. 3 is a block circuit diagram illustrating a schematic configuration of an edge time measuring circuit section of an input signal of the L device.

FIG. 2 is a circuit diagram showing a configuration example of a ring oscillator used in the embodiment.

FIG. 3 is a timing chart for explaining an operation of the ring oscillator shown in FIG. 2;

FIG. 4 is a timing chart for explaining an edge detection operation of an input signal.

FIG. 5 is a timing chart for explaining an edge position detection operation of an input signal.

FIG. 6 is a circuit diagram showing a specific example of a binary conversion circuit.

FIG. 7 shows a digital PL as one embodiment according to the present invention.
FIG. 3 is a block circuit diagram illustrating a schematic configuration of a phase synchronization circuit unit of the L device.

FIG. 8 is a diagram illustrating a specific example of a signal value representing an edge position.

FIG. 9 is a diagram for explaining calculation of an edge position where a phase error is 0;

FIG. 10 is a block circuit diagram showing a specific example of a window generator in FIG. 7;

11 is a diagram for explaining the operation of the window generator in FIG.

FIG. 12 is a block circuit diagram showing a specific configuration example of a window circuit in FIG. 7 and circuits in the vicinity thereof.

FIG. 13 is a block circuit diagram showing a specific example of a reproduction clock one cycle length measuring circuit.

FIG. 14 is a timing chart for explaining erroneous detection of an input edge position.

FIG. 15 is a block circuit diagram showing a schematic configuration of an input signal edge time measurement circuit unit which prevents erroneous detection of an input edge position.

FIG. 16 is a timing chart for explaining the operation of the circuit of FIG. 15;

FIG. 17 is a circuit diagram showing a main configuration of another specific example for preventing erroneous detection of an input edge position.

FIG. 18 is a timing chart for explaining the operation of the circuit in FIG. 17;

FIG. 19 is a block circuit diagram showing a specific configuration example of a ring delay time measurement circuit and a ring delay selection circuit in FIG.

FIG. 20 is a block circuit diagram showing a specific example of a ring oscillator capable of switching and selecting a delay time.

FIG. 21 is a circuit diagram showing a specific example of an inverting circuit used in a ring oscillator capable of switching and selecting a delay time.

[Explanation of symbols]

11 RF signal input terminal 12 Master clock signal input terminal 13, 14, 74, 77, 78 ... Flip-flop 15, 22 ... Exclusive OR ( Ex-OR) circuit 23, 24, 27, 59 ... flip-flop circuit unit 25, 28 ... binary conversion circuit 26, 55 ... subtractor 30, 30 ', 30 " ············································································································· 9-bit shift register 52 ········· ... Reproduction clock 1 cycle length window circuit 53... Reproduction clock cycle latch circuit 54... Edge position integer part decoder 56... 6-bit parallel 9-bit shift register 57. ······ 1/4 circuit 61 ··· Reproduced clock 1 cycle length measurement value supply terminal 62, 64, 66 ··· Adder 63 ··· Latch circuit 67 ··· ..Window generator 71... Comparator 72... 3 bit counter

Claims (6)

(57) [Claims] 1. A ring oscillator comprising an odd number of inverting elements connected in a ring, means for detecting an edge of an input signal, and the state of each stage of the ring oscillator is determined by the timing of the detected edge of the input signal. A first latch means for capturing the state of each stage of the ring oscillator at a master clock timing, and a state of each stage of the ring oscillator captured by the first latch means. Edge position calculating means for comparing the state of each stage of the ring oscillator taken in by the second latch means, expressing the difference between these states in time, and outputting it as an edge position signal. Characteristic input signal edge time measurement circuit. 2. The edge position calculation means includes: third latch means for taking in an output from the first latch means at a rising timing of the master clock;
And a fourth latch means for taking in the output from the latch means at the falling timing of the master clock.
The edge of the input signal is "H" of the master clock.
The output from the third latch means is in the (high level) section, and the output from the fourth latch means is in the "L" (low level) section of the master clock when the edge of the input signal is in the "L" (low level) section. 2. The circuit for measuring the edge time of an input signal according to claim 1, wherein each of them is selected and compared with an output from said second latch means. 3. The ring oscillator comprises an inverting element having a variable delay time, and switches and selects the delay time according to a ratio of an oscillation operation cycle of the ring oscillator to a cycle of the master clock. The edge time measuring circuit for an input signal according to claim 1. 4. A ring oscillator comprising an odd number of inverting elements connected in a ring, means for detecting an edge of an input signal, and the state of each stage of the ring oscillator is determined by the timing of the detected edge of the input signal. A first latch means for capturing the state of each stage of the ring oscillator at a master clock timing, and a state of each stage of the ring oscillator captured by the first latch means. Edge position calculating means for comparing the states of the respective stages of the ring oscillator taken in by the second latch means, expressing the difference between these states in time and outputting them as edge position signals, and sampling the input signal with a master clock Means for detecting the presence or absence of an edge of the input signal in master clock units and outputting the same as an edge detection signal; Reproduction clock generating means for outputting a reproduction clock based on the difference data and the reproduction clock cycle data; and obtaining the phase error data between the reproduction clock and an input signal edge based on the edge position signal and the edge detection signal. A phase error detecting means for transmitting to the clock generating means; and a reproduced clock cycle detecting means for detecting periodic data of the reproduced clock from the reproduced clock generating means and transmitting the data to the reproduced clock generating means. Digital PLL device. 5. The edge position calculating means includes: third latch means for capturing an output from the first latch means at a rising timing of the master clock;
And a fourth latch means for taking in the output from the latch means at the falling timing of the master clock.
The edge of the input signal is "H" of the master clock.
The output from the third latch means is in the (high level) section, and the output from the fourth latch means is in the "L" (low level) section of the master clock when the edge of the input signal is in the "L" (low level) section. 5. The digital PLL device according to claim 4, wherein each of the selected signals is selected and compared with an output from said second latch means. 6. The ring oscillator includes an inverting element having a variable delay time, and switches and selects the delay time in accordance with a ratio of an oscillation operation cycle of the ring oscillator to a cycle of the master clock. The digital PLL device according to claim 4, wherein