JPS62132406A - Sinusoidal wave generator - Google Patents
Sinusoidal wave generatorInfo
- Publication number
- JPS62132406A JPS62132406A JP27152685A JP27152685A JPS62132406A JP S62132406 A JPS62132406 A JP S62132406A JP 27152685 A JP27152685 A JP 27152685A JP 27152685 A JP27152685 A JP 27152685A JP S62132406 A JPS62132406 A JP S62132406A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- frequency
- frequency division
- signal
- sine wave
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は、正弦波をデジタル的に発生する正弦波発生器
に係り、特に、低次の高調波を低減した正弦波をデジタ
ル的に発生するのに好適な正弦波発生器に関する。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a sine wave generator that digitally generates a sine wave, and particularly to a sine wave generator that digitally generates a sine wave with reduced lower harmonics. This invention relates to a sine wave generator suitable for.
［発明の背景］
正弦波をデジタル的に発生する従来の正弦波・発生器の
一例として、流通角制量を行ない、低次の高調波を消去
した矩形波を発生させて用いる方法が特開昭６０−６５
６０４に示されている。その正弦波発生器を第３図によ
つズ説明する。[Background of the Invention] As an example of a conventional sine wave generator that digitally generates a sine wave, a method for generating and using a rectangular wave with flow angle control and eliminating lower harmonics has been disclosed in Japanese Patent Application. Showa 60-65
604. The sine wave generator will be explained in detail with reference to FIG.
入力端子１に加えるクロック信号は、Ｍ分周回路１２で
１／Ｍに分周され、さらＫ、５分周回路３で１／Ｓに分
周された後、２分周回路４および。The clock signal applied to the input terminal 1 is frequency-divided to 1/M by the M frequency divider circuit 12, further divided to 1/S by the K, 5 frequency divider circuit 3, and then to the 2 frequency divider circuit 4.
スイッチ回路５に供給される。２分周回Ｗ８４で１／２
Ｖｃ分周された信号はスイッチ回路５に供給され、この
スイッチ回路５は５分周回路５の出力信号によってオン
、オフ制御される。これにより、スイッチ回路５から流
通角１２０ａの矩形波が得られる＠
ここで、入力端子１に加えられるクロック信号の周波数
をｆとし、出力端子１１から出力される正弦波の周波数
をＰとすると、
ｆ＝２ｘｓｘＭｘｐ＝６ｘＭｘｐ
となる。つまり、かかる従来の正弦波発生器では、その
人力クロック信号の周波数は出力信号・の周波数の６の
整数倍である必要があり、もし、この条件を満たさない
場合には、条件を満たす６の整数倍であるようなより高
い周波数としてさらに、分周回路を設けるか、あるいは
入力クロックを複数種用い、それらを逐次切り換えるな
どして利用するしかなく、ハードウェアの複、ｌ雑化、
大規模化や、コストの増大を招いていた−６〔発明の目
的〕
本発明の目的は、上記従来技術の欠点を除去。It is supplied to the switch circuit 5. 1/2 with 2 division revolution W84
The Vc frequency-divided signal is supplied to a switch circuit 5, and this switch circuit 5 is controlled on/off by the output signal of the 5 frequency divider circuit 5. As a result, a rectangular wave with a flow angle of 120a is obtained from the switch circuit 5.@Here, if the frequency of the clock signal applied to the input terminal 1 is f, and the frequency of the sine wave output from the output terminal 11 is P, f=2xsxMxp=6xMxp. In other words, in such a conventional sine wave generator, the frequency of the human clock signal must be an integral multiple of 6 of the frequency of the output signal, and if this condition is not met, then To obtain a higher frequency that is an integer multiple, the only option is to provide a frequency divider circuit or use multiple types of input clocks and switch them sequentially, which increases the complexity and complexity of the hardware.
-6 [Object of the Invention] The object of the present invention is to eliminate the drawbacks of the above-mentioned prior art.
し、周波数と分周比が任意の関係にあっても、希望する
周波数の正弦波を簡易に得ることのできるようにした正
弦波発生器を提供することにある。However, it is an object of the present invention to provide a sine wave generator that can easily obtain a sine wave of a desired frequency even if the frequency and division ratio have an arbitrary relationship.
〔発明の概要〕
この目的を達成するために、本発明は、入力される原ク
ロ・ツク信号を、可変分周回路で分周した後、流通角制
御されるようにし、該可変分周回路の分周比を流通角を
制御する回路の状態に応じて変化きせ、全体の分周比が
６の倍数でない場合においても、流通角制御を行なえる
ようにした点に特徴がある。[Summary of the Invention] In order to achieve this object, the present invention divides the input original clock signal by a variable frequency dividing circuit, and then controls the flow angle. A feature of the present invention is that the frequency division ratio of the circuit is changed depending on the state of the circuit for controlling the flow angle, and the flow angle can be controlled even when the overall frequency division ratio is not a multiple of 6.
以下、本発明の実施例を図面により説明する。。 Embodiments of the present invention will be described below with reference to the drawings. .
第１図は本発明による正弦波発生器の一実施例を示すブ
ロック図であって、１は原クロック。FIG. 1 is a block diagram showing an embodiment of a sine wave generator according to the present invention, and 1 is an original clock.
の入力端子、２は可変分周回路、５は５分周回路、４は
２分周回路、５はスイッチ回路、６は電圧端子、７．８
は抵抗、９は低域Ｐ波器、１０はデコード回路、１１は
出力端子である。また第。input terminal, 2 is a variable frequency divider circuit, 5 is a 5 frequency divider circuit, 4 is a 2 frequency divider circuit, 5 is a switch circuit, 6 is a voltage terminal, 7.8
9 is a resistor, 9 is a low-frequency P wave generator, 10 is a decoding circuit, and 11 is an output terminal. See you again.
２図は第１図の各部の信号を示す波形図であり、第１図
の信号に対応する信号には同一符号をつけている。FIG. 2 is a waveform diagram showing signals at various parts in FIG. 1, and signals corresponding to those in FIG. 1 are given the same symbols.
次に、この実施例の動作を説明する。Next, the operation of this embodiment will be explained.
第１図および第２図において、入力端子１より入力され
るデジタル波形のクロック信号Ａは可変分周回路２に供
給される。可変分周回路２では、デコーダ１０から入力
される分周比切り換え信号Ｂによって、分周比が１／ｓ
５および１１５４と切換えられる。この可変分周回路２
の出力信号Ｃは５分周回路Ｓに入力されて１／、 ｔ、
ｃ分周され、この５分周回路５の出力は、さらに、２分
周回路４へ入力されて１／２に分周されると共に・。In FIGS. 1 and 2, a digital waveform clock signal A input from an input terminal 1 is supplied to a variable frequency divider circuit 2. In FIG. In the variable frequency divider circuit 2, the frequency division ratio is set to 1/s by the frequency division ratio switching signal B input from the decoder 10.
5 and 1154. This variable frequency divider circuit 2
The output signal C is input to the divide-by-5 circuit S and is divided into
The output of the divide-by-5 circuit 5 is further input to the divide-by-2 circuit 4, where the frequency is divided into 1/2.
スイッチ回路５の切断信号となる。この２分周・回路４
の出力信号Ｅはスイッチ回路５に入力さ・れる。スイッ
チ回路５はＳ分周回路５の出方信号りの高レベル期間オ
ンする。そこで、スイッチ回路の出力端子を、電圧端子
６と接地間に設けた抵抗７．８によってその中間電位に
保持しておくことにより、スイッチ回路５からは、図示
する矩形波形の信号Ｆが得られる。デコード回路１０は
、５分周回＃８５．２分周回路４の出力に応じて分周比
切り換え信号Ｂを発生する。This serves as a disconnection signal for the switch circuit 5. This divide-by-2 circuit 4
The output signal E is input to the switch circuit 5. The switch circuit 5 is turned on during the period when the output signal of the S frequency divider circuit 5 is at a high level. Therefore, by holding the output terminal of the switch circuit at an intermediate potential by a resistor 7.8 provided between the voltage terminal 6 and the ground, a signal F having a rectangular waveform as shown in the figure can be obtained from the switch circuit 5. . The decoding circuit 10 generates a frequency division ratio switching signal B in response to the output of the frequency division circuit 4 for frequency division by 5 #85.2.
このように、この実施例によれば、スイッチ回路５の出
力信号は、原クロツク信号Ａを′／２ｏ。Thus, according to this embodiment, the output signal of the switch circuit 5 is the original clock signal A by '/2o.
Ｋ分周したものとなっており、従来では、′／６または
１／（６Ｘ ｎ ） でなければならない全体の分周
比を任意の分周比とすることができる。また・、矩形波
の流通角は１２０．６＠となり、各高調波の歪の減衰量
にル（ｄＢ ’）で示すと、Ｋ２＝■、 Ｋ、 ＝＝
４４．４＜ｄＢ）、 Ｋ４＝ω＊ Ｋｓ ＝’ ４−０
（ｄＢ ）＊ Ｋ６＝ω・Ｋ、＝１６．７ （ｄＢ）
、 Ｋ８＝ ｏｏ 、 Ｋｇ、 ＝ ４４．４ （Ｊ
Ｂ）、 Ｋ＋ｏ ＝ ” ・・・・・どなる。このため
に、後段に挿入する低域Ｐ波器９としては、主として５
以上の高調波の減衰特性を考慮すればよく、構成が簡単
で低価格なものでよく、また、場合によっては、ｆ波器
なしでも充分に所期の目的をはだすことも可能である。The frequency is divided by K, and the overall frequency division ratio, which conventionally must be '/6 or 1/(6X n ), can be set to any desired frequency division ratio. Also, the circulation angle of the rectangular wave is 120.6 @, and the attenuation of distortion of each harmonic is expressed in le (dB'), K2=■, K, ==
44.4<dB), K4=ω* Ks=' 4-0
(dB) *K6=ω・K,=16.7 (dB)
, K8=oo, Kg, = 44.4 (J
B), K+o = ” ..... For this reason, the low-frequency P wave generator 9 inserted in the latter stage is mainly 5
It is sufficient to take into account the above harmonic attenuation characteristics, and the structure may be simple and inexpensive, and in some cases, it is possible to achieve the desired purpose without an f-wave device.
〔発明の効果〕
以上説明したように、本発明によれば、従来実現が困難
であった任意の周波数と分周比の条件においても、流通
角制御することができるので、希望する正弦波を容易に
得られるという効果がある。[Effects of the Invention] As explained above, according to the present invention, it is possible to control the flow angle even under conditions of arbitrary frequency and frequency division ratio, which was difficult to realize in the past, so that the desired sine wave can be generated. It has the advantage of being easily obtainable.
第１図は本発明による正弦波発生器の一実施例を示すブ
ロック図、第２図は第１図の各部の＝信号を示す波形図
、第３図は従来の正弦波発生・器の一例を示すブロック
図である。
１・・・入力端子、２・・・可変分周回路、５・・・５
分・周回路、４・・・２分周回路、５・・・スイッチ回
路、・６・・・電圧端子、７．８・・・抵抗、９・・・
低蛾ｒ波器−１１０・・・デコード回路、１１・・・出
力端子。
！慟−Fig. 1 is a block diagram showing an embodiment of a sine wave generator according to the present invention, Fig. 2 is a waveform diagram showing = signals of each part in Fig. 1, and Fig. 3 is an example of a conventional sine wave generator/device. FIG. 1...Input terminal, 2...Variable frequency divider circuit, 5...5
Divider/frequency circuit, 4...2 frequency divider circuit, 5...Switch circuit, 6...Voltage terminal, 7.8...Resistor, 9...
Low moth r wave device-110...decoding circuit, 11...output terminal. ! Lagoon
Claims (2)
該第１の分周回路の出力信号が供給され第２、第３の分
周回路とスイッチ回路とからなる流通角制御回路とを備
え、出力される矩形波の流通角を制御することにより、
該矩形波の所定の高調波を減衰させて正弦波を生成可能
とした正弦波発生器において、前記第１の分周回路を可
変分周回路とし、前記第２、第３の分周回路の状態に応
じて前記第１の分周回路の分周比を切換えることを特徴
とする正弦波発生器。(1) a first frequency divider circuit that frequency divides an input clock signal;
A flow angle control circuit including a second and third frequency divider circuit and a switch circuit is supplied with the output signal of the first frequency divider circuit, and controls the flow angle of the output rectangular wave.
In the sine wave generator capable of generating a sine wave by attenuating a predetermined harmonic of the rectangular wave, the first frequency dividing circuit is a variable frequency dividing circuit, and the second and third frequency dividing circuits are A sine wave generator characterized in that the frequency division ratio of the first frequency dividing circuit is switched depending on the state.
回路を３分周回路とし、前記第３の分周回路を２分周回
路としたことを特徴とする正弦波発生器。(2) The sine wave generator according to claim 1, wherein the second frequency dividing circuit is a frequency dividing circuit by three, and the third frequency dividing circuit is a frequency dividing circuit by two.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27152685A JPS62132406A (en) | 1985-12-04 | 1985-12-04 | Sinusoidal wave generator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27152685A JPS62132406A (en) | 1985-12-04 | 1985-12-04 | Sinusoidal wave generator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62132406A true JPS62132406A (en) | 1987-06-15 |
| JPH0462604B2 JPH0462604B2 (en) | 1992-10-07 |
Family
ID=17501292
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27152685A Granted JPS62132406A (en) | 1985-12-04 | 1985-12-04 | Sinusoidal wave generator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62132406A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04242891A (en) * | 1991-01-08 | 1992-08-31 | Kubota Corp | Robbery preventing device |
| JPH0629745A (en) * | 1991-12-28 | 1994-02-04 | Intaanix Kk | Partial pulse height type reference frequency generating circuit for phase locked loop |
| JPH0666122U (en) * | 1993-12-16 | 1994-09-16 | 株式会社三陽電機製作所 | Sine wave generator for uninterruptible power supply |
-
1985
- 1985-12-04 JP JP27152685A patent/JPS62132406A/en active Granted
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04242891A (en) * | 1991-01-08 | 1992-08-31 | Kubota Corp | Robbery preventing device |
| JPH0629745A (en) * | 1991-12-28 | 1994-02-04 | Intaanix Kk | Partial pulse height type reference frequency generating circuit for phase locked loop |
| JPH0666122U (en) * | 1993-12-16 | 1994-09-16 | 株式会社三陽電機製作所 | Sine wave generator for uninterruptible power supply |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0462604B2 (en) | 1992-10-07 |
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