JPH0462604B2 - - Google Patents
Info
- Publication number
- JPH0462604B2 JPH0462604B2 JP27152685A JP27152685A JPH0462604B2 JP H0462604 B2 JPH0462604 B2 JP H0462604B2 JP 27152685 A JP27152685 A JP 27152685A JP 27152685 A JP27152685 A JP 27152685A JP H0462604 B2 JPH0462604 B2 JP H0462604B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- frequency divider
- divider circuit
- frequency
- output signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
- 230000003111 delayed effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Landscapes
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は、正弦波をデジタル的に発生する正弦
波発生器に係り、特に、低次の高調波を低減した
正弦波をデジタル的に発生するのに好適な正弦波
発生器に関する。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a sine wave generator that digitally generates a sine wave, and particularly to a sine wave generator that digitally generates a sine wave with reduced lower harmonics. This invention relates to a sine wave generator suitable for.
正弦波をデジタル的に発生する従来の正弦波発
生器の一例として、流通角制御を行ない、低次の
高調波を消去した矩形波を発生させて用いる方法
が特開昭60−65604に示されている。その正弦波
発生器を第３図によつて説明する。
As an example of a conventional sine wave generator that digitally generates sine waves, Japanese Patent Laid-Open Publication No. 65604/1983 shows a method that controls the flow angle and generates and uses a rectangular wave that eliminates lower harmonics. ing. The sine wave generator will be explained with reference to FIG.
入力端子１に加えるクロツク信号は、Ｍ分周回
路１２で１／Ｍに分周され、さらに、３分周回路
３で1/3に分周された後、２分周回路４およびス
イツチ回路５に供給される。２分周回路４で1/2
に分周された信号はスイツチ回路５に供給され、
このスイツチ回路５は３分周回路３の出力信号に
よつてオン，オフ制御される。これにより、スイ
ツチ回路５から流通角120゜の矩形波が得られる。 The clock signal applied to the input terminal 1 is frequency-divided by 1/M by the M frequency divider circuit 12, further divided by 1/3 by the 3-frequency divider circuit 3, and then sent to the 2-frequency divider circuit 4 and the switch circuit 5. is supplied to 1/2 with 2 frequency divider circuit 4
The frequency-divided signal is supplied to the switch circuit 5,
This switch circuit 5 is controlled on and off by the output signal of the frequency divider circuit 3. As a result, a rectangular wave with a flow angle of 120° is obtained from the switch circuit 5.
ここで、入力端子１に加えられるクロツク信号
の周波数をとし、出力端子１１から出力される
正弦波の周波数をｐとすると、
＝２×３×Ｍ×ｐ＝６×Ｍ×ｐ
となる。つまり、かかる従来の正弦波発生器で
は、その入力クロツク信号の周波数は出力信号の
周波数の６の整数倍である必要があり、もし、こ
の条件を満たさない場合には、条件を満たす６の
整数倍であるようなより高い周波数としてさら
に、分周回路を設けるか、あるいは入力クロツク
を複数種用い、それらを逐次切り換えるなどして
利用するしかなく、ハードウエアの複雑化，大規
模化や、コストの増大を招いていた。 Here, if the frequency of the clock signal applied to the input terminal 1 is set and the frequency of the sine wave outputted from the output terminal 11 is set to p, then =2 x 3 x M x p = 6 x M x p. In other words, in such a conventional sine wave generator, the frequency of its input clock signal must be an integer multiple of 6 than the frequency of its output signal, and if this condition is not met, then In order to obtain a higher frequency that is twice as high, the only option is to install a frequency divider circuit or use multiple types of input clocks and switch them sequentially, which increases the complexity and scale of the hardware and increases the cost. This led to an increase in
本発明の目的は、上記従来技術の欠点を除去
し、周波数と分周化が任意の関係にあつても、希
望する周波数の正弦波を簡易に得ることのできる
ようにした正弦波発生器を提供することにある。
An object of the present invention is to provide a sine wave generator that eliminates the drawbacks of the above-mentioned prior art and allows a sine wave of a desired frequency to be easily obtained even if the frequency and frequency division have an arbitrary relationship. It is about providing.
この目的を達成するために、本発明は、入力さ
れる原クロツク信号を、可変分周回路で分周した
後、流通角制御されるようにし、該可変分周回路
の分周比を流通角を制御する回路の状態に応じて
変化させ、全体の分周比が６の倍数でない場合に
おいても、流通角制御を行なえるようにした点に
特徴がある。
In order to achieve this object, the present invention divides the frequency of an input original clock signal by a variable frequency divider circuit and then controls the flow angle, and sets the frequency division ratio of the variable frequency divider circuit to the flow angle. The characteristic is that the flow angle can be controlled even when the overall frequency division ratio is not a multiple of 6 by changing it according to the state of the circuit to be controlled.
以下、本発明の実施例を図面により説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第１図は本発明による正弦波発生器の一実施例
を示すブロツク図であつて、１は原クロツクの入
力端子、２は可変分周回路、３は３分周回路、４
は２分周回路、５はスイツチ回路、６は電圧端
子、７，８は抵抗、９は低域波器、１０はデコ
ード回路、１１は出力端子である。また第２図は
第１図の各部の信号を示す波形図であり、第１図
の信号に対応する信号には同一符号をつけてい
る。 FIG. 1 is a block diagram showing one embodiment of a sine wave generator according to the present invention, in which 1 is an input terminal of the original clock, 2 is a variable frequency divider circuit, 3 is a frequency divider circuit, 4 is a frequency divider circuit.
2 is a frequency divider circuit, 5 is a switch circuit, 6 is a voltage terminal, 7 and 8 are resistors, 9 is a low frequency filter, 10 is a decoding circuit, and 11 is an output terminal. Further, FIG. 2 is a waveform diagram showing signals of each part in FIG. 1, and signals corresponding to the signals in FIG. 1 are given the same symbols.
次に、この実施例の動作を説明する。 Next, the operation of this embodiment will be explained.
第１図および第２図において、入力端子１より
入力されるデジタル波形のクロツク信号Ａは可変
分周回路２に供給される。可変分周回路２では、
デコーダ回路１０から入力される分周比切換え信
号Ｂが、高レベルの期間では分周比が１／33に、
また低レベルの期間では１／34にそれぞれ切換え
られる。この可変分周回路２の出力信号Ｃは３分
周回路３に入力されて1/3に分周され、この３分
周回路３の出力は、さらに、２分周回路４へ入力
されて1/2に分周されると共に、スイツチ回路５
の切断信号となる。この２分周回路４の出力信号
Ｅはスイツチ回路５に入力される。スイツチ回路
５は、３分周回路３の出力信号Ｄの高レベル期間
にオンし、低レベル期間にオフする。オンの状態
では、出力信号Ｅがそのまま信号Ｆとなつて低域
波器９に入力される。一方、スイツチ回路５が
オフの状態では、信号Ｆは電源端子６と接地間に
設けた抵抗７，８によつて中間電位になる。この
結果、信号Ｆは第２図に示すように３値波形とな
る。デコード回路１０は、３分周回路３の出力信
号Ｄ、２分周回路４の出力信号Ｅに応じて分周比
切り換え信号Ｂを発生するが、本実施例では、信
号Ｂは信号Ｄを単に遅延させている。 1 and 2, a digital waveform clock signal A input from an input terminal 1 is supplied to a variable frequency divider circuit 2. In FIG. In the variable frequency divider circuit 2,
When the frequency division ratio switching signal B input from the decoder circuit 10 is at a high level, the frequency division ratio becomes 1/33.
In addition, during the low level period, it is switched to 1/34. The output signal C of this variable frequency divider circuit 2 is inputted to a frequency divider circuit 3 and divided into 1/3, and the output of this frequency divider circuit 3 is further inputted to a frequency divider circuit 4 and divided into 1/3. /2, and the switch circuit 5
It becomes a disconnection signal. The output signal E of this divide-by-2 circuit 4 is input to a switch circuit 5. The switch circuit 5 is turned on during the high level period of the output signal D of the frequency divider circuit 3, and turned off during the low level period. In the on state, the output signal E becomes the signal F as it is and is inputted to the low frequency converter 9. On the other hand, when the switch circuit 5 is off, the signal F has an intermediate potential due to the resistors 7 and 8 provided between the power supply terminal 6 and the ground. As a result, the signal F has a ternary waveform as shown in FIG. The decoding circuit 10 generates the division ratio switching signal B according to the output signal D of the frequency divider 3 and the output signal E of the divider 2 circuit 4, but in this embodiment, the signal B is simply the signal D. It's delayed.
このように、この実施例によれば、スイツチ回
路５の出力信号は、原クロツク信号Ａを1/200
（1/200＝１／（（33＋34＋33）×２））に分周した
ものとなつており、従来では、1/6または１／
（６×ｎ）でなければならない全体の分周比を任
意の分周比とすることができる。また、矩形波の
流通角は120.6゜となり、各高調波の歪の減衰量Ko
（dB）で示すと、K2＝∞，K3＝44.4（dB），K4＝
∞，K5＝14.0（dB），K6＝∞，K7＝16.7（dB），K8
＝∞，K9＝44.4（dB），K10＝∞……となる。この
ために、後段に挿入する低域波器９としては、
主として５以上の高調波の減衰特性を考慮すれば
よく、構成が簡単で低価格なものでよく、また、
場合によつては、波器なしでも充分に所期の目
的をはたすことも可能である。 Thus, according to this embodiment, the output signal of the switch circuit 5 is 1/200 of the original clock signal A.
(1/200=1/((33+34+33)×2)), and conventionally, it is 1/6 or 1/200.
The overall frequency division ratio, which must be (6×n), can be any frequency division ratio. Also, the distribution angle of the rectangular wave is 120.6°, and the attenuation amount of distortion of each harmonic is K o
Expressed in (dB), K 2 = ∞, K 3 = 44.4 (dB), K 4 =
∞, K 5 = 14.0 (dB), K 6 = ∞, K 7 = 16.7 (dB), K 8
= ∞, K 9 = 44.4 (dB), K 10 = ∞... For this reason, the low frequency device 9 inserted in the latter stage is as follows:
It is sufficient to mainly consider the attenuation characteristics of harmonics of 5 or more, the configuration is simple and inexpensive, and
In some cases, it may be possible to achieve the intended purpose without a waver.
以上説明したように、本発明によれば、従来実
現が困難であつた任意の周波数と分周比の条件に
おいても、流通角制御することができるので、希
望する正弦波を容易に得られるという効果があ
る。
As explained above, according to the present invention, it is possible to control the flow angle even under conditions of arbitrary frequency and frequency division ratio, which was difficult to achieve in the past, so it is possible to easily obtain the desired sine wave. effective.
第１図は本発明による正弦波発生器の一実施例
を示すブロツク図、第２図は第１図の各部の信号
を示す波形図、第３図は従来の正弦波発生器の一
例を示すブロツク図である。
１…入力端子、２…可変分周回路、３…３分周
回路、４…２分周回路、５…スイツチ回路、６…
電圧端子、７，８…抵抗、９…低域波器、１０
…デコード回路、１１…出力端子。
FIG. 1 is a block diagram showing an embodiment of a sine wave generator according to the present invention, FIG. 2 is a waveform diagram showing signals of each part in FIG. 1, and FIG. 3 is an example of a conventional sine wave generator. It is a block diagram. 1...Input terminal, 2...Variable frequency divider circuit, 3...3 frequency divider circuit, 4...2 frequency divider circuit, 5...Switch circuit, 6...
Voltage terminal, 7, 8...Resistance, 9...Low frequency device, 10
...Decode circuit, 11...Output terminal.
Claims (1)
と、該可変分周回路に直列接続される第１の分周
回路、第２の分周回路、スイツチ回路および電圧
端子と抵抗で構成されるレベル設定回路を備え、 上記第１もしくは第２の分周回路のうち、少な
くとも一方の出力信号に応じて、上記可変分周回
路に予じめ定められた複数の分周比を切換えるた
めの制御信号発生回路を備え、 上記第２の分周回路の出力信号を、上記第１の
分周回路の出力信号によつて、上記スイツチ回路
で切換えることによつて３値波形を出力するよう
に構成したことを特徴とする正弦波発生器。[Claims] 1. A variable frequency divider circuit that frequency divides an input clock signal, a first frequency divider circuit, a second frequency divider circuit, a switch circuit, and a voltage terminal connected in series to the variable frequency divider circuit. A level setting circuit configured with a resistor is provided, and a plurality of predetermined frequency dividing ratios are set in the variable frequency dividing circuit according to an output signal of at least one of the first or second frequency dividing circuit. and a control signal generation circuit for switching the output signal of the second frequency divider circuit, and generates a ternary waveform by switching the output signal of the second frequency divider circuit with the output signal of the first frequency divider circuit using the switch circuit. A sine wave generator configured to output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27152685A JPS62132406A (en) | 1985-12-04 | 1985-12-04 | Sinusoidal wave generator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27152685A JPS62132406A (en) | 1985-12-04 | 1985-12-04 | Sinusoidal wave generator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62132406A JPS62132406A (en) | 1987-06-15 |
| JPH0462604B2 true JPH0462604B2 (en) | 1992-10-07 |
Family
ID=17501292
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27152685A Granted JPS62132406A (en) | 1985-12-04 | 1985-12-04 | Sinusoidal wave generator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62132406A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2836644B2 (en) * | 1991-01-08 | 1998-12-14 | 株式会社クボタ | Anti-theft device |
| JP2733528B2 (en) * | 1991-12-28 | 1998-03-30 | インターニックス株式会社 | Partial pulse height reference frequency generator for phase locked loop |
| JP2508472Y2 (en) * | 1993-12-16 | 1996-08-21 | 株式会社三陽電機製作所 | Sine wave generator for uninterruptible power supply |
-
1985
- 1985-12-04 JP JP27152685A patent/JPS62132406A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62132406A (en) | 1987-06-15 |
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