JP2715210B2 - Partial-integral switching type reference frequency generation method for phase locked loop, and reference frequency generation circuit thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of generating a reference frequency of a partial integration switching type for generating a reference input signal of a phase locked loop, and a reference frequency generating circuit thereof.

[0002]

2. Description of the Related Art A frequency synthesizer using a phase-locked loop (PLL) uses a high-precision fixed reference frequency generator, and has been used in many fields as a means for generating almost any frequency while maintaining its frequency accuracy. Used in
And as a high-precision reference frequency generator, ambient temperature,
When it is required to maintain a constant value with respect to a wide range of circuit load, power supply voltage, etc., a combination of a so-called crystal oscillation circuit with a TTL-IC, a CMOS-IC, or the like is often used. I have. However, such a frequency synthesizer changes the frequency divider in the phase-locked loop to obtain the desired output frequency, so that the loop gain changes depending on the frequency division ratio, and the settling time greatly changes. I do. Furthermore, it is difficult to obtain stability with a fast settling time, so it is generally used in over-damping.However, in such a combination, it is difficult to freely obtain an arbitrary frequency, so that it is usually extremely extreme. A high clock source had to be used.

FIG. 11 shows a conventional example of a frequency synthesizer using a phase locked loop. That is, as is well known, the phase locked loop is composed of a phase comparator (PC) 1, a low-pass filter (LPF) 2, an amplifier (A) 3, a voltage controlled oscillator (VCO) 4, and the like. The oscillation frequency f _O of the voltage controlled oscillator 4 in the frequency synthesizer using the loop is as follows, and the single frequency from the crystal oscillation circuit 7 is determined by the division ratios m and n of the frequency division circuits 5 and 6. Various oscillation frequencies can be obtained based on the oscillation frequency fr.

[0004]

(Equation 1)

In a conventional frequency synthesizer using a phase-locked loop, since there is no requirement for high-speed settling, an arbitrary frequency can be set by a combination of the dividing ratio n in the dividing circuit 6 and the dividing ratio m in the dividing circuit 5. Is occurring. However, there is also a problem that the stability and settling time of the phase-locked loop change depending on the frequency division ratio m of the frequency divider 5 in the phase-locked loop.

For this reason, in recent years, a method for realizing a frequency synthesizer using a stable variable frequency source instead of the fixed frequency source which is the crystal oscillation circuit 7 as shown in FIG. 11 is disclosed in, for example, US Pat. No. 4,965,533. And US Patent No. 5
No. 028887 and the like. That is, a reference frequency is generated by a direct digital synthesizer (DDS) as a stable variable frequency source, and a frequency synthesizer in which a phase locked loop is driven by the direct digital synthesizer, a so-called DDS drive type frequency synthesizer Is the emergence of

FIG. 12 shows a conventional example of a DDS drive type frequency synthesizer. This DDS drive type frequency synthesizer is a direct digital synthesizer 10
A phase lock loop 20 including a phase detector 21, a loop filter 22, a voltage controlled oscillator (VCO) 23, and a fixed frequency divider 24 connecting the voltage controlled oscillator 23 and the phase detector 21 is provided at the next stage. The configuration is connected. However, the direct digital synthesizer 1
Since the frequency step required for 0 is a decimal point dividing operation, the desired frequency cannot be generated only by the digital circuit.

FIG. 13 is a diagram showing the direct digital
FIG. 15 is a block diagram showing the synthesizer 10 in more detail, and shows an accumulator 3 including an accumulator (accumulator) 30a and a register 30b as shown in FIG.
The following is a description of a simplified model in which 0 is 4 bits. That is, when used in f _CL = 16MH _Z clock, setting the accumulator 30 a phase increment Δθ as binary data, the reference frequency f _R is

[0009]

(Equation 2) Given by

Therefore, in order to obtain an arbitrary frequency, the phase increment Δθ may be varied. This can be called an accumulator divider, so to speak.
Fig. 3 shows the frequency division mechanism and the sawtooth wave as its output waveform. As is apparent from FIG. 15, the increment value / clock differs depending on the phase increment value Δθ.

Therefore, when the phase increment value Δθ is changed from 24 ° to 44 °, the sine LUT shown in FIG.
The output waveform of the (look-up table) 31 is shown in FIG.
The digital value of the step-like sine wave shown in FIG. 6 is obtained. FIG. 17 shows the state of the clock shift based on the generated waveform with the phase increment value Δθ set to 22.5 °.

This accumulator frequency divider only functions as a periodic function generator, passes the digital value of the staircase sawtooth wave output from the accumulator through the sine LUT 31, and reads the digital data value of the sine wave.

Next, the digital data value of the sine wave is applied to the D / A converter 32 in the next stage to convert the sine wave into an analog waveform, and the analog-converted output signal is converted to a high-order L in the next stage.
The signal is supplied to a PF (high-order low-pass filter) 33 to perform smoothing (interpolation) and remove a clock frequency component.

The output from the high-order LPF 33 is applied to a high-pass filter (HPF) 34 at the next stage, where the D / D
Eliminates in-band jitter due to quantization errors and other errors during A-conversion. And this high-pass filter 3
The output from 4 is converted to a digital signal again,
The signal is supplied to a high gain AC coupling comparator 35 which is connected to the next stage and includes a capacitor C and an analog voltage comparator 35a. An output signal from the AC coupling comparator 35 becomes a reference frequency output f _{R of the} direct digital synthesizer 10. , Driving the phase locked loop.

In this case, the higher the gain of the AC coupling comparator 35 is, the smaller the jitter can be.
13, point A, point B, point C and point D in FIG.
Each output waveform at the point (MSB at point A) is a waveform shown in FIG. Further, when the decimal point division N = 7.2, the waveform similarly becomes as shown in FIG. 19, and the waveform is different for each cycle at the same time as the start point and the end point are shifted. As shown by 20, the MSB bit output in FIG. 14 draws the same sequence every five periods, so that it can be seen that there is periodicity. Therefore, if this is the case, the frequency differs for each cycle, and the reference frequency f
Since it cannot be used as _R , the signal is once converted to an analog signal using the sine LUT 31 and the D / A converter 32 to correct this. This analog signal is converted into a signal having phase continuity at the same time as the clock is removed by the subsequent high-order LPF 33. The signal is further reduced to a digital signal through the subsequent high-pass filter 34, and then converted to a digital signal again. A frequency reference signal is generated through the AC coupling comparator 35 for returning. The conventional DDS drive type frequency synthesizer that operates as described above can also divide a decimal point, so that an arbitrary frequency can be generated.

[0016]

By the way, in the direct digital synthesizer shown in FIG. 13, the sign L is calculated based on the accumulated phase increment regardless of the generation cycle.
The digital data value of the sine wave is read from the UT 31 to perform D / A conversion. However, a D / A converter 32 that performs this conversion requires a high-speed and high-resolution converter.
There is a problem that the cost increases. The frequency accuracy in the case of accumulator frequency division and the accumulator 30
The relationship of the bit width of

[0017]

[Equation 3] Number of bits = INT [0.5 + L _{Og 2} (1 / frequency accuracy)]

, The frequency accuracy is 1 ppm
If (10 ^-6 ), the bit width of the accumulator 30 becomes 20 bits. Since the output waveform of the D / A converter 32 is a step-like sine wave, the D / A converter 3
After 2 is a high-order LPF which is a high-performance low-pass filter
33 is required. In the near future, the reference frequency will be generated by a direct digital synthesizer using a limited number of sample pulses, and the settling time for switching the frequency with high stability in the phase locked loop will be 1 m.
It is expected that digital cellular telephones, digital cordless telephones, digital PBXs (private branch exchanges), etc., which require S or less, will spread.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and it is an object of the present invention to easily perform higher-precision frequency compensation as compared with the related art when generating a reference frequency for driving a phase locked loop. It is an object of the present invention to provide a quasi-frequency generation method for a partial integration type phase-locked loop, which is effective for reducing the cost, and a reference frequency generation circuit thereof.

[0020]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention compares a phase of a self-oscillation output waveform with a reference frequency signal at the same time as receiving the reference frequency signal, and reduces the error thereof. In a method for generating a reference frequency of a phase locked loop that locks or follows a reference frequency by changing an oscillation output frequency, a set phase increment value (Δθ) is accumulated for each clock, and the reference frequency signal is generated. And a polarity inversion point (90 °, 270 °, 450 °,...) Based on the periodic value.
) And a second clock period other than the first clock period, and a phase difference (θB) between the terminal phase value and the polarity inversion point in the first clock period.
Calculating a first integral value (± (Δθ−2θB)) based on the phase increment value (Δθ) and a second integral value (± Δθ) based on the phase increment value (Δθ) And integrating the first integrated value during the first clock period and integrating the second integrated value during the second clock period.

An accumulator for accumulating the digital set value supplied from the phase increment value (Δθ) setting section in synchronization with a predetermined clock, and outputting a phase value, based on the phase value, , The first polarity reversal point (90 °, 450 °, 810)
..), And a second polarity inversion point (270 °, 630)
１,...), A one-cycle component period detecting means including a bottom region integration period detecting section for detecting a clock period including the remaining clock period, and a top region integration period. , A first compensation integral value (+ (Δθ−2θB)) is calculated based on the phase difference (θB) between the terminal phase value and the polarity reversal point and the phase increment value (Δθ). The second compensation integral value (− (Δθ) based on the phase difference (θB) between the terminal phase value and the polarity inversion point in the period and the phase increment value (Δθ).
-2θB)), a first digital-to-analog converter for converting an output from the partial integral compensation value generating means into an analog signal, and an analog value for the phase increment value (Δθ). Second digital-to-analog converting means for converting the signal into a signal, an output of the first digital-to-analog converting means, and an output of the second digital-to-analog converting means are input, and the top region integration period and the bottom region During the integration period, the first digital
Signal switching means for outputting the output of the analog conversion means and outputting the output of the second digital-to-analog conversion means during other periods; integration means for integrating the analog signal input from the signal switching means; A comparator to which the output of the integrating means is input and which outputs a rectangular wave.

Further, on the connection line between the integrating means and the comparator, the area below the boundary level value between the region of the remaining period and the top region of the periodic signal waveform and the residual level are set so that the areas on the positive and negative sides of the periodic signal waveform are equal. It is characterized in that a clipper circuit that limits the amplitude to a value equal to or lower than a boundary level value between the period region and the bottom region and removes a beat is provided, and a low-pass filter that removes a harmonic component is provided at a subsequent stage.

[0023]

According to the present invention, based on the result of accumulating the phase increment value, which is a digital set value corresponding to the reference frequency signal to be applied to the phase locked loop, a periodic signal waveform for each period serving as the reference frequency signal is provided. Compensated partial integration is performed on the top region and the bottom region of the periodic signal waveform, and the compensated partial integrated output and the integrated waveform during the remaining period from the top region to the bottom region or from the bottom region to the top region of the periodic signal waveform are true zero. The compensation partial integration and the integration result during the remaining period are switched and output so as to pass through the cross point, and the reference frequency to the phase locked loop is stably obtained.

When a clipper circuit and a low-pass filter are interposed on the connecting line between the integrating means and the comparator, beat removal is performed by the clipper circuit to equalize the areas on the positive and negative sides of the periodic signal waveform. Becomes possible,
In addition, the low-pass filter allows the signal to be input to the comparator as a clean sine wave with little jitter.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a reference frequency generating circuit according to the present invention. FIG. 2 is a detailed circuit diagram of FIG. 1, and FIG. 3 shows signal waveforms of various parts in the circuit shown in FIG. It is a timing chart.

In the reference frequency generation according to the present invention, a periodic signal is generated using an accumulator, and a desired analog frequency signal is generated using a digital set value of a plurality of bits set in the accumulator and an output of the accumulator. The principle will be described first for convenience of explanation.

The accumulator used in the present invention comprises:
By accumulating a digital set value consisting of a plurality of bits (24 bits in the embodiment described below) arbitrarily set, that is, a phase increment value Δθ in synchronization with a clock of a predetermined frequency f _CL , the MSB (most significant bit) is obtained. forming a periodic function of the frequency f _R which corresponds to a phase increment Δθ from the upper bits). That is, the phase value (period value) of the reference frequency signal
Occurs.

Here, the frequency f_RIs this accumulator
Is 24 bits, f = f_CL・ Δθ / 2²⁴  Given by In this case, the phase increment value Δθ is, for example, 50
If set to ゜, this accumulator will
0, 50, 100, 150, 200, 25
0 ゜, 300 ゜ ... discrete point division values are obtained
You. However, from analog integrator 121, 0 ° to 10 °
The amplitude at 0 ° is +100,
Amplitude is 0, and the amplitude at 200 to 300 degrees is -1.
00, the amplitude becomes 0 at 300 to 400 °
A square waveform is obtained. This triangular waveform is shown in FIG.
Is a solid line representing the amplitude +50 at 0 ° to 50 °, and 50 °
The amplitude +50 at ゜ 100 ° is indicated by a dotted line.

Here, if this waveform is simply integrated, an analog integrated waveform passing through a true zero cross point (180 °, 360 °..., That is, 180 ° × n including 0 °) is obtained. It is not possible. This is because no output is obtained from the accumulator at 90 ° and 270 ° which are the polarity reversal points shown in FIG. Therefore, when the figure is examined in detail, from 50 ° to 100 °, the amplitude at the time of 50 ° is +50 and the amplitude at the time of 100 ° is +80, and the amplitude difference between them is +30.
It is. Then, when examining the phase difference between the clocks,
The time point of 0 ° is 40 ° after the polarity inversion point 90 °, and the time point of 100 ° is 10 ° before the polarity inversion point 90 °, that is, 40 ° −10 ° = 30 °. .

Here, assuming that the phase difference between the polarity inversion point and the subsequent clock timing is θF, θF−θB =
40 ° −10 ° = 30 ° is obtained, and it is understood that the integral slope of (θF−θB) / clock should be generated from 50 ° to 100 °. Similarly, from 250 ° to 300 °
, The amplitude at the time of 250 ° is −70, and the amplitude at the time of 300 ° is −60, and the amplitude difference between them is +70.
It is 10. When the phase difference between the clocks is examined, the time point at 250 ° is 20 ° with respect to the polarity inversion point 270 °.
After 300 °, the point at 300 ° is 30 ° before the polarity reversal point 270 °. Here, as in the above case, if the phase difference between the polarity inversion point and the subsequent clock timing is θB and the phase difference between the polarity inversion point and the previous clock timing is θF, then θB−θF = 30 ° − 20
° = 10 ° and from 250 ° to 300 ° (θB
It can be seen that an integral slope of −θF) / clock may be generated.

That is, in FIG. 5, assuming that the analog integrated waveform passes through the zero cross point (180 °, 360 °...), Since it is known that Δθ = 50 °, θ
F-θB and θB-θF are determined by an appropriate method,
From 0 ° to 50 °, it is incremented by Δθ / clock, and from 50 ° to 100 °, (θF−θ
B) / Increment by clock. From 100 ° to 250 °, increment by −Δθ / clock. From 250 ° to 300 °, (θB−θ)
F) / Increment by clock. From 300 ° to 350 °, increment by Δθ / clock, and then repeat in the same way to set the analog integrated waveform to zero.
It can pass through the cross points (180 °, 360 °...).

Here, θB from 50 ° to 100 °
Can be obtained from the output of the accumulator at the clock edge just after 90 °, but the value of θF cannot be obtained directly from the output of the accumulator.
However, since there is a relationship of θF = Δθ−θB, θF can be obtained from this relationship. Therefore, if the correction phase increment value from 50 ° to 100 ° is θC9, then θC9 = θF−θB = (Δθ−θB) −θB = Δθ−2θB.

As shown in FIG. 4A, the arithmetic circuit for calculating θC9 includes a subtractor 31 for calculating Δθ−θB and a subtractor 32 for subtracting θB from the output of the subtractor 31. It can be composed of two subtractors. Further, as shown in FIG.
It is also possible to use a single subtracter 33 for bit shifting to obtain 2θB and directly subtracting 2θB from Δθ. Similarly, from 250 ° to 300 °, the value of θB can be obtained from the output of the accumulator at the clock edge immediately after exceeding 270 °, but the value of θF cannot be obtained directly from the output of the accumulator. However, since there is a relationship of θF = Δθ−θB, θF can be obtained from this relationship. Therefore, if the correction phase increment value from 250 ° to 300 ° is θC27, then θC27 = θB−θF = θB− (Δθ−θB) = − (Δθ−2θB).

As shown in FIG. 4 (c), the arithmetic circuit for calculating θC27 includes a subtractor 34 for calculating Δθ−θB and a subtractor 35 for subtracting the output of the subtractor 34 from θB. It can be composed of two subtractors. Further, as shown in FIG.
It is also possible to use a single subtractor 36 for bit-shifting to obtain 2θB and to directly subtract 2θB from Δθ, and invert this by an inverter 37 to obtain it.

Next, a specific embodiment of a frequency signal generating circuit according to the present invention and an embodiment of a frequency signal generating method will be described with reference to FIG. That is, FIG.
Register 10 to which an adder 101 and a clock are added
Reference numeral 2 denotes an accumulator, and an adder 101
Is a periodic function corresponding to the phase increment value Δθ from the output of the register 102 by adding the phase increment value Δθ set in the phase increment value setting section 103 and the output of the register 102 in synchronization with the clock. Get.

The output of the register 102 is a +/-. DELTA..theta. Integration period detector 104 as a residual integration period detector, a .theta.C9 integration period detector 105 as a top integration period detector, and a .theta.C27 integration period as a bottom integration period detector. It is provided to the detection unit 106. +/− Δθ integration period detection unit 1
04 is + / + based on the output of the register 102 and the clock.
-Δθ integration period, ie, 0 ° → 50 °, 100 ° → 250 °, 30 of the periodic function output from the register 102
0 ° → 400 ° ... is detected. Further, the θC9 integration period detecting section 105 detects the θC9 integration period, that is, 50 ° → 100 °, based on the output of the register 102 and the clock. Further, the θC27 integration period detecting unit 106 determines the θC27 integration period based on the output of the register 102 and the clock.
That is, 250 ° → 300 °... Is detected.

The polarity detector 107 receives the output of the register 102, and detects the polarity inversion of the periodic function output from the register 102 based on the output of the register 102. The data θB detection unit 108 receives the output of the register 102, the output of the θC9 integration period detection unit 105, and the clock, and detects and stores θB for the θC9 integration period. Further, the data θB detection unit 109
And the output and clock of the θC27 integration period detecting unit 106 are received, and θB relating to the θC27 integration period is detected and stored.

The switch 110 is driven based on the output of the polarity detector 107, and selects the output of the data θB detector 108 during the θC9 integration period, and selects the output of the data θB detector 109 during the θC27 integration period. Switch. The output of the switch 110 is applied to the B input of the subtractor 112, while the A input of the subtractor 112 is applied to the phase increment value Δ set in the Δθ setting unit 103.
θ is added. Therefore, the subtractor 112 calculates Δθ−θ
The output of the subtracter 112 is applied to the A input of the subtractor 114 via the switch 113 while performing the operation of B. A switch 11 is connected to the B input of the subtractor 114.
3, the output of the switch 110, that is, θB is added. Here, the switch 113 is a double switch, and is driven based on the output of the polarity detection unit 107.
In the θC9 integration period, the output of the subtractor 112 is added to the A input of the subtractor 114, and θB is added to the subtractor 114.
In addition to the B input of FIG.
12 is added to the B input of the subtractor 114,
Switching is performed so that θB is added to the A input of the subtractor 114. That is, the subtractor 112 and the subtractor 114
During the C9 integration period, the same operation as that of the circuit shown in FIG. 4A is performed. Therefore, θC9 = Δθ−2θB is calculated. During the θC27 integration period, the same operation as the circuit shown in FIG. 4C is performed. Therefore, θC27 = − (Δθ−2θ
B) is calculated.

The output of the subtractor 114 is converted into an analog signal by a digital / analog converter 115 and is applied to an output on / off controller 116. A clock is applied to the output on / off control unit 116, and θC
9 integration period detection unit 105, θC27 integration period detection unit 10
6 and the output of the partial integration control unit 111 for inputting the clock, and the output of the partial integration control unit 111 outputs the output of the digital-analog conversion unit 115 in the θC9 integration period and the θC27 integration period, An analog signal corresponding to ± (Δθ−2θB) is output.

On the other hand, the phase increment value Δθ set in the Δθ setting unit 103 is
Converted into an analog signal corresponding to the phase increment value Δθ,
It is added to the state control unit 119.

The three-state control unit 119 receives the output of the +/- Δθ integration period detecting unit 104 and the clock, and outputs the clock during the detection period of the +/- Δθ integration period detecting unit 104, ie, the +/- Δθ integration period. The analog signal corresponding to the phase increment value Δθ added from the digital-to-analog converter 118 is given a sign corresponding to the +/− Δθ integration period, and is output as an analog signal corresponding to ± Δθ. The output ON / OFF control section 116 outputs the θC9 integration period and θ
± (Δθ−2θB) output during C27 integration period
Signal corresponding to, and three-state control unit 11
9 and the analog signal corresponding to ± Δθ output during the +/− Δθ integration period is supplied to the operational amplifier 121 and the capacitor 1 via the resistor 117 and the resistor 120, respectively.
22 is added to the integrating circuit.

Therefore, the integration circuit composed of the operational amplifier 121 and the capacitor 122 integrates the analog signal corresponding to + Δθ during the + Δθ integration period,
During the -Δθ integration period, the analog signal corresponding to -Δθ is integrated, and during the θC9 integration period, + (Δθ-2θ
The analog signal corresponding to B) is integrated, and the analog signal corresponding to-(Δθ−2θB) is integrated during the θC27 integration period. The output of this integration circuit has already been subjected to compensation partial integration in the top region and bottom region of the periodic signal waveform for each period serving as the reference frequency signal. may be output as a signal f _R, and + side of the periodic signal waveform by performing a beat removal - clipper equal the area of the side circuit (CLP) 123 (FIG. 2 (c), the
(D) and a low-pass filter (LPF) 124 that removes a harmonic component, and may be received by the comparator 125 as a clean sine wave with little jitter.

In the configuration shown in FIG. 1A, the portions of the subtractor 112 and the subtractor 114 are implemented by adopting the circuit schemes shown in FIGS. 4B and 4D.
It can be composed of two subtractors. This embodiment is shown in FIG. That is, the subtractor 1 shown in FIG.
12, the switch 113 and the subtractor 114 are composed of one subtractor 126, an inverter 127, and a switch 128.
Since the other configuration is the same as that shown in FIG. 1A, the same reference numerals are used for the common parts with FIG. 1A for convenience of explanation.

Here, the switch 128 switches so as to select the output of the subtractor 126 during the θC integration period and to select the output of the inverter 127 during the θC27 integration period. In this embodiment, the subtractor 126 and the inverter 127 operate in the same manner as the circuit shown in FIG.
During the seven integration periods, the operation is the same as that of the circuit shown in FIG.

FIG. 2 shows an example of a detailed circuit diagram of the above embodiment including a timing circuit. In this circuit, an adder 301 and a register 302 to which a clock is added constitute an accumulator, and the adder 301 has a phase increment Δθ set in a Δθ setting unit 303.
And the output of the register 302 are added in synchronization with the clock,
From the output of the register 302, a periodic function corresponding to the phase increment value Δθ is obtained.

Then, exclusive OR circuits 304 and 308 and an inverter 30 are used by using the upper two bits of the signal of the register 302, that is, MSB and MSB-1.
5,309,317, AND circuit 310, NOR circuit 31
2. OR circuits 318 and 319, D flip-flop 30
7, 313, 314, a timing corresponding to the +/- Δθ integration period is created, and at this timing, the digital / analog conversion section 320 with a sign is operated.
During the -Δθ integration period, ± Δθ output, that is, an analog signal corresponding to ± Δθ is formed.

Also, the upper two of the outputs of the register 302
Signals excluding bit signals, that is, MSB-2 to LSB
(Least significant bit), θB is detected, and
21. The arithmetic circuit 322 obtains ± (Δθ−2θB) from the θB stored in the register 321 and the phase increment value Δθ set in the Δθ setting unit 303.
This is added to the digital / analog conversion unit with sign 324 via the register 323, and the D flip-flop 315,
By switching the switches 325, 326, and 327 according to the output of the signal 316, θC9 in the θC9 integration period
An output, that is, an analog signal corresponding to + (Δθ−2θB) is formed, and an θC27 output, that is, an analog signal corresponding to − (Δθ−2θB) is formed during the θC27 integration period. ± Δθ output and θC9 output and θC
The 27 outputs are applied to an integrating circuit including an operational amplifier 334 and a capacitor 335 via resistors 331, 332, and 333, respectively.

As shown in FIG. 2C, the output of the integrating circuit is output to the clipper circuit 336 and the low-pass filter 33.
7. The noise component is removed via the comparator 338 or directly via the comparator 338, and the frequency signal f
Output as _R.

FIG. 3 is a timing chart showing signal waveforms at various parts of the circuit shown in FIG. Here, FIG. 3A shows a clock used in this embodiment, and FIG. 3B shows the most significant bit MS of the register 302.
FIG. 3C shows the signal of the first bit MSB-1 from the most significant bit of the register 302.

FIG. 3D shows the MSB and M of the register 302.
The output of the exclusive OR circuit 304 that takes an exclusive OR condition with the signal of SB-1. FIG. 3E shows the output of the exclusive OR circuit 304 and the non-inverted output of the D flip-flop 307 added to the D input. 7 shows the output of an exclusive OR circuit 308 that takes an exclusive OR condition with the output of the OR circuit 304. The output of the exclusive OR circuit 308 is applied to the clock input of the register 321 to control the timing at which the register 321 takes in θB.

FIG. 3F shows the output of the AND circuit 310 which takes the AND condition between the output of the exclusive OR circuit 304 and the signal obtained by inverting the output of the exclusive OR circuit 308 by the inverter 309, and FIG. Circuit 31 that takes a NOR condition between the output of the exclusive OR circuit 304 and the output of the exclusive OR circuit 308
2 shows the output.

FIG. 3H shows that the output of the AND circuit 310 is D
The non-inverted output of the D flip-flop 313 applied to the input and the output of the NOR circuit 312 take the output of the OR circuit 318 taking the OR condition of the signal obtained by inverting the non-inverted output of the D flip-flop 314 applied to the D input with the inverter 317. Show. The output of the OR circuit 318 is added to the signed digital / analog converter 320 as a sign bit, and the sign of the analog signal to be converted in the signed digital / analog converter 320 is determined.

FIG. 3 (i) shows the non-inverted output of the D flip-flop 313 in which the output of the AND circuit 310 is applied to the D input, and the non-inverted output of the D flip-flop 314 in which the output of the NOR circuit 312 is applied to the D input. 5 shows the output of the OR circuit 319 that takes the OR condition of FIG. The output of the OR circuit 319 is output from the digital / analog conversion unit 320 with a sign.
The signal is applied to a put enable terminal OE, and controls the operation timing of the digital / analog converter 320 with a sign.

FIG. 3 (j) shows the output of the D flip-flop 316 in which the output of the exclusive OR circuit 308 is added to the D input. The output of the D flip-flop 316 is the output of the signed digital / analog converter 324. The signal is applied to the enable terminal OE and to the switches 326 and 327 to control the operation timing of the digital-to-analog converter 324 and to control the switching of the switches 326 and 327.

FIG. 3K shows the output of the D flip-flop 315 in which the output of the inverter 305 is added to the D input. The output of the D flip-flop 315 is applied to the switch 325 and controls the switching of the switch 325. .

FIG. 6 shows a result obtained by computer simulation for one waveform in the first cycle of the frequency signal f _R generated in the above-described embodiment, and FIG. 7 shows the result in the 24th cycle. FIG. 8 shows the result obtained by computer simulation for one waveform of the above, and FIG. 8 shows the result of the computer simulation in a time-series expression. 6, 7,
As is clear from FIG. 8, the generated waveform has zero cross point 0.
It turns out that it passes through °, 180 °, and 360 °.

Incidentally, in the above-described embodiment, 5
From 0 ° to 100 °, integration is performed using the correction phase increment θC9, and from 250 ° to 300 °, the correction phase increment θ
Although the integration is performed using C27, as shown in FIG. 9, the correction phase increment value is calculated in a portion including 180 ° and 360 °, and the correction phase increment value may be integrated. Good. In this case, θC18 = θF−θB = (Δθ−θB) −θB = Δθ−2θB θC36 = θB−θF = θB− (Δθ−θB) = − (Δθ−2θB), and from 0 ° to 150 ° Until + Δθ is integrated, 15
From 0 ° to 200 °, integration is performed using the corrected phase increment θC18, from 200 ° to 350 °, −Δθ is integrated, and from 350 ° to 400 °, the corrected phase increment θC3 is integrated.
6 to be integrated. In this case, the accumulator is not completely cleared in the initial state, but is initialized to 90 °. The circuit configuration is, for example, the circuit shown in FIG.
May be directly applied to the D input of the D flip-flop 315 without passing through the inverter 305.

FIG. 10 shows one waveform of the frequency signal f _R generated by the above-described configuration, which is obtained by computer simulation. As is apparent from FIG. 10, the generated waveform passes through the zero cross points 90 ° and 270 ° and satisfies the predetermined condition.

As described above, in each of the above embodiments, the accumulating means for calculating the phase increment value from the setting section in synchronization with a predetermined clock is provided by the accumulator 101 and the register 10.
.Theta.C9, which is a top region integration period detection unit for the periodic signal waveform generated from the output of the accumulation means.
The integration period detecting unit 105, the θC27 integration period detecting unit 106 as a bottom region integration period detecting unit, and the +/− Δθ integration period detecting unit 104 as a residual integration period detecting unit constitute an integration period detecting unit for one cycle. doing.

The polarity detector 107, the data θB detectors 108 and 109, the switch 110, the partial integration controller 111, the subtractors 112 and 114, and the double switch 1
13, the subtractor 126, the buffer 127 and the double switch 1 which are replaced with the subtractor 112 and the subtractor 114.
A partial integral compensation value generating means is constituted by a switch 128 or the like which is replaced with the switch 13.

Further, output on / off control units 116 and 3
The state control section 119 constitutes signal switching means for selectively switching the analog signals from the first digital / analog conversion means 115 and the second digital / analog conversion means 119, and the operational amplifier 121 and the capacitor 122 integrate the signal switching means. Is configured.

[0062]

As described above, according to the present invention,
Based on the result of accumulating the phase increment value, which is a digital set value corresponding to the reference frequency signal given to the phase locked loop, a compensation portion is provided in the top region and the bottom region of the periodic signal waveform for each period serving as the reference frequency signal. Integration is performed, and the compensation is performed so that the compensated partial integral output and the integral waveform during the remaining period from the top region to the bottom region or from the bottom region to the top region of the periodic signal waveform pass through a true zero cross point. It is configured to switch and output the partial integration and the integration result during the above-mentioned remaining period, and obtain the reference frequency to the phase locked loop. Can be.

Further, since a sine LUT is not used for generating a reference frequency as in the prior art, an enormous capacity R
An OM is not required, and an arbitrary frequency can be generated with a simple configuration, which is effective for cost reduction.

Accordingly, the frequency is switched by driving the phase locked loop with high stability and high speed settling. For example, a digital cellular phone, a digital cordless phone, a digital cordless phone having a settling time of 1 ms or less is required. It is particularly effective for PBX applications.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic configuration of the present invention.

FIG. 2 is a detailed circuit diagram according to one embodiment of the present invention.

FIG. 3 is a diagram showing timings of signal waveforms of various parts in FIG. 2;

FIG. 4 is a diagram showing an arithmetic circuit for calculating θC9 and θC27 used in the present invention.

FIG. 5 is an explanatory waveform diagram showing integral compensation of a one-period signal waveform according to the present invention.

FIG. 6 is a diagram showing a simulation waveform in the first cycle when Δθ = 50 °.

FIG. 7 is a diagram showing a simulation waveform in the 24th cycle when Δθ = 50 °.

FIG. 8 is a diagram showing a simulation waveform expressed in time series when Δθ = 50 °.

FIG. 9 is an explanatory waveform diagram of a periodic signal waveform in a case where partial integration compensation is performed at 0 °, 180 °, and 360 ° clock portions.

FIG. 10 is a diagram showing a simulation waveform in the 24th cycle in the case of FIG. 9;

FIG. 11 is a block diagram showing a conventional frequency synthesizer using a phase locked loop.

FIG. 12 is a block diagram showing a conventional DDS drive type frequency synthesizer.

FIG. 13 is a block diagram showing details of a direct digital synthesizer in FIG. 10;

FIG. 14 is an explanatory diagram in which the accumulator portion of FIG. 11 is simplified to 4 bits.

FIG. 15 is a diagram illustrating a mechanism of accumulator frequency division.

FIG. 16 is a diagram showing a generated waveform based on a clock of the direct digital synthesizer in FIG. 10;

FIG. 17 is a diagram showing a clock shift based on a generated waveform.

FIG. 18 is a waveform chart in the case of integer frequency division.

FIG. 19 is a waveform chart in the case of decimal point division.

FIG. 20 is an MBS output waveform chart in the case of decimal point frequency division.

[Explanation of symbols]

 Reference Signs List 10 variable frequency source 20 PLL circuit 21 phase detection circuit 22 loop filter 23 VCO (voltage controlled oscillator) 24 fixed frequency divider 101 adder 102 register 103 Δθ setting unit 104 +/− Δθ integration period detection unit 105 θC9 integration period detection Unit 106 θC27 integration period detection unit 107 polarity detection unit 108, 109 data θB detection unit 110, 113 switch 112, 114, 126 subtractor 115, 118 digital / analog conversion unit 116 output on / off control unit 119 three-state control unit 121 Operational amplifier 122 Capacitor 123 Low-pass filter 124 High-pass filter 125 Comparator

 ────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-58-106901 (JP, A) JP-A-6-61743 (JP, A) JP-A-6-29745 (JP, A)

Claims (3)

(57) [Claims] 1. A phase for locking or following a reference frequency by receiving a reference frequency signal, comparing the phase with its own oscillation output waveform, and changing the oscillation output frequency in a direction to reduce the error. In a method for generating a reference frequency of a lock loop, a set phase increment value (Δθ) is accumulated for each clock,
Generating a period value of the reference frequency signal; and, based on the period value, a polarity inversion point (90 °, 270 °, 4 °).
..), And a second clock period other than the first clock period, and a phase difference between a terminal phase value and a polarity inversion point in the first clock period. calculating a first integral value (± (Δθ−2θB)) based on the phase increment value (Δθ) and the second integral value (± Δ
.theta.), and integrating the first integral during the first clock period and integrating the second integral during the second clock period. Method of generating reference frequency for partial integral switching. 2. An accumulator for accumulating a digital set value supplied from a phase increment value (Δθ) setting section in synchronization with a predetermined clock, and outputting a phase value, based on the phase value. , The first polarity inversion point (90 °, 45
0 °, 810 °,...), And a second polarity inversion point (27).
0%, 630 °,...), And a one-period component period detecting means including a bottom region integration period detecting unit for detecting a clock period including the remaining clock periods. A first compensation integral value (+ (Δθ−2θB)) is calculated based on the phase difference (θB) between the terminal phase value and the polarity inversion point in the top region integration period and the phase increment value (Δθ), The second compensation integral value (− (Δθ−2) based on the phase difference (θB) between the terminal phase value and the polarity reversal point during the bottom region integration period and the phase increment value (Δθ).
θB)), a first digital-to-analog conversion means for converting an output from the partial integration compensation value generating means into an analog signal, and an analog signal for converting the phase increment value (Δθ) into an analog signal. Convert to the second
And the output of the first digital-to-analog conversion means and the output of the second digital-to-analog conversion means are input to the first and second digital-to-analog conversion means. Signal switching means for outputting the output of the digital / analog conversion means and outputting the output of the second digital / analog conversion means during other periods; and integration means for integrating the analog signal inputted from the signal switching means. And a comparator to which an output of the integration means is input and outputs a rectangular wave. A reference frequency generation circuit for switching partial integration for a phase locked loop, comprising: 3. A connection line between the integration means and the comparator is provided so as to equalize the areas on the positive and negative sides of the periodic signal waveform.
A clipper circuit that limits the amplitude below the boundary level value between the remaining period region and the top region and the boundary level value between the remaining period region and the bottom region of the periodic signal waveform and removes the beat is interposed, and 3. The reference frequency generating circuit according to claim 2, further comprising a low-pass filter for removing harmonic components.