JPH10322164A - Digital filter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a digital filter in which dispenses with transfer of a first data memory and a second data memory, and a multiplicative step can be increased, and the precision of a filter can be improved, without damaging an arithmetic speed in a digital filter for thinning-out input data at a constant ratio. SOLUTION: Data are read from RAMs 63 and 64, in which input data 1 are written based on an address supplied from an address generator 51, and a value obtained by adding the data by an adder 30 is multiplied by a coefficient read from an ROM 71. The input data are divided into blocks constituted of N pieces of data and alternately stored in first and second memories. The addresses of the first and second data memories are calculated from the first and second numbers which indicate the block numbers of the block constituted of the N pieces of data, and the third number which indicates the location of data in the block.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a digital filter, and more particularly to a digital filter for thinning out input data at a constant rate and outputting the same.

[0002]

2. Description of the Related Art In recent years, A / D conversion technology for performing signal processing using a digital filter has become mainstream along with the high integration of digital circuits and the development of oversampling A / D conversion technology. Oversampling A / D
The converter performs A / D conversion at a sampling frequency higher than the final conversion frequency, performs low-pass filtering using a digital filter, reduces aliasing noise, and repeatedly thins out data. , And obtain the data of the final conversion frequency. This means, for example,
"Oversampling A / D Conversion Technology" Akira Yukawa, Nikkei BP, 1990, pp. 97-127.

As a digital filter for an oversampling A / D converter, a FIR (Finite Imp) is used.
ulse response) filter, IIR (in)
A fine impulse response (Finite Impulse Response) filter is used depending on the purpose. Among them, those where the mutual relationship of the phases of the input and output waveforms do not change,
That is, as a digital filter having no group delay distortion, there is a perfect linear phase FIR filter.

Next, a first conventional example of a perfect linear phase FIR filter having 2N (N is an integer) taps will be described with reference to a block diagram shown in FIG. A delay circuit 2 for sequentially delaying data 1, an adder 3, and adding coefficients a _{0 to} a _N-1 to the adder 3
And an accumulator 4.

[0005] The complete linear phase FI constructed as described above
The operation of the R filter will be described. Input data 1 at a certain time is represented by x (n), and data delayed by one sample by the delay circuit 2 is represented by x (n-1).
Similarly, the input data 1 is sequentially delayed by the delay circuit 2,
Delayed data x (n-1) to x (n-N + 1) to x
(N−2N + 1) and input data x (n) are input to the adder 3.

Two sets of data x (nk), x (n + k-
(2N-1)) (where k = 0 to N-1) are added by the adder 3, and then added to the multipliers 10 to 1 (N-
1) are multiplied by the coefficients a _{0 to} a _N−1, and all are added by the accumulator 4. Therefore, the output data y (n) is calculated by the following equation (1).

[0007]

Here, two sets of data x (nk), x
Since the coefficients multiplied by (n + k- (2N-1)) are equal to each other, the expression (1) can be modified as the following expression (2).

[0009]

An example of a digital filter obtained by improving the above-described perfect linear phase FIR filter is disclosed in Japanese Patent Laid-Open No. 61-6 / 1986.
0005. A second conventional example of a perfect linear phase FIR filter will be described with reference to the block diagram shown in FIG. 5 and the block diagram of FIG. 6 in which the number of taps is set to 4 and a data delay is configured using a shift register.
In FIG. 5, reference numeral 5 denotes an address generation circuit for generating addresses of the ROM 7 and the RAMs 61 and 62. Reference numeral 7 denotes a ROM for storing multiplication coefficients, reference numeral 3 denotes an adder, reference numeral 8 denotes a multiplier, and reference numeral 4 denotes a cumulative adder including the adder 3 and a register 9. Reference numerals 61 and 62 denote RAMs for data delay.

In FIG. 6, reference numeral 20 denotes a shift register for delaying one sample time; 31, 32, adders for adding data at symmetrical positions; 81, 82, multipliers for applying coefficients; It is a vessel.

Since the coefficients at the symmetrical positions are equal, the data at the symmetrical positions are added in advance by the adders 31 and 32, and the coefficients a ₁ ′ and a ₂ ′ are added to the data using multipliers 81 and 82, respectively. The result is multiplied by the accumulator 4 to perform filtering. A specific processing procedure will be described with reference to FIGS.
61 reads data x _n-1 from the read data x _n-4 from RAM62 same time, the data x _n-1 and the data x _n-4
Is multiplied by a coefficient a ₁ ′, and this value is stored in the accumulator 4.

Next, data _xn-2 is read from the RAM 61, and data _xn-3 is read from the RAM 62 at the same time.
After adding the data x _n−2 and the data x _{n−3, the result} is multiplied by a coefficient a ₂ ′, and this value is added to the previous cumulative addition value by the cumulative adder 4 to obtain one output sample value y (n−
Obtain 1).

Thereafter, the oldest data in the RAM 61 is written to the RAM 62 through 101 in FIG.
Is written with new data, and the same operation as when the previous output sample value was calculated is performed to obtain the next output sample value.

At this time, when the above-mentioned digital filter is a low-pass filter for thinning out the data used in the oversampling A / D converter, the amount of calculation can be reduced according to the thinning ratio. For example, assuming that the data is thinned out to 1/3, the above-described operation may be performed by calculating y (n + 2) next to the operation for obtaining y (n-1). In this case, time tn and time t (n +
In 1), only the transfer of data from the RAM 61 to the RAM 62 and the writing of input data need be performed.

[0016]

In the above-described conventional digital filter, two data obtained by multiplying the same coefficient by a multiplier are stored in the first digital filter.
In order to read data from the data memory and the second data memory, it is necessary to transfer data from the first data memory to the second data memory, and the data transfer period cannot be multiplied, so that the speed cannot be increased. There is.

In order to increase the speed, the conversion process must be performed within the time excluding the transfer time from the first data memory to the second data memory, and the number of taps of the digital filter is necessarily limited. There is a problem that is.

Therefore, an object of the present invention is to provide a high-accuracy and high-speed digital filter which eliminates the need for data transfer from the first data memory to the second data memory and increases the number of taps of the digital filter. It is in.

It is another object of the present invention to provide a digital filter which can easily generate addresses of the first data memory and the second data memory.

Still another object of the present invention is to provide a digital filter which simplifies an address configuration and has a high circuit delay with only one multiplication period.

[0021]

Therefore, a digital filter according to the present invention comprises first and second data memories for storing input data, a coefficient generator for generating coefficient values of the digital filter, and a first and a second data memory. An address generator for generating an address signal of the second data memory and the coefficient generator; an adder for adding each data stored in the first data memory and the second data memory; A multiplier for multiplying the output of the adder by the output of the coefficient generator; and a cumulative adder for cumulatively adding the multiplication result of the multiplier. The input data is 1 / N (N = 2, 3,
..), The address generator divides the input data into blocks of N data in the first and second data memories. The address signal is generated so as to alternately write to the address.

[0022]

Next, embodiments of the present invention will be described with reference to the drawings and tables.

FIG. 1 is a block diagram showing an embodiment of a digital filter according to the present invention. The digital filter according to the embodiment of the present invention includes RAMs 63 and 64 for delaying input data 1, an adder 30 for adding data stored in RAMs 63 and 64, and an RO for storing coefficients.
M71, data and ROM stored in the adder 30
A multiplier 8 for multiplying the coefficient stored in the memory 71; a cumulative adder 4 including an adder 3 and a register 9;
3 and 64 and an address generator 51 for supplying an address signal to the ROM 71.

Although not explicitly shown in FIG. 1, the digital filter according to the present embodiment is a perfect linear phase FIR low-pass filter having 48 taps, and the description will be made on the assumption that input data is thinned out to 1/3. That is, assuming that an input sampling frequency which is a frequency for sampling input data is Fs1 and an output sampling frequency which is a frequency for sampling output data is Fs2,
Fs1: Fs2 = 3: 1, and the input data is 1 / Fs
1 and the output data is output every 1 / Fs2.

Next, the basic operation of the digital filter according to the embodiment of the present invention will be described with reference to FIG.

The input data 1 is stored in the RAM 63 or RAM in accordance with the address signal supplied from the address generator 51.
64. Next, the data read from the RAM 63 and the RAM 64 are added by the adder 30. This addition data is read out together with a coefficient corresponding to the addition data stored in the ROM 71 based on the address signal supplied from the address generator 51, and is multiplied by the multiplier 8.

The output data of the multiplier 8 is accumulated by the adder 3 with the data held in the register 9 and is again held in the register 9. This is repeated, and after the filter operation is completed, the output data is output from the accumulator and the register 9 is reset.

Next, the operation of the digital filter according to the embodiment of the present invention shown in FIG. 1 will be described based on the transition table of the address signals of the RAMs 63 and 64 shown in Table 1.

[0029]

The numbers from 0 to 15 shown at the left end of Table 1 are RA
M63 and M64 represent 16 states of all data held. Addresses A63 and A64 of RAMs 63 and 64
Is A63 = a1 using the order a1, a2, and b, respectively.
+ 8b, A64 = a2 + 8b, and the order a
1 and a2 take values of 0 to 7, respectively, and the order b takes values of 0, 1 and 2, so that A63 and A64 take values of 0 to 23, respectively.

First, as shown in FIG. 2, the input data is divided into blocks composed of three continuous data corresponding to the thinning ratio, and the order a1, a2 represents this block number. The order b indicates the order in the block, and when combined with the order a1 or the order a2, the RAM 63, 6
4 shows how many samples of the data stored in the delay data correspond to the delay data.

For example, in state 0, the order b is 2 → 1 →
0, but RAM changes when b = 2 and a1 = 7
The address A63 of 63 is A63 = 7 + 8.2 = 23, and data x (n-44) is stored in this address as shown by the arrow in Table 1. Here, 44 indicates a tap number. That is, the numbers in the bold lines in Table 1 correspond to the RAMs 63 and 64 specified in the order a1, a2 and b.
Indicates which tap number data corresponds to the address. In the above case, the address A64 is stored in the RAM 64.
= 0 + 8.2 = 16, data x (n−3) is stored as indicated by the arrow in Table 1.

Next, while the order b holds 2, the order a1
Changes from 7 to 6, and the order a2 changes from 0 to 1
, The address A63 becomes A63 = 6 + 8.2 =
22, the address A64 changes to A64 = 1 + 8.2 = 17, and the data x (n-38) is stored in the address A63.
Data x (n-9) is stored in the address A64.

Further, while the order b holds 2, the order a
When 1 changes from 6 to 5, and the order a2 changes from 1 to 2, address A63 changes to A63 = 5 + 8.2 = 21, address A64 changes to A64 = 2 + 8.2 = 18, and data is stored in address A63. x (n-32) is the address A
64 stores data x (n-15).

Similarly, if the order a1 and a2 advance to 0 and 7 respectively while the order b holds 2, the address A63
Is A63 = 0 + 8.2 = 16, and address A64 is A6
3 = 7 + 8.2 · 2 = 23. At this time, the address A6
3, data x (n-2) is stored in the dress A63, and data x (n-45) is stored in the address A64.
When the order b changes from 2 to 1, the order a1 becomes 7 → 6 → 5
.. 0, and the order a2 changes as 0 → 1 → 2... 7 in conjunction with the change of the order a2. This operation is repeated until the order b becomes 0 and the orders a1 and a2 become 0 and 7, respectively, and the state 0 ends.

As described above, during state 0, RA
Three pieces of data are input to M63, and the data is written to the addresses that specify the order b in the order of 2 → 1 → 0 in the order of input data. In the RAM 64, writing is not performed in the state 0.

The addresses of the RAMs 63 and 64 are in the order shown in the order a1, a2, b in Table 1, that is, b: 2 → 1 →
0, a1: 7 → 6 → 5... 0 (a2: 0 → 1 → 2.
・ Readout in the order of 7).

From the above results, the following Table 2 at the time of state 0
, And the output data is output from the accumulator 4 shown in FIG.

[0039]

As can be seen from Table 2, since the change in the address increases or decreases by one, the input data can be taken in at equal intervals. The data to be read last is b
= 0, a1 = 0. At this time, as can be seen from Table 1, data x (n) is input to the input terminal (tap number 0). That is, the last data x (n) is input,
There is a feature that a filter operation result can be obtained immediately.

For the above-mentioned reasons, the circuit delay is reduced and a high-speed digital filter can be realized.

Next, an address for reading the ROM 71 storing the coefficients will be described.

As can be seen from Table 1, in state 0, b
The tap number of = 0, a1 = 0 is 0. If a1 changes from 0 → 1... 5 → 6 → 7 while the order b remains 0, the tap numbers change as tap number 1 in Table 3. Here, data x stored in tap number 1
(N-tap number 1) and data x (n-tap number 2) stored in tap number 2 are multiplied by the same coefficient. However, tap number 2 = 47−tap number 1.

[0044]

Therefore, the address of the coefficient stored in the ROM 71 is such that the tap number 1 is 0 →... → 17 → 11
→ 5 → 1 → ・ ・ ・ → 10 → 4 → 2 → ・ ・ ・ → 9 → 3 In conjunction with the change, the coefficient specified by the coefficient address and the data x stored in each tap (N-
k), and accumulates by the accumulator 4 shown in FIG. 1 to obtain output data in the state 0 in which the input data is thinned to 1/3.

Next, the operation in the state 1 shown in Table 1 will be described.

The operation performed in the state 1 is performed to obtain the output data in the state 1 which is the next state of the output data in the state 0. The difference from the operation in the state 0 is that the RAM 63,
The second difference is that the write destination of the input data is RAM 63 in state 0, whereas the write destination of the input data is RAM 64 in state 1. Other actions,
That is, the operations of the ROM 71, the adder 30, the multiplier 8, and the accumulator 4 are the same as those in the state 0.

As can be seen from Table 1, R in state 1
Table 4 shows address transitions of the AMs 63 and 64 and writing of input signals.

[0049]

As described above, the operation of each address in Table 4 is performed by R
The output data from the accumulator 4 in the state 1 is obtained by repeating 24 times from each address A63 = 0, A64 = 6 to A63 = 23, A64 = 23 of the AM 63, 64.

The same processing is repeated up to state 15 as shown in Table 1, and 16 output data are obtained for 48 input data. That is, when the state is an even number, the RAM 63
Input data to the RAM 6 when the state is odd.
4. Write the input data into 4.

After proceeding to state 15, the state returns to state 0 again, and the same operation as described above is repeated, thereby performing a low-pass filter operation on continuous input data.
Thus, continuous output data thinned by 3 can be obtained.

In this embodiment, the case of thinning out to 1/3 has been described. However, the present invention relates to 1 / M (M = 2,
3,...) Can be applied to all filters thinned out, and of course, it can also be applied to a half band filter thinned out by ２.

Next, the address generator 51 constituting the digital filter of the present invention will be described with reference to the block diagram shown in FIG.

The address generator 51 includes a 3-bit up counter 101 for increasing the count value by one at a clock 1, a 3-bit down counter 102 for decreasing a count value by one at a clock 2, and a two-to-one switch 103. , 104, an order b generating circuit 200 for generating the values 0, 1, 2 of the order b, and R from the orders a1, a2, b.
The addresses of AM63 and 64 are generated, and R is output from the output terminal O1.
The address A63 of the AM63 is transferred from the output terminal O2 to the RAM6.
Address operation circuit 300 that outputs address A64 of address 4
And

Next, the operation of the address generator 51 will be described.

In state 0 of Table 1, the 2-to-1 switch 1
03 is connected to the down counter 102, and the output terminal
The output terminal of the switch 104 is connected to the up counter 101. The order b generating circuit 200 is
While outputting 2 to 0, the up counter 101 outputs the value of the order a2 from 0 to 7 to the address arithmetic circuit 300 via the switch 104, and the down counter 102
Outputs the value of the order a1 from 7 to 0 to the address arithmetic circuit 300 via the switch 103.

The address operation circuit 300 operates in the order a1a
From the values of 2 and b, the address A63 of the RAM 63 = a1 +
8 · b and the address A64 of the RAM 64 = a2 + 8 ·
The value of b is calculated and output to output terminals O1 and O2, respectively. When the order b is 1, 0, the order a generating circuit performs the same operation and outputs the order a1, a2 shown in Table 1 to the address arithmetic circuit 300.

On the other hand, when the state shown in Table 1 is an odd number, the output terminal of the switch 103 is connected to the up counter 101, and the output terminal of the switch 104 is connected to the down counter 102, so that the order a1 and the order a2 are in descending order. The orders a1 and a2 shown in Table 1 can be generated.

As can be seen from Table 1, the order a1, a
The initial value of 2 differs depending on each state (0 to 15). However, when the state of the up counter 101 is switched from an odd number to an even number, the clock 1 is not supplied to prevent the count up for one time, and the state of the down counter 102 is not changed. When is switched from an even number to an odd number, the initial value of the order a1, a2 can be changed by supplying an extra clock 2 to count down one more time.

As a method of changing the initial values of the up counter 101 and the down counter 102, the up counter 101 and the down counter 102 are configured so that the initial value is set according to each state (0 to 15). May be. Further, in FIG.
Although described as a one-to-one switch, any selection means such as a multiplexer and a selector can be used.

[0062]

As described above, the digital filter according to the present invention does not need to transfer data between the two RAMs, so that it is not necessary to secure the time for the data transfer and the filter can be executed without lowering the operation speed. The number of taps for calculation can be increased. Except for the operation of the RAM address, there are many repetitive operations in a short cycle, and control of each circuit block is easy. Further, since the address simply changes in ascending order or descending order, it is possible to easily generate the RAM address.

Further, despite the simplification of the address configuration, the circuit delay is one multiplication, so that not only the circuit scale can be minimized, but also the operation speed of the digital filter can be increased. .

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a digital filter according to the present invention.

FIG. 2 is an explanatory diagram showing a structure of input data of the digital filter shown in FIG.

FIG. 3 is a block diagram showing an address generator constituting the digital filter of the present invention.

FIG. 4 is a block diagram showing a first conventional example of a perfect linear phase FIR filter.

FIG. 5 is a block diagram showing a second conventional example of a perfect linear phase FIR filter.

6 is a block diagram showing a data delay using a shift register in the conventional perfect linear phase FIR filter shown in FIG. 5;

[Explanation of symbols]

 Reference Signs List 1 input data 2 delay circuit 3, 30, 31, 32 adder 4 cumulative adder 5, 51 address generator 61, 62, 63, 64 RAM 7, 71 ROM 8, 81, 82, 10 to 10 (N-1 ) Multiplier 9,20 Register 100 Order a generator 101 Up counter 102 Down counter 103,104 Switch 200 Order b generator 300 Address operation circuit

Claims (7)

[Claims] A first data memory for storing input data; a coefficient generator for generating a coefficient value of a digital filter; an address of the first and second data memories and an address of the coefficient generator An address generator for generating a signal; an adder for adding each data stored in the first data memory and the second data memory; and an output of the adder and an output of the coefficient generator. A digital filter, comprising: a multiplier for multiplying; and a cumulative adder for cumulatively adding the multiplication result of the multiplier, wherein the digital filter thins out input data to 1 / N (N = 2, 3,...). Transmits the address signal to the first and second data memories such that input data is divided into blocks of N data and written alternately to the first and second data memories. A digital filter characterized by generating. 2. A block number representing an order of the blocks is determined by a first number and a second number.
And the address signal of the second data memory is generated by the address generator based on the first and second numbers and a third number representing the order of data in the block. The digital filter according to claim 1, wherein 3. The address signal of the first data memory is generated by the first number + (2N) × (the third number), and the address signal of the second data memory is , The second number + (2 N) × (the third number
3. The digital filter according to claim 2, wherein the digital filter is generated by the following. 4. The address generator includes a sequence 1 generation circuit that generates the first and second numbers, and a sequence 2 generation circuit that generates the third number, wherein the sequence 1 generation circuit is , A first input terminal connected to an output terminal of the up counter, and an output terminal of the first address calculation circuit for generating an address signal of the first and second data memories.
A first selecting means connected to the input terminal of the down counter; a second input terminal connected to the output terminal of the down counter; and an output terminal connected to the second input terminal of the address arithmetic circuit.
And an output terminal of the up-counter is connected to a third input terminal of the address operation circuit, and an output terminal of the up-counter is connected to a second input terminal of the second selection device. And the output terminal of the down counter is connected to a second terminal of the first selecting means.
A signal input to the first input terminal of each of the selection means or the second input terminal of each of the selection means each time the operation of the up counter or the down counter makes one cycle. 3. The digital filter according to claim 2, wherein the output is alternately switched to an output terminal of the first selection unit and an output terminal of the second selection unit. 5. The digital filter according to claim 4, wherein a clock input to said up counter is temporarily stopped to change an initial value of said up counter. 6. The digital filter according to claim 4, wherein an extra clock supplied to said down counter is temporarily supplied to change an initial value of said down counter. 7. The up counter and the down counter each have an initial value determined by the first and second numbers and the third number, and by the first and second numbers and the third number. 5. The digital filter according to claim 4, wherein: