JPH1155076A - Sampling frequency converting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accelerate operation without expanding the scale of a hardware. SOLUTION: A FIFO 20 stores inputted data Din according to a write address supplied from a read/write counter 21 and outputs the stored data according to a read address. An O/S (over sampling) coefficient designation/interpolation ratio generation part 23 calculates COE A and COE B (actually only the COE A as the set of coefficients for finding two over sampling points A and B required for finding the value of an interpolating point) for over sampling and linear interpolation, and also calculates an interpolation ratio while considering over sampling. According to the said coefficient set COE A and the interpolation ratio considering the over sampling, an 8-times over sampling/linear interpolating part 24 converts the sampling frequency of input data Din through linear interpolation and convolving operation without two producers, i.e., over sampling and linear interpolation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a sampling frequency converter for converting input data captured at a predetermined sampling frequency to a different sampling frequency and outputting the converted data.

[0002]

2. Description of the Related Art Conventionally, there has been known a sampling frequency converter for converting input data fetched at a predetermined sampling frequency into a different sampling frequency and outputting the converted data. Typical sampling frequency conversion methods include:
(1) A method of writing input data to a FIFO at a predetermined sampling frequency and reading the input data at a desired sampling frequency different from that at the time of writing, (2) The temporal relationship between a sampling point before conversion and a sampling point after conversion. A method of obtaining new data at a sampling point after conversion based on input data by linear interpolation calculation (described in Japanese Utility Model Laid-Open No. 6-54323), and the like.

[0003] The method (1) described above uses a FIF to determine the difference between the sampling frequency before conversion and the sampling frequency after conversion.
Since it is a method of absorbing by O, the same data is repeatedly read or data is skipped and read, and there is a problem that a waveform is distorted. In addition, the above (2)
However, the method of (1) merely performs a simple linear interpolation operation, and thus has a problem that the interpolation accuracy is too coarse.

[0004] As a development of improving the interpolation accuracy of the above method (2), a method of combining oversampling and linear interpolation as shown in FIG. 14 can be considered. In the method using this oversampling + linear interpolation, the data of the new sampling point X is calculated by the linear interpolation as shown in FIG. The data A and B of the oversampling points adjacent to each other across the sampling point X are used. Thereby, highly accurate interpolation is realized.

FIG. 15 schematically shows the technique of oversampling and linear interpolation. The upper part shows a configuration for performing an eight-times oversampling operation based on four sampling data, and the lower part shows a configuration for performing a linear interpolation operation based on two oversampling values calculated in the upper part. In the upper part, D1,
D2, D3, and D4 are one-sample delay units, respectively.
The input data is transferred to the subsequent stage according to a sampling clock (44.1 kHz in this example). Coefficient Cij (i = 1
４4, j = 0７7) represents a coefficient added (multiplied) to the data of the delay part Di, and the suffix j is
This represents a coefficient for calculating the value of the j-th oversampling point. That is, the data of the j-th oversampling point is calculated by the four coefficients having the same value of j. In addition, data of eight oversampling points is calculated by using a total of eight sets of coefficients with four coefficients having the same j as one set. Based on the calculated data of the two oversampling points, data at an arbitrary position between the two oversampling points is calculated by a linear interpolation operation in the lower linear interpolation part.
As described above, by performing the calculation of the two oversampling values and the linear interpolation operation at a cycle corresponding to a new sampling frequency (48 kHz in this example), highly accurate sampling frequency conversion can be performed.

[0006]

In the above-mentioned conventional sampling frequency converter, a high-precision operation is required for oversampling, and the oversampling is performed to calculate an interpolation value X between two points. Two calculations are required to calculate the values A and B. Further, linear interpolation requires hardware for calculation. As described above, in the conventional sampling frequency conversion device, there is a problem that it takes a long time to perform the calculation, the hardware becomes large-scale, and the cost increases.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a sampling frequency conversion device capable of speeding up the operation without increasing the scale of hardware.

[0008]

In order to solve the above-mentioned problems, according to the present invention, a first interpolation ratio for obtaining an interpolation point between input data inputted by a first clock is provided. , A coefficient generation means for generating a pair of coefficient sets for obtaining an oversampling point based on the first interpolation ratio, and a first interpolation ratio based on the first interpolation ratio. A second interpolation ratio generating means for generating a second interpolation ratio of the interpolation points between the over-sampling points, and the coefficient based on the second interpolation ratio generated by the second interpolation ratio generating means. Interpolating means for linearly interpolating between a pair of coefficient sets generated by the generating means; and a convolution operation between the value of the interpolation point linearly interpolated by the interpolating means and the input data in accordance with a second clock, and output data age Characterized by comprising a calculating means for outputting.

Further, according to the invention described in claim 2, according to claim 1,
In the sampling frequency conversion device described above, the coefficient generation means includes a storage means for storing a plurality of pairs of coefficient sets corresponding to the first interpolation ratio.

[0010] According to the third aspect of the present invention, the first aspect is provided.
In the sampling frequency conversion device described in the first aspect, the coefficient generation unit stores a coefficient for calculating an even-numbered oversampling point in the pair of coefficient sets.
Storage means, and a second storage means for storing a coefficient for calculating an odd-numbered oversampling point in the pair of coefficient sets, based on the first interpolation ratio,
An even coefficient stored in the first storage means and an odd coefficient stored in the second storage means are read out in pairs.

Further, according to the invention described in claim 4, according to claim 1,
In the sampling frequency conversion device described above, the coefficient generation means includes a storage means for storing half of the pair of coefficient sets.

Further, according to the invention described in claim 5, according to claim 1,
In the sampling frequency conversion apparatus described above, the coefficient generation means includes a storage means for compressing the pair of coefficient sets by a power of two and storing the compressed coefficient set.

According to the present invention, the first interpolation ratio generating means generates the first interpolation ratio for finding the interpolation point between the input data input at the first clock, and Based on the ratio, the coefficient generation means generates a pair of coefficient sets for obtaining the oversampling points, and the second interpolation ratio generation means calculates the second interpolation ratio of the interpolation points between the oversampling points. Generate. Then, the interpolation means linearly interpolates between the pair of coefficient sets on the basis of the second interpolation ratio, and then calculates the interpolation points of the interpolation points linearly interpolated by the interpolation means in accordance with the second clock in accordance with the second clock. Since the value and the input data are convolved and output as output data, the number of calculations can be reduced without increasing the scale of hardware, so that the calculation required for the sampling frequency conversion is speeded up. It becomes possible.

[0014]

Embodiments of the present invention will now be described with reference to the drawings.

A. Configuration of Embodiment A-1. Basic Configuration of Embodiment FIG. 1 is a block diagram showing a basic configuration of a sampling frequency conversion device according to an embodiment of the present invention. In the figure, a FIFO 20 is constituted by a dual port RAM (random access memory), stores input data Din in accordance with a write address supplied from a read / write counter 21 described later, and stores in accordance with a read address. Is output to the eight-times oversampling / linear interpolation unit 24.

The read / write counter 21 generates a write timing and a write address according to the write timing CKin (44.1 kHz), and
The read timing and the read address are generated and supplied to the FIFO 20 in accordance with a clock CO supplied from the PLL 22 described later. Further, the read / write counter 21 has an up-down which is counted up by CKin and down-counted by CO, detects the amount of data in the FIFO 20, and supplies it to the PLL 22.

The PLL 22 is composed of a full adder, a latch circuit and the like, and receives an externally input clock CKout.
A read timing CO is generated according to the data amount ΔS according to 48 kHz and supplied to the read / write counter 21. Further, as shown in FIG. 2, the PLL 22 calculates an interpolation ratio Δt for obtaining an interpolation value (×) between the input data Din (○) and supplies the interpolation ratio Δt to the O / S coefficient designation / interpolation ratio generation unit 23. I do. Note that the interpolation ratio Δt is a value that does not consider oversampling.

FIG. 3 is a block diagram showing an example of the configuration of the PLL 22. In the figure, the conversion unit 22a
The non-linear conversion is performed on the current data amount ΔS which is the counter value of the read / write counter 21 to obtain the data G
ain (△ S) is output, and the converted data Ga
in (△ S) is supplied to the full adder 22c. Here, FIG.
Is a table showing conversion characteristics of the conversion unit 22a. The full adder 22c adds the data Gain (ＧS) and an output of a later-described selection circuit 22b. If the value supplied from the selection circuit 22b is y (n), y (n)
+1) = y (n) + Gain (△ S), and y
(N + 1) is output.

The selection circuit 22b gives the above-mentioned y (n) to the full adder 22c.
(0), and thereafter, the output y (n) of the latch circuit 22d is selected. Here, the initial value y (0) converts 44.1 kHz to 48 kHz. In this embodiment, y (0) =
It is set to 4096 × (44.1 / 48). It is to be noted that this initial value is provided for the purpose of shortening the time until the operation becomes stable, and is not essential. Full adder 22
c gives y (n + 1) to the latch circuit 22d according to the above equation. The latch circuit 22d includes a full adder 22c.
The clock CKout (48 k
Hz), and is supplied to the selection circuit 22b (feedback) and supplied to the full adder 22e.

The full adder 22e is connected to the latch circuit 22d.
Is added to a value supplied (feedback) from a latch circuit 22f described later, and the addition result is supplied to the latch circuit 22f and a carrier is supplied to the above-described read / write counter 21 as a read timing CO. I do. The latch circuit 22e outputs the addition result to a clock CKout (48 kHz) externally input.
And supplies it to the full adder 22e, and supplies it to an O / S (oversampling) coefficient designation / interpolation ratio generation unit 23 to be described later as an interpolation ratio Δt.

O / S (oversampling) coefficient designation /
An interpolation ratio generating unit 23 is a coefficient set for obtaining oversampling points A and B necessary for obtaining values of interpolation points (×) shown in FIG. COEA and COEB (actually, only COEA) are calculated based on the interpolation ratio Δt, and an interpolation ratio a in consideration of oversampling is calculated and supplied to the 8 × oversampling / linear interpolation unit 24.

The coefficient sets COEA and COEB are determined by the following equations. COEA = Int (△ t / 512) COEB = COEA + 1 where Int (x) is an operation for setting the decimal part to “0”. The coefficient set COEA, COEB is 0 ≦ COEA,
COEB ≦ 7. Further, the interpolation ratio a between the oversampling points A and B is a = Mod 512 (Δt) / 5
12 can be obtained. In addition, Mod512 (x) is
This is an operation for obtaining a remainder when x is divided by 512.

Next, the eight-times oversampling / linear interpolation unit 24 performs oversampling → in accordance with the coefficient set COEA and the interpolation ratio a in consideration of the oversampling.
Without going through the two steps of linear interpolation, the input data Din
Is converted and output as data Dout. Here, oversampling according to the present invention +
The linear interpolation is represented by the following equation. X = a (D1 * C1i + D2 * C2i + D3 * C3i + D4 * C4
i) + b (D1 * C1 (i + 1) + D2 * C2 (i + 1) + D3 * C3 (i +
1) + D4 * C4 (i + 1)) Therefore, X = D1 (aC1i + bC1 (i + 1)) + D2 (aC2i + bC2)
(i + 1)) + D3 (aC3i + bC3 (i + 1)) + D4 (aC4i +
bC4 (i + 1)) In the above equation, the values in parentheses correspond to linear interpolation between adjacent coefficients. Therefore, by calculating the value in the parentheses and directly multiplying the data, the sampling frequency can be converted with the same accuracy without performing the above-described two procedures.

A-2.8 Configuration of 2.8 × Oversampling / Linear Interpolation Unit FIG. 6 is a block diagram showing an example of the configuration of the 8 × oversampling / linear interpolation unit 24. In the figure, the 8 times oversampling / linear interpolation unit 24
The right half of the figure is a coefficient interpolator for linearly interpolating between coefficients according to the above principle, and the left half of the figure is a convolution unit.

The coefficient interpolation unit includes an adder 30, a ROM read control unit 31, a coefficient ROM 32, a full adder 33, and a multiplier 34.
And a full adder 35. Adder 30
Calculates COEB by adding "1" to a coefficient COEA specifying a coefficient set. ROM read control unit 3
1 reads a coefficient set from the coefficient ROM 32 according to COEA and COEB designating the coefficient set. At this time, ROM
The read control unit 21 supplies a coefficient Cij for COEA to one input terminal of the adder 33, and a coefficient Ci for COEB.
(j + 1) is added to the other input terminal (-) of the adder 33 and the adder 35.
Is controlled to be supplied to one input terminal (+). The coefficient ROM 32 stores coefficients Cij (i = 1 to 4, j = 0 to 7) required for oversampling, as shown in FIG. The sets Cij and Ci (j + 1) are output to the above-described units. As shown in FIG. 5, for example, as shown in FIG. 5, when COEA is (a) to (d), COEB specifies a set of coefficients as (a) to (d). It has become.

Next, the full adder 33 calculates Cij-Ci (j + 1).
Is calculated and supplied to the multiplier 34. The multiplier 34 multiplies the Cij-Ci (j + 1) by the interpolation ratio a, and calculates a (Cij-Ci (j
+1)) is calculated and supplied to the full adder 35. Full adder 3
5 calculates Ci (j + 1) + {a (Cij−Ci (j + 1))},
It is supplied to a multiplier 36. The above-described calculation is sequentially performed at a first timing (i = 1), a second timing (i = 2), a third timing (i = 3), and a fourth timing (i = 4).

Next, the convolution operation section comprises a multiplier 36, a full adder 37, a register 38 and a register 39. The multiplier 36 multiplies Ci (j + 1) + {a (Cij−Ci (j + 1))}, which is the operation result of the full adder 35, by the input data Di (i = 1 to 4), It is supplied to one input terminal of the full adder 37. The full adder 37 calculates the above (Ci (j + 1)
+ {A (Cij−Ci (j + 1))}) · Di and a value supplied from a register 38 described later, and the result of the addition is supplied to the register 38. The register 38 holds the result of the addition, supplies the result to one input terminal of the full adder 37, and supplies the result to the register 39. Therefore, the multiplier 3
6, the full adder 37, and the register 38, the (Ci (j + 1) +) supplied at the above-described first to fourth timings.
{a (Cij−Ci (j + 1))}) · Di is accumulated (convolution operation). The register 39 takes in data supplied from the register 38 in accordance with a clock (48 kHz) externally input, and finally outputs the data.

B. Next, an operation according to the above-described embodiment will be described.
The input data Din is supplied to the FIFO 20 according to the write address supplied from the read / write counter 21.
Is stored. Data Din stored in the FIFO 20
Is read out according to the read address supplied from the read / write counter 21 and supplied to the 8 × oversampling / linear interpolation unit 24. At this time, FI
The read timing of the FO 20 is determined by the read / write counter 21 and the PLL 22 by the FIFO 20.
Is controlled based on the data amount so that the data amount becomes an appropriate value.

Further, the PLL 22 calculates an interpolation ratio Δt for obtaining an interpolation value (×) between the input data Din (○) according to the data amount according to an externally input clock CKout (48 kHz). It is supplied to the S coefficient designation / interpolation ratio generation unit 23. Next, in the O / S coefficient designation / interpolation ratio generation unit 23, the oversampling point A required when the value of the interpolation point (x) shown in FIG. , B, a coefficient set Cij, a COEA for obtaining Ci (j + 1) and an interpolation ratio a in consideration of oversampling are obtained by an interpolation ratio Δt.
Is calculated based on

Next, the 8 × oversampling / linear interpolating unit 24 sets a · C1j at the first timing (i = 1).
+ (1-a) · C1 (j + 1), second timing (i = 2)
Then, a · C2j + (1-a) · C2 (j + 1), at the third timing (i = 3), a · C3j + (1-a) · C3 (j + 1), and at the fourth timing ( i = 4), a · C4j + (1-a) ·
C4 (j + 1) is calculated, and the data Di (i = 1 to 1)
4) is convolved with ｛a · C1j + (1-a) ·
C1 (j + 1)｝ · D1 + ｛a · C2j + (1-a) · C2 (j +
1)｝ ・ D2 + {a ・ C3j + (1-a) ・ C3 (j + 1)} ・ D3
+ {A.C4j + (1-a) .C4 (j + 1)}. D4 is calculated. This equation is equivalent to obtaining the interpolation value X by the conventional configuration shown in FIG.

In the result of the above-described convolution operation, the value in brackets of each term corresponds to linear interpolation between adjacent coefficients. By directly multiplying this value by the data Di, the interpolation value X can be obtained with the same precision without performing the two steps of oversampling and linear interpolation.
In other words, in the related art, a convolution operation for obtaining the eight-times oversampling value A, a convolution operation for obtaining the eight-times oversampling value B, and an operation for linear interpolation are required. In contrast, in the embodiment described above,
An operation for coefficient linear interpolation or a convolution operation may be used.
Further, depending on the interpolation accuracy, sufficient accuracy can be obtained even if the multiplier 34 for coefficient interpolation is smaller than the multiplier 36 for convolution operation.

C. First Modified Example Next, a first modified example of the present invention will be described. In the first modification, the coefficient Cij stored in the coefficient ROM 32 is defined as a coefficient for calculating an odd-numbered oversampling point (hereinafter simply referred to as an odd coefficient) and a coefficient for calculating an even-numbered oversampling point (hereinafter simply referred to as an even numbered coefficient). (Referred to as a coefficient) and storing them separately to speed up the calculation. Here, FIG. 8 is a block diagram replacing the ROM read control unit 31 and the coefficient ROM 32 shown in FIG. Other configurations are the same as those in FIG. 6, and illustration and description are omitted. In the figure, an adder 41
Calculates COEB by adding “1” to COEA specifying the coefficient set, and selects the selector circuits 43 and 4 described later.
6 The even / odd discriminating unit 42 outputs a selection signal for determining which of the even coefficient and the odd coefficient to output to the selection circuits 43 and 46 based on the COEA.
The signals are supplied to the selection circuits 49 and 50.

The selection circuit 43 operates according to the above selection signal.
If the even number is "0", COEA is supplied to the read control unit 44. If the odd number is "1", COEB is supplied to the read control unit 4.
4 The read control unit 44 specifies C
According to one of OEA and COEB, the coefficients are read from the coefficient ROM 45 storing only the even coefficients. Coefficient RO
As shown in FIG. 9, among the coefficients Cij (i = 1 to 4, j = 0 to 7) required for oversampling, M45 calculates coefficients (C10, C12, C14, ..., C46)
The coefficients specified by the read control unit 44 are supplied to the selection circuits 49 and 50.

Next, according to the selection signal, if the even number is “0”, the selection circuit 46 outputs COEB to the read control unit 4.
7 and, if the odd number is “1”, COEA is supplied to the read control unit 47. The read control unit 47 reads coefficients from a coefficient ROM 48 storing only odd coefficients according to either COEA or COEB specifying a coefficient set. As shown in FIG. 9, the coefficient ROM 48 stores coefficients Cij (i = 1 to 4, j = 0 to 7) required for oversampling.
Among them, the coefficients (C11, C13, C15,..., C47) for calculating the odd-numbered oversampling points are stored, and the coefficients specified by the read control unit 47 are supplied to the selection circuits 49 and 50. .

The selection circuit 49 operates according to the above selection signal.
In the case of an even number "0", the even number coefficient from the coefficient ROM 45 is output to the subsequent circuit, and in the case of an odd number "1", the coefficient R
The odd coefficient from the OM 48 is output to a subsequent circuit. According to the selection signal, the selection circuit 50 outputs the odd coefficient from the coefficient ROM 48 to the subsequent circuit when the even number is “0”, and outputs the coefficient ROM when the odd number is “1”.
The even-number coefficient from 45 is output to the subsequent circuit.

In the configuration described above, the eight-time oversampling / linear interpolation unit 24 sets the first timing (i =
1) At the second timing (i = 2), the third timing, and the fourth timing (i = 4), the coefficient set Ci
Since the access speed at the time of reading j and Ci (j + 1) can be increased, the operation can be speeded up.

D. Second Modification Next, a second modification of the present invention will be described. In the second modification, by storing only half of the coefficient Cij stored in the coefficient ROM 32, the storage capacity of the coefficient ROM is reduced and the calculation is speeded up. Here, FIG. 10A is a block diagram illustrating the concept of the calculation unit according to the above-described embodiment, and FIG.
It is a block diagram which shows the concept of the calculation part by a modification. In the above-described embodiment, as shown in FIG. 10A, the output (D1, D2, D3, D4) of each delay circuit is multiplied by a multiplier M
1, M2, M3, and M4 are multiplied by coefficients, and each is added by an adder AD and output. In the second modification, the symmetry of the coefficients, that is, M1 = M4, M2
= M, and as shown in FIG.
1, the data D2 and the data D3 are added, and the adder AD2 adds the data D1 and the data D4.
The multipliers M5 and M6 multiply the coefficients, and the adders AD3 add each to output. Therefore, in the second modification, since only the multipliers M5 and M6 need to multiply the coefficients, only half of the coefficient ROM needs to be stored. As a result, the storage capacity of the coefficient ROM can be reduced, and the calculation can be speeded up.

E. Third Modification Next, a third modification of the embodiment according to the present invention will be described. In the third embodiment, the coefficients stored in the coefficient ROM are "compressed" so that the limited storage capacity is used effectively. Specifically, the coefficient values used in the linear interpolation are subjected to power-of-two compression as shown in FIG.
To memorize it. The coefficients are decompressed as a result by performing shift control in an actual convolution operation.

FIG. 12 is a block diagram showing the configuration of the coefficient linear interpolation unit of the sampling frequency conversion device according to the third modification. In the figure, the coefficient ROM 60a
Along with information on the shift, even coefficients (C10, C12, C14,..., C46) among coefficients Cij (i = 1 to 4, j = 0 to 7) required for oversampling are stored. The coefficient ROM 60b stores the coefficient C required for oversampling together with information on the shift.
ij (i = 1 to 4, j = 0 to 7), odd coefficient (C1
1, C13, C15,..., C47) are stored. The shift control unit 61 controls the shift control signal C1 according to the shift information supplied from the coefficient ROMs 60a and 60b.
(+1/0) is supplied to the shift register 63. The replacement unit 62 replaces the coefficients supplied from each of the coefficient ROMs 60a and 60b, and supplies the coefficients to the shift register 63 and the interpolation unit 64. The shift register 63 shifts the coefficients according to the shift control signal C1 and supplies the coefficients to the interpolation unit 64 in order to adjust the scale between the coefficients to be interpolated. The interpolation unit 64 performs linear interpolation between data according to the supplied coefficients.

Next, FIG. 13 is a block diagram showing the configuration of the convolution operation unit of the sampling frequency conversion device according to the third modification. Parts corresponding to those in FIG. 6 are denoted by the same reference numerals, and description thereof is omitted. In the figure, the shift register 65 at the last stage in the convolution operation unit is provided with a shift control signal C2 (−1 /
0), and shifts and outputs the data. In the convolution operation, since the calculation is performed from both sides (the coefficient value is small), the number of times of shifting down increases on both sides, and as a result, the compression is decompressed.

As described above, in the third modification, the coefficients used for linear interpolation are compressed and stored in the coefficient ROM, so that a limited storage capacity can be used effectively.

The first modification to the third modification can be individually combined with the embodiment shown in FIG. 6, but all of them can be combined.

[0043]

As described above, according to the present invention, according to the present invention, the first interpolation ratio generating means for obtaining the interpolation point between the input data inputted by the first clock is used. Is generated by the coefficient generation means based on the first interpolation ratio, and a pair of coefficient sets for obtaining the oversampling point is generated. A second interpolation ratio of an interpolation point is generated, and the interpolation means linearly interpolates between the pair of coefficient sets based on the second interpolation ratio.
The value of the interpolation point linearly interpolated by the interpolation means is convoluted with the input data and output as output data.Therefore, there is an advantage that the operation can be speeded up without increasing the scale of hardware. can get.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a sampling frequency conversion device according to an embodiment of the present invention.

FIG. 2 is a conceptual diagram for explaining a method of calculating an interpolation ratio Δt in a PLL of a sampling frequency conversion device.

FIG. 3 is a block diagram illustrating a configuration example of a PLL.

FIG. 4 shows a data amount ΔS and a gain Gain (△) of a FIFO.
It is a conceptual diagram which shows the correspondence relationship with S).

FIG. 5 is a conceptual diagram for explaining a method of calculating an interpolation ratio a used in linear interpolation in an 8 × oversampling / linear interpolation unit.

FIG. 6 is a block diagram illustrating a configuration example of an 8 × oversampling / linear interpolation unit.

FIG. 7 is a conceptual diagram for explaining coefficients stored in a coefficient ROM.

FIG. 8 is a block diagram showing a configuration according to a first modified example.

FIG. 9 is a conceptual diagram for explaining coefficients stored in a coefficient ROM according to a first modification.

FIG. 10 is a block diagram illustrating the concept of an arithmetic unit according to the embodiment and an arithmetic unit according to the second modified example.

FIG. 11 is a conceptual diagram for explaining coefficient compression.

FIG. 12 is a block diagram showing a configuration (linear interpolation unit) according to a third modification.

FIG. 13 shows a configuration according to a third modification (convolution operation unit).
FIG.

FIG. 14 is a block diagram illustrating a configuration of a conventional sampling frequency conversion device.

FIG. 15 is a block diagram showing a configuration for realizing oversampling + linear interpolation by a conventional sampling frequency conversion device.

FIG. 16 is a conceptual diagram for explaining conventional oversampling + linear interpolation.

[Explanation of symbols]

Reference Signs List 20 FIFO 21 read / write counter (first interpolation ratio generation unit) 22 PLL (first interpolation ratio generation unit) 23 O / S coefficient designation / interpolation ratio generation unit (second interpolation ratio generation unit) 24 8 times Oversampling / linear interpolation unit (interpolation means, calculation means) 31 ROM read control unit (coefficient generation means) 32 coefficient ROM (coefficient generation means, storage means) 60a, 60b coefficient ROM (first storage means, second storage) means)

Claims (5)

[Claims] 1. A first interpolation ratio generating means for generating a first interpolation ratio for obtaining an interpolation point between input data inputted by a first clock, based on the first interpolation ratio, Coefficient generation means for generating a pair of coefficient sets for obtaining an oversampling point; and second interpolation for generating a second interpolation ratio of interpolation points between oversampling points based on the first interpolation ratio. A ratio generating unit; an interpolating unit that linearly interpolates between a pair of coefficient sets generated by the coefficient generating unit based on the second interpolation ratio generated by the second interpolation ratio generating unit; And a calculating means for convolving the value of the interpolation point linearly interpolated by the interpolating means with the input data in accordance with the clock, and outputting the result as output data. Location. 2. The sampling frequency conversion device according to claim 1, wherein said coefficient generation means includes storage means for storing a plurality of pairs of coefficient sets corresponding to said first interpolation ratio. 3. The coefficient generation means includes: first storage means for storing a coefficient for calculating an even-numbered oversampling point in the pair of coefficient sets; And second storage means for storing a coefficient for calculating an odd-numbered oversampling point. Based on the first interpolation ratio, the coefficient stored in the first storage means and the second 2. The method according to claim 1, wherein the coefficients are read out in pairs with the coefficients stored in the storage means.
The sampling frequency converter according to the above. 4. The sampling frequency conversion device according to claim 1, wherein said coefficient generation means includes a storage means for storing half of said pair of coefficient sets. 5. The sampling frequency conversion apparatus according to claim 1, wherein said coefficient generation means includes storage means for compressing and storing said pair of coefficient sets by a power of two.